[PATCH] D127195: [CodeEmitter] Fix encoding wide instructions on big-endian hosts

[Jay Foad via Phabricator via llvm-commits]

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For instructions wider than 64 bits the InstBits table is initialized in
64-bit chunks from APInt::getRawData, but it was being read with
LoadIntFromMemory which is byte-based.

Fix this by reading the table with the APInt constructor that takes an
ArrayRef to the raw data instead.

This is currently NFC for in-tree targets but fixes AMDGPU failures on
big-endian hosts that were caused by D126483 <https://reviews.llvm.org/D126483> until it was reverted.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D127195

Files:
  llvm/utils/TableGen/CodeEmitterGen.cpp


Index: llvm/utils/TableGen/CodeEmitterGen.cpp
===================================================================
--- llvm/utils/TableGen/CodeEmitterGen.cpp
+++ llvm/utils/TableGen/CodeEmitterGen.cpp
@@ -482,14 +482,12 @@
     // Emit initial function code
     if (UseAPInt) {
       int NumWords = APInt::getNumWords(BitWidth);
-      int NumBytes = (BitWidth + 7) / 8;
       o << "  const unsigned opcode = MI.getOpcode();\n"
-        << "  if (Inst.getBitWidth() != " << BitWidth << ")\n"
-        << "    Inst = Inst.zext(" << BitWidth << ");\n"
         << "  if (Scratch.getBitWidth() != " << BitWidth << ")\n"
         << "    Scratch = Scratch.zext(" << BitWidth << ");\n"
-        << "  LoadIntFromMemory(Inst, (const uint8_t *)&InstBits[opcode * "
-        << NumWords << "], " << NumBytes << ");\n"
+        << "  Inst = APInt(" << BitWidth
+        << ", makeArrayRef(InstBits + opcode * " << NumWords << ", " << NumWords
+        << "));\n"
         << "  APInt &Value = Inst;\n"
         << "  APInt &op = Scratch;\n"
         << "  switch (opcode) {\n";


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