[PATCH] D127154: [AArch64] Remove isDef32

Tue Jun 7 02:40:48 PDT 2022

dmgreen added inline comments.

================
Comment at: llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp:209
+static bool isFreeZExtOfGPR32(MachineInstr *MI, MachineRegisterInfo *MRI) {
+  // A COPY from and FPR will become a FMOVSWr.
+  if (MI->getOpcode() == TargetOpcode::COPY &&
----------------
efriedma wrote:
> It's not clear to me we'll always end up with an FMOVSWr, given copy coalescing.
> 
> You could explicitly select an FMOVSWr here, but I guess that has other consequences for register allocation...
We can try it and see how it goes. I'm hoping it is fairly rare that it both is used by a redundant ORR and has negative consequences for register allocation.

================
Comment at: llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp:218
+  }
+  return MI->getOpcode() > TargetOpcode::GENERIC_OP_END;
+}
----------------
efriedma wrote:
> Should we check for pseudo-instructions here?  Are there any pseudo-instructions which might produce a register with undefined high bits?
Do you mean the AArch64 pseudos? Do you have any instructions in mind?

This is a list of the pseudos, minus the SVE instructions and G_ pseudos:
```
ADDSWrr     = 249,
ADDSXrr     = 250,
ADDWrr      = 251,
ADDXrr      = 252,
ADDlowTLS   = 257,
ADJCALLSTACKDOWN    = 258,
ADJCALLSTACKUP      = 259,
AESIMCrrTied        = 260,
AESMCrrTied = 261,
ANDSWrr     = 262,
ANDSXrr     = 263,
ANDWrr      = 264,
ANDXrr      = 265,
BICSWrr     = 286,
BICSXrr     = 287,
BICWrr      = 288,
BICXrr      = 289,
BLRNoIP     = 294,
BLR_BTI     = 295,
BLR_RVMARKER        = 296,
BSPv16i8    = 297,
BSPv8i8     = 298,
CATCHRET    = 299,
CLEANUPRET  = 300,
CMP_SWAP_128        = 309,
CMP_SWAP_128_ACQUIRE        = 310,
CMP_SWAP_128_MONOTONIC      = 311,
CMP_SWAP_128_RELEASE        = 312,
CMP_SWAP_16 = 313,
CMP_SWAP_32 = 314,
CMP_SWAP_64 = 315,
CMP_SWAP_8  = 316,
CompilerBarrier     = 325,
EMITBKEY    = 326,
EONWrr      = 327,
EONXrr      = 328,
EORWrr      = 329,
EORXrr      = 330,
F128CSEL    = 335,
FMOVD0      = 440,
FMOVH0      = 441,
FMOVS0      = 442,
HOM_Epilog  = 671,
HOM_Prolog  = 672,
HWASAN_CHECK_MEMACCESS      = 673,
HWASAN_CHECK_MEMACCESS_SHORTGRANULES
IRGstack    = 675,
JumpTableDest16     = 676,
JumpTableDest32     = 677,
JumpTableDest8      = 678,
LOADgot     = 730,
MOPSMemoryCopyPseudo        = 755,
MOPSMemoryMovePseudo        = 756,
MOPSMemorySetPseudo = 757,
MOPSMemorySetTaggingPseudo  = 758,
MOVMCSym    = 759,
MOVaddr     = 760,
MOVaddrBA   = 761,
MOVaddrCP   = 762,
MOVaddrEXT  = 763,
MOVaddrJT   = 764,
MOVaddrTLS  = 765,
MOVbaseTLS  = 766,
MOVi32imm   = 767,
MOVi64imm   = 768,
ORNWrr      = 781,
ORNXrr      = 782,
ORRWrr      = 783,
ORNXrr      = 782,
ORRWrr      = 783,
ORRXrr      = 784,
RET_ReallyLR        = 791,
SEH_AddFP   = 805,
SEH_EpilogEnd       = 806,
SEH_EpilogStart     = 807,
SEH_Nop     = 808,
SEH_PrologEnd       = 809,
SEH_SaveFPLR        = 810,
SEH_SaveFPLR_X      = 811,
SEH_SaveFReg        = 812,
SEH_SaveFRegP       = 813,
SEH_SaveFRegP_X     = 814,
SEH_SaveFReg_X      = 815,
SEH_SaveReg = 816,
SEH_SaveRegP        = 817,
SEH_SaveRegP_X      = 818,
SEH_SaveReg_X       = 819,
SEH_SetFP   = 820,
SEH_StackAlloc      = 821,
SPACE       = 834,
TGloop
STGloop_wback       = 868,
STZGloop    = 872,
STZGloop_wback      = 873,
SUBSWrr     = 878,
SUBSXrr     = 879,
SUBWrr      = 880,
SUBXrr      = 881,
SpeculationBarrierISBDSBEndBB       = 892,
SpeculationBarrierSBEndBB   = 893,
SpeculationSafeValueW       = 894,
SpeculationSafeValueX       = 895,
StoreSwiftAsyncContext      = 896,
TAGPstack   = 897,
TCRETURNdi  = 898,
TCRETURNri  = 899,
TCRETURNriALL       = 900,
TCRETURNriBTI       = 901,
TLSDESCCALL = 902,
TLSDESC_CALLSEQ     = 903,
```

Most don't def a GPR32, and the ones that do (ADDWrr and friends, MOVi32imm) should be OK as far as I understand, as they always become W instructions.

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D127154/new/

https://reviews.llvm.org/D127154