[PATCH] D126952: [DAGCombiner] Remove overzealous assertion when folding assert+trunc+assert (PR55846)

[Nikita Popov via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
nikic marked an inline comment as done.
Closed by commit rG5a64bc207ee0: [DAGCombiner] Remove overzealous assertion when folding assert+trunc+assert… (authored by nikic).

Changed prior to commit:
  https://reviews.llvm.org/D126952?vs=433986&id=434716#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D126952/new/

https://reviews.llvm.org/D126952

Files:
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/test/CodeGen/X86/pr55846.ll


Index: llvm/test/CodeGen/X86/pr55846.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/X86/pr55846.ll
@@ -0,0 +1,26 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck %s
+
+; After legalization, this could be: "i8 truncate (i64 AssertZext X, Type: i9)"
+; The AssertZext does not add information, so it should be eliminated,
+; but that must not trigger a compile-time assert.
+
+define void @test(i64* %p) {
+; CHECK-LABEL: test:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    movl $256, %eax # imm = 0x100
+; CHECK-NEXT:    movq %rax, (%rdi)
+; CHECK-NEXT:    retq
+  %sel = select i1 true, i64 256, i64 0
+  br label %bb2
+
+bb2:
+  store i64 %sel, i64* %p, align 4
+  %p.bc = bitcast i64* %p to <2 x i1>*
+  %load = load <2 x i1>, <2 x i1>* %p.bc, align 1
+  br label %bb3
+
+bb3:
+  %use = add <2 x i1> %load, zeroinitializer
+  ret void
+}
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -12508,13 +12508,9 @@
     // This eliminates the later assert:
     // assert (trunc (assert X, i8) to iN), i1 --> trunc (assert X, i1) to iN
     // assert (trunc (assert X, i1) to iN), i8 --> trunc (assert X, i1) to iN
+    SDLoc DL(N);
     SDValue BigA = N0.getOperand(0);
     EVT BigA_AssertVT = cast<VTSDNode>(BigA.getOperand(1))->getVT();
-    assert(BigA_AssertVT.bitsLE(N0.getValueType()) &&
-           "Asserting zero/sign-extended bits to a type larger than the "
-           "truncated destination does not provide information");
-
-    SDLoc DL(N);
     EVT MinAssertVT = AssertVT.bitsLT(BigA_AssertVT) ? AssertVT : BigA_AssertVT;
     SDValue MinAssertVTVal = DAG.getValueType(MinAssertVT);
     SDValue NewAssert = DAG.getNode(Opcode, DL, BigA.getValueType(),
@@ -12530,10 +12526,6 @@
       Opcode == ISD::AssertZext) {
     SDValue BigA = N0.getOperand(0);
     EVT BigA_AssertVT = cast<VTSDNode>(BigA.getOperand(1))->getVT();
-    assert(BigA_AssertVT.bitsLE(N0.getValueType()) &&
-           "Asserting zero/sign-extended bits to a type larger than the "
-           "truncated destination does not provide information");
-
     if (AssertVT.bitsLT(BigA_AssertVT)) {
       SDLoc DL(N);
       SDValue NewAssert = DAG.getNode(Opcode, DL, BigA.getValueType(),


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