[llvm] 576b824 - [WebAssembly][NFC] RelaxedBinary tablegen multiclass for relaxed SIMD

[Thomas Lively via llvm-commits]

Author: Thomas Lively
Date: 2022-06-06T17:56:39-07:00
New Revision: 576b8245c838e822f709d8450f537c7909d45411

URL: https://github.com/llvm/llvm-project/commit/576b8245c838e822f709d8450f537c7909d45411
DIFF: https://github.com/llvm/llvm-project/commit/576b8245c838e822f709d8450f537c7909d45411.diff

LOG: [WebAssembly][NFC] RelaxedBinary tablegen multiclass for relaxed SIMD

Refactor the tablegen definitions for relaxed SIMD min/max instructions to use a
shared RelaxedBinary multiclass modeled on the existing SIMDBinary multiclass. A
future commit will add further instruction definitions that use RelaxedBinary.

Also rename the SIMD_RELAXED_CONVERT multiclass to RelaxedConvert to better fit
existing naming conventions.

Reviewed By: aheejin

Differential Revision: https://reviews.llvm.org/D127157

Added: 
    

Modified: 
    llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td

Removed: 
    


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diff  --git a/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td b/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
index 98944fcc4c941..6fcf91e27f435 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
@@ -1347,21 +1347,21 @@ defm RELAXED_SWIZZLE :
 // Relaxed floating-point to int conversions
 //===----------------------------------------------------------------------===//
 
-multiclass SIMD_RELAXED_CONVERT<Vec vec, Vec arg, SDPatternOperator op, string name, bits<32> simdop> {
+multiclass RelaxedConvert<Vec vec, Vec arg, SDPatternOperator op, string name, bits<32> simdop> {
   defm op#_#vec :
     RELAXED_I<(outs V128:$dst), (ins V128:$vec), (outs), (ins),
               [(set (vec.vt V128:$dst), (vec.vt (op (arg.vt V128:$vec))))],
               vec.prefix#"."#name#"\t$dst, $vec", vec.prefix#"."#name, simdop>;
 }
 
-defm "" : SIMD_RELAXED_CONVERT<I32x4, F32x4, int_wasm_relaxed_trunc_signed,
-                               "relaxed_trunc_f32x4_s", 0x101>;
-defm "" : SIMD_RELAXED_CONVERT<I32x4, F32x4, int_wasm_relaxed_trunc_unsigned,
-                               "relaxed_trunc_f32x4_u", 0x102>;
-defm "" : SIMD_RELAXED_CONVERT<I32x4, F64x2, int_wasm_relaxed_trunc_signed_zero,
-                               "relaxed_trunc_f64x2_s_zero", 0x103>;
-defm "" : SIMD_RELAXED_CONVERT<I32x4, F64x2, int_wasm_relaxed_trunc_unsigned_zero,
-                               "relaxed_trunc_f64x2_u_zero", 0x104>;
+defm "" : RelaxedConvert<I32x4, F32x4, int_wasm_relaxed_trunc_signed,
+                         "relaxed_trunc_f32x4_s", 0x101>;
+defm "" : RelaxedConvert<I32x4, F32x4, int_wasm_relaxed_trunc_unsigned,
+                         "relaxed_trunc_f32x4_u", 0x102>;
+defm "" : RelaxedConvert<I32x4, F64x2, int_wasm_relaxed_trunc_signed_zero,
+                         "relaxed_trunc_f64x2_s_zero", 0x103>;
+defm "" : RelaxedConvert<I32x4, F64x2, int_wasm_relaxed_trunc_unsigned_zero,
+                         "relaxed_trunc_f64x2_u_zero", 0x104>;
 
 //===----------------------------------------------------------------------===//
 // Relaxed Fused Multiply- Add and Subtract (FMA/FMS)
@@ -1408,18 +1408,21 @@ defm "" : SIMDLANESELECT<I64x2, 0x10c>;
 // Relaxed floating-point min and max.
 //===----------------------------------------------------------------------===//
 
-multiclass SIMD_RELAXED_FMINMAX<Vec vec, bits<32> simdopMin, bits<32> simdopMax> {
-  defm RELAXED_FMIN_#vec :
-    RELAXED_I<(outs V128:$dst), (ins V128:$a, V128:$b), (outs), (ins),
-              [(set (vec.vt V128:$dst), (int_wasm_relaxed_min
-                (vec.vt V128:$a), (vec.vt V128:$b)))],
-              vec.prefix#".relaxed_min\t$dst, $a, $b", vec.prefix#".relaxed_min", simdopMin>;
-  defm RELAXED_FMAX_#vec :
-    RELAXED_I<(outs V128:$dst), (ins V128:$a, V128:$b), (outs), (ins),
-              [(set (vec.vt V128:$dst), (int_wasm_relaxed_max
-                (vec.vt V128:$a), (vec.vt V128:$b)))],
-              vec.prefix#".relaxed_max\t$dst, $a, $b", vec.prefix#".relaxed_max", simdopMax>;
+multiclass RelaxedBinary<Vec vec, SDPatternOperator node, string name,
+                         bits<32> simdop> {
+  defm _#vec : RELAXED_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs),
+                         (outs), (ins),
+                         [(set (vec.vt V128:$dst),
+                           (node (vec.vt V128:$lhs), (vec.vt V128:$rhs)))],
+                         vec.prefix#"."#name#"\t$dst, $lhs, $rhs",
+                         vec.prefix#"."#name, simdop>;
 }
 
-defm "" : SIMD_RELAXED_FMINMAX<F32x4, 0x10d, 0x10e>;
-defm "" : SIMD_RELAXED_FMINMAX<F64x2, 0x10f, 0x110>;
+defm SIMD_RELAXED_FMIN :
+   RelaxedBinary<F32x4, int_wasm_relaxed_min, "relaxed_min", 0x10d>;
+defm SIMD_RELAXED_FMAX :
+   RelaxedBinary<F32x4, int_wasm_relaxed_max, "relaxed_max", 0x10e>;
+defm SIMD_RELAXED_FMIN :
+   RelaxedBinary<F64x2, int_wasm_relaxed_min, "relaxed_min", 0x10f>;
+defm SIMD_RELAXED_FMAX :
+   RelaxedBinary<F64x2, int_wasm_relaxed_max, "relaxed_max", 0x110>;