[PATCH] D126896: [DAGCombiner][RISCV] Improve computeKnownBits for (smax X, C) where C is non-negative.

[Jay Foad via Phabricator via llvm-commits]

foad added inline comments.


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Comment at: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:3709
+        Known.Zero.setHighBits(std::min(SignBits, ValueLow.getNumSignBits()));
+        break;
+      }
----------------
craig.topper wrote:
> foad wrote:
> > If you break here you don't call smin/smax below, which could compute known low order bits in the result. Wouldn't it be better to add this new code after the calls to smin/smax below, to improve the result that they calculate?
> I suppose so. I hadn't realized we could compute the lower order bits. I guess there's no test coverage for the constant case. Does the same issue exist with the clamp pattern code that was already here?
Yes, it looks like that has the same problem.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D126896/new/

https://reviews.llvm.org/D126896