[PATCH] D127122: [InstCombine] reduce right-shift-of-left-shifted constant via demanded bits

[Sanjay Patel via Phabricator via llvm-commits]

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If we don't demand high bits (zeros) and it is valid to pre-shift a constant:
(C2 << X) >> C1 <https://reviews.llvm.org/C1> --> (C2 >> C1 <https://reviews.llvm.org/C1>) << X

https://alive2.llvm.org/ce/z/ZCgqj5

There are a variety of related patterns, but I haven't found a single solution that gets all of the motivating examples - so pulling this piece out of D126617 <https://reviews.llvm.org/D126617> along with more tests.

We should also handle the case where we shift-right followed by shift-left, but I'll make that a follow-on patch assuming this one is ok. It seems likely that we would want to add this to the SDAG version of the code too to keep it on par with IR.


https://reviews.llvm.org/D127122

Files:
  llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
  llvm/test/Transforms/InstCombine/shift-shift.ll

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