[PATCH] D127112: llvm-reduce: Don't set generic instruction operands to undef

[Matt Arsenault via Phabricator via llvm-commits]

arsenm created this revision.
arsenm added reviewers: qcolombet, paquette, aemerson, markus, MatzeB.
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The intention is that these should never have undef operands. It turns
out the restriction the verifier enforces is too lax. The verifier
enforces that registers without a register class cannot be undef, but
it's valid to use a register with a register class and type. The
verifier needs to change to be based on the opcode.


https://reviews.llvm.org/D127112

Files:
  llvm/test/tools/llvm-reduce/mir/generic-vreg.mir
  llvm/test/tools/llvm-reduce/mir/reduce-register-uses-generic.mir
  llvm/tools/llvm-reduce/deltas/ReduceRegisterUses.cpp


Index: llvm/tools/llvm-reduce/deltas/ReduceRegisterUses.cpp
===================================================================
--- llvm/tools/llvm-reduce/deltas/ReduceRegisterUses.cpp
+++ llvm/tools/llvm-reduce/deltas/ReduceRegisterUses.cpp
@@ -22,6 +22,10 @@
 
   for (MachineBasicBlock &MBB : MF) {
     for (MachineInstr &MI : MBB) {
+      // Generic instructions are not supposed to have undef operands.
+      if (isPreISelGenericOpcode(MI.getOpcode()))
+        continue;
+
       int NumOperands = MI.getNumOperands();
       int NumRequiredOps = MI.getNumExplicitOperands() +
                            MI.getDesc().getNumImplicitDefs() +
Index: llvm/test/tools/llvm-reduce/mir/reduce-register-uses-generic.mir
===================================================================
--- /dev/null
+++ llvm/test/tools/llvm-reduce/mir/reduce-register-uses-generic.mir
@@ -0,0 +1,25 @@
+# REQUIRES: amdgpu-registered-target
+# RUN: llvm-reduce -abort-on-invalid-reduction -simplify-mir --delta-passes=register-uses -mtriple=amdgcn-amd-amdhsa --test FileCheck --test-arg --check-prefix=CHECK-INTERESTINGNESS --test-arg %s --test-arg --input-file %s -o %t 2> %t.log
+# RUN: FileCheck --match-full-lines --check-prefix=RESULT %s < %t
+
+# Generic instructions should not have undef set on operands
+# CHECK-INTERESTINGNESS: G_ADD
+
+# RESULT: %1:vreg_64(s64) = IMPLICIT_DEF
+# RESULT: %add:_(s64) = G_ADD %1, %1
+
+---
+name: func
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $vgpr0, $vgpr1, $vgpr2_vgpr3
+
+    %0:vgpr(s32) = G_IMPLICIT_DEF
+    %1:vreg_64(s64) = IMPLICIT_DEF
+    %add:_(s64) = G_ADD %1, %1
+    %ptr:_(p1) = G_IMPLICIT_DEF
+    G_STORE %0(s32), %ptr(p1) :: (store (s32), addrspace 1)
+    S_ENDPGM 0, implicit %add(s64), implicit %1(s64)
+
+...
Index: llvm/test/tools/llvm-reduce/mir/generic-vreg.mir
===================================================================
--- llvm/test/tools/llvm-reduce/mir/generic-vreg.mir
+++ llvm/test/tools/llvm-reduce/mir/generic-vreg.mir
@@ -1,5 +1,5 @@
 # REQUIRES: amdgpu-registered-target
-# RUN: llvm-reduce -mtriple=amdgcn-amd-amdhsa --test FileCheck --test-arg --check-prefix=CHECK-INTERESTINGNESS --test-arg %s --test-arg --input-file %s -o %t 2> %t.log
+# RUN: llvm-reduce -abort-on-invalid-reduction -mtriple=amdgcn-amd-amdhsa --test FileCheck --test-arg --check-prefix=CHECK-INTERESTINGNESS --test-arg %s --test-arg --input-file %s -o %t 2> %t.log
 # RUN: FileCheck --match-full-lines --check-prefix=RESULT %s < %t
 
 # Verify that reduction works with generic virtual registers, and the


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