[llvm] 84bacb1 - [RISCV] Use check-prefixes to reduce check lines
Shao-Ce SUN via llvm-commits
llvm-commits at lists.llvm.org
Mon Jun 6 00:59:29 PDT 2022
Author: Shao-Ce SUN
Date: 2022-06-06T15:59:15+08:00
New Revision: 84bacb18c6c50c303bf90243019643ede91676c1
URL: https://github.com/llvm/llvm-project/commit/84bacb18c6c50c303bf90243019643ede91676c1
DIFF: https://github.com/llvm/llvm-project/commit/84bacb18c6c50c303bf90243019643ede91676c1.diff
LOG: [RISCV] Use check-prefixes to reduce check lines
Reviewed By: frasercrmck
Differential Revision: https://reviews.llvm.org/D125083
Added:
Modified:
llvm/test/CodeGen/RISCV/double-arith-strict.ll
llvm/test/CodeGen/RISCV/double-arith.ll
llvm/test/CodeGen/RISCV/double-convert-strict.ll
llvm/test/CodeGen/RISCV/double-convert.ll
llvm/test/CodeGen/RISCV/double-fcmp-strict.ll
llvm/test/CodeGen/RISCV/double-fcmp.ll
llvm/test/CodeGen/RISCV/double-imm.ll
llvm/test/CodeGen/RISCV/double-intrinsics-strict.ll
llvm/test/CodeGen/RISCV/double-intrinsics.ll
llvm/test/CodeGen/RISCV/double-isnan.ll
llvm/test/CodeGen/RISCV/double-mem.ll
llvm/test/CodeGen/RISCV/double-round-conv-sat.ll
llvm/test/CodeGen/RISCV/double-round-conv.ll
llvm/test/CodeGen/RISCV/double-select-fcmp.ll
llvm/test/CodeGen/RISCV/float-arith-strict.ll
llvm/test/CodeGen/RISCV/float-arith.ll
llvm/test/CodeGen/RISCV/float-convert-strict.ll
llvm/test/CodeGen/RISCV/float-convert.ll
llvm/test/CodeGen/RISCV/float-fcmp-strict.ll
llvm/test/CodeGen/RISCV/float-fcmp.ll
llvm/test/CodeGen/RISCV/float-imm.ll
llvm/test/CodeGen/RISCV/float-intrinsics-strict.ll
llvm/test/CodeGen/RISCV/float-isnan.ll
llvm/test/CodeGen/RISCV/float-mem.ll
llvm/test/CodeGen/RISCV/float-round-conv-sat.ll
llvm/test/CodeGen/RISCV/float-select-fcmp.ll
llvm/test/CodeGen/RISCV/half-arith-strict.ll
llvm/test/CodeGen/RISCV/half-arith.ll
llvm/test/CodeGen/RISCV/half-convert-strict.ll
llvm/test/CodeGen/RISCV/half-convert.ll
llvm/test/CodeGen/RISCV/half-fcmp-strict.ll
llvm/test/CodeGen/RISCV/half-fcmp.ll
llvm/test/CodeGen/RISCV/half-imm.ll
llvm/test/CodeGen/RISCV/half-intrinsics.ll
llvm/test/CodeGen/RISCV/half-isnan.ll
llvm/test/CodeGen/RISCV/half-mem.ll
llvm/test/CodeGen/RISCV/half-round-conv-sat.ll
llvm/test/CodeGen/RISCV/half-round-conv.ll
llvm/test/CodeGen/RISCV/half-select-fcmp.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/RISCV/double-arith-strict.ll b/llvm/test/CodeGen/RISCV/double-arith-strict.ll
index 915b63588d5a..eb9721a104b4 100644
--- a/llvm/test/CodeGen/RISCV/double-arith-strict.ll
+++ b/llvm/test/CodeGen/RISCV/double-arith-strict.ll
@@ -1,25 +1,20 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \
; RUN: -disable-strictnode-mutation -target-abi=ilp32d \
-; RUN: | FileCheck -check-prefix=RV32IFD %s
+; RUN: | FileCheck -check-prefixes=CHECKIFD,RV32IFD %s
; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \
; RUN: -disable-strictnode-mutation -target-abi=lp64d \
-; RUN: | FileCheck -check-prefix=RV64IFD %s
+; RUN: | FileCheck -check-prefixes=CHECKIFD,RV64IFD %s
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: -disable-strictnode-mutation | FileCheck -check-prefix=RV32I %s
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: -disable-strictnode-mutation | FileCheck -check-prefix=RV64I %s
define double @fadd_d(double %a, double %b) nounwind strictfp {
-; RV32IFD-LABEL: fadd_d:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: fadd.d fa0, fa0, fa1
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: fadd_d:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fadd.d fa0, fa0, fa1
-; RV64IFD-NEXT: ret
+; CHECKIFD-LABEL: fadd_d:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: fadd.d fa0, fa0, fa1
+; CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fadd_d:
; RV32I: # %bb.0:
@@ -44,15 +39,10 @@ define double @fadd_d(double %a, double %b) nounwind strictfp {
declare double @llvm.experimental.constrained.fadd.f64(double, double, metadata, metadata)
define double @fsub_d(double %a, double %b) nounwind strictfp {
-; RV32IFD-LABEL: fsub_d:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: fsub.d fa0, fa0, fa1
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: fsub_d:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fsub.d fa0, fa0, fa1
-; RV64IFD-NEXT: ret
+; CHECKIFD-LABEL: fsub_d:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: fsub.d fa0, fa0, fa1
+; CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fsub_d:
; RV32I: # %bb.0:
@@ -77,15 +67,10 @@ define double @fsub_d(double %a, double %b) nounwind strictfp {
declare double @llvm.experimental.constrained.fsub.f64(double, double, metadata, metadata)
define double @fmul_d(double %a, double %b) nounwind strictfp {
-; RV32IFD-LABEL: fmul_d:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: fmul.d fa0, fa0, fa1
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: fmul_d:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fmul.d fa0, fa0, fa1
-; RV64IFD-NEXT: ret
+; CHECKIFD-LABEL: fmul_d:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: fmul.d fa0, fa0, fa1
+; CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fmul_d:
; RV32I: # %bb.0:
@@ -110,15 +95,10 @@ define double @fmul_d(double %a, double %b) nounwind strictfp {
declare double @llvm.experimental.constrained.fmul.f64(double, double, metadata, metadata)
define double @fdiv_d(double %a, double %b) nounwind strictfp {
-; RV32IFD-LABEL: fdiv_d:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: fdiv.d fa0, fa0, fa1
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: fdiv_d:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fdiv.d fa0, fa0, fa1
-; RV64IFD-NEXT: ret
+; CHECKIFD-LABEL: fdiv_d:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: fdiv.d fa0, fa0, fa1
+; CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fdiv_d:
; RV32I: # %bb.0:
@@ -143,15 +123,10 @@ define double @fdiv_d(double %a, double %b) nounwind strictfp {
declare double @llvm.experimental.constrained.fdiv.f64(double, double, metadata, metadata)
define double @fsqrt_d(double %a) nounwind strictfp {
-; RV32IFD-LABEL: fsqrt_d:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: fsqrt.d fa0, fa0
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: fsqrt_d:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fsqrt.d fa0, fa0
-; RV64IFD-NEXT: ret
+; CHECKIFD-LABEL: fsqrt_d:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: fsqrt.d fa0, fa0
+; CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fsqrt_d:
; RV32I: # %bb.0:
@@ -258,15 +233,10 @@ define double @fmax_d(double %a, double %b) nounwind strictfp {
declare double @llvm.experimental.constrained.maxnum.f64(double, double, metadata) strictfp
define double @fmadd_d(double %a, double %b, double %c) nounwind strictfp {
-; RV32IFD-LABEL: fmadd_d:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: fmadd.d fa0, fa0, fa1, fa2
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: fmadd_d:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fmadd.d fa0, fa0, fa1, fa2
-; RV64IFD-NEXT: ret
+; CHECKIFD-LABEL: fmadd_d:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: fmadd.d fa0, fa0, fa1, fa2
+; CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fmadd_d:
; RV32I: # %bb.0:
diff --git a/llvm/test/CodeGen/RISCV/double-arith.ll b/llvm/test/CodeGen/RISCV/double-arith.ll
index dafb39d7a670..dc3228586d6d 100644
--- a/llvm/test/CodeGen/RISCV/double-arith.ll
+++ b/llvm/test/CodeGen/RISCV/double-arith.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \
-; RUN: -target-abi=ilp32d | FileCheck -check-prefix=RV32IFD %s
+; RUN: -target-abi=ilp32d | FileCheck -check-prefixes=CHECKIFD,RV32IFD %s
; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \
-; RUN: -target-abi=lp64d | FileCheck -check-prefix=RV64IFD %s
+; RUN: -target-abi=lp64d | FileCheck -check-prefixes=CHECKIFD,RV64IFD %s
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32I %s
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
@@ -14,15 +14,10 @@
; instructions that don't directly match a RISC-V instruction.
define double @fadd_d(double %a, double %b) nounwind {
-; RV32IFD-LABEL: fadd_d:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: fadd.d fa0, fa0, fa1
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: fadd_d:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fadd.d fa0, fa0, fa1
-; RV64IFD-NEXT: ret
+; CHECKIFD-LABEL: fadd_d:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: fadd.d fa0, fa0, fa1
+; CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fadd_d:
; RV32I: # %bb.0:
@@ -46,15 +41,10 @@ define double @fadd_d(double %a, double %b) nounwind {
}
define double @fsub_d(double %a, double %b) nounwind {
-; RV32IFD-LABEL: fsub_d:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: fsub.d fa0, fa0, fa1
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: fsub_d:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fsub.d fa0, fa0, fa1
-; RV64IFD-NEXT: ret
+; CHECKIFD-LABEL: fsub_d:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: fsub.d fa0, fa0, fa1
+; CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fsub_d:
; RV32I: # %bb.0:
@@ -78,15 +68,10 @@ define double @fsub_d(double %a, double %b) nounwind {
}
define double @fmul_d(double %a, double %b) nounwind {
-; RV32IFD-LABEL: fmul_d:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: fmul.d fa0, fa0, fa1
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: fmul_d:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fmul.d fa0, fa0, fa1
-; RV64IFD-NEXT: ret
+; CHECKIFD-LABEL: fmul_d:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: fmul.d fa0, fa0, fa1
+; CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fmul_d:
; RV32I: # %bb.0:
@@ -110,15 +95,10 @@ define double @fmul_d(double %a, double %b) nounwind {
}
define double @fdiv_d(double %a, double %b) nounwind {
-; RV32IFD-LABEL: fdiv_d:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: fdiv.d fa0, fa0, fa1
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: fdiv_d:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fdiv.d fa0, fa0, fa1
-; RV64IFD-NEXT: ret
+; CHECKIFD-LABEL: fdiv_d:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: fdiv.d fa0, fa0, fa1
+; CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fdiv_d:
; RV32I: # %bb.0:
@@ -144,15 +124,10 @@ define double @fdiv_d(double %a, double %b) nounwind {
declare double @llvm.sqrt.f64(double)
define double @fsqrt_d(double %a) nounwind {
-; RV32IFD-LABEL: fsqrt_d:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: fsqrt.d fa0, fa0
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: fsqrt_d:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fsqrt.d fa0, fa0
-; RV64IFD-NEXT: ret
+; CHECKIFD-LABEL: fsqrt_d:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: fsqrt.d fa0, fa0
+; CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fsqrt_d:
; RV32I: # %bb.0:
@@ -178,15 +153,10 @@ define double @fsqrt_d(double %a) nounwind {
declare double @llvm.copysign.f64(double, double)
define double @fsgnj_d(double %a, double %b) nounwind {
-; RV32IFD-LABEL: fsgnj_d:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: fsgnj.d fa0, fa0, fa1
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: fsgnj_d:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fsgnj.d fa0, fa0, fa1
-; RV64IFD-NEXT: ret
+; CHECKIFD-LABEL: fsgnj_d:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: fsgnj.d fa0, fa0, fa1
+; CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fsgnj_d:
; RV32I: # %bb.0:
@@ -212,19 +182,12 @@ define double @fsgnj_d(double %a, double %b) nounwind {
; This function performs extra work to ensure that
; DAGCombiner::visitBITCAST doesn't replace the fneg with an xor.
define i32 @fneg_d(double %a, double %b) nounwind {
-; RV32IFD-LABEL: fneg_d:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: fadd.d ft0, fa0, fa0
-; RV32IFD-NEXT: fneg.d ft1, ft0
-; RV32IFD-NEXT: feq.d a0, ft0, ft1
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: fneg_d:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fadd.d ft0, fa0, fa0
-; RV64IFD-NEXT: fneg.d ft1, ft0
-; RV64IFD-NEXT: feq.d a0, ft0, ft1
-; RV64IFD-NEXT: ret
+; CHECKIFD-LABEL: fneg_d:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: fadd.d ft0, fa0, fa0
+; CHECKIFD-NEXT: fneg.d ft1, ft0
+; CHECKIFD-NEXT: feq.d a0, ft0, ft1
+; CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fneg_d:
; RV32I: # %bb.0:
@@ -267,15 +230,10 @@ define double @fsgnjn_d(double %a, double %b) nounwind {
; TODO: fsgnjn.s isn't selected on RV64 because DAGCombiner::visitBITCAST will
; convert (bitconvert (fneg x)) to a xor.
;
-; RV32IFD-LABEL: fsgnjn_d:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: fsgnjn.d fa0, fa0, fa1
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: fsgnjn_d:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fsgnjn.d fa0, fa0, fa1
-; RV64IFD-NEXT: ret
+; CHECKIFD-LABEL: fsgnjn_d:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: fsgnjn.d fa0, fa0, fa1
+; CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fsgnjn_d:
; RV32I: # %bb.0:
@@ -306,19 +264,12 @@ declare double @llvm.fabs.f64(double)
; This function performs extra work to ensure that
; DAGCombiner::visitBITCAST doesn't replace the fabs with an and.
define double @fabs_d(double %a, double %b) nounwind {
-; RV32IFD-LABEL: fabs_d:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: fadd.d ft0, fa0, fa1
-; RV32IFD-NEXT: fabs.d ft1, ft0
-; RV32IFD-NEXT: fadd.d fa0, ft1, ft0
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: fabs_d:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fadd.d ft0, fa0, fa1
-; RV64IFD-NEXT: fabs.d ft1, ft0
-; RV64IFD-NEXT: fadd.d fa0, ft1, ft0
-; RV64IFD-NEXT: ret
+; CHECKIFD-LABEL: fabs_d:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: fadd.d ft0, fa0, fa1
+; CHECKIFD-NEXT: fabs.d ft1, ft0
+; CHECKIFD-NEXT: fadd.d fa0, ft1, ft0
+; CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fabs_d:
; RV32I: # %bb.0:
@@ -355,15 +306,10 @@ define double @fabs_d(double %a, double %b) nounwind {
declare double @llvm.minnum.f64(double, double)
define double @fmin_d(double %a, double %b) nounwind {
-; RV32IFD-LABEL: fmin_d:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: fmin.d fa0, fa0, fa1
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: fmin_d:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fmin.d fa0, fa0, fa1
-; RV64IFD-NEXT: ret
+; CHECKIFD-LABEL: fmin_d:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: fmin.d fa0, fa0, fa1
+; CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fmin_d:
; RV32I: # %bb.0:
@@ -389,15 +335,10 @@ define double @fmin_d(double %a, double %b) nounwind {
declare double @llvm.maxnum.f64(double, double)
define double @fmax_d(double %a, double %b) nounwind {
-; RV32IFD-LABEL: fmax_d:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: fmax.d fa0, fa0, fa1
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: fmax_d:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fmax.d fa0, fa0, fa1
-; RV64IFD-NEXT: ret
+; CHECKIFD-LABEL: fmax_d:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: fmax.d fa0, fa0, fa1
+; CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fmax_d:
; RV32I: # %bb.0:
@@ -423,15 +364,10 @@ define double @fmax_d(double %a, double %b) nounwind {
declare double @llvm.fma.f64(double, double, double)
define double @fmadd_d(double %a, double %b, double %c) nounwind {
-; RV32IFD-LABEL: fmadd_d:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: fmadd.d fa0, fa0, fa1, fa2
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: fmadd_d:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fmadd.d fa0, fa0, fa1, fa2
-; RV64IFD-NEXT: ret
+; CHECKIFD-LABEL: fmadd_d:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: fmadd.d fa0, fa0, fa1, fa2
+; CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fmadd_d:
; RV32I: # %bb.0:
@@ -951,15 +887,10 @@ define double @fnmsub_d_2(double %a, double %b, double %c) nounwind {
}
define double @fmadd_d_contract(double %a, double %b, double %c) nounwind {
-; RV32IFD-LABEL: fmadd_d_contract:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: fmadd.d fa0, fa0, fa1, fa2
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: fmadd_d_contract:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fmadd.d fa0, fa0, fa1, fa2
-; RV64IFD-NEXT: ret
+; CHECKIFD-LABEL: fmadd_d_contract:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: fmadd.d fa0, fa0, fa1, fa2
+; CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fmadd_d_contract:
; RV32I: # %bb.0:
diff --git a/llvm/test/CodeGen/RISCV/double-convert-strict.ll b/llvm/test/CodeGen/RISCV/double-convert-strict.ll
index 52f7d16d42c0..3e3f8c33e3c2 100644
--- a/llvm/test/CodeGen/RISCV/double-convert-strict.ll
+++ b/llvm/test/CodeGen/RISCV/double-convert-strict.ll
@@ -1,10 +1,10 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \
; RUN: -disable-strictnode-mutation -target-abi=ilp32d \
-; RUN: | FileCheck -check-prefix=RV32IFD %s
+; RUN: | FileCheck -check-prefixes=CHECKIFD,RV32IFD %s
; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \
; RUN: -disable-strictnode-mutation -target-abi=lp64d \
-; RUN: | FileCheck -check-prefix=RV64IFD %s
+; RUN: | FileCheck -check-prefixes=CHECKIFD,RV64IFD %s
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: -disable-strictnode-mutation | FileCheck -check-prefix=RV32I %s
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
@@ -15,15 +15,10 @@
; support rounding mode.
define float @fcvt_s_d(double %a) nounwind strictfp {
-; RV32IFD-LABEL: fcvt_s_d:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: fcvt.s.d fa0, fa0
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: fcvt_s_d:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fcvt.s.d fa0, fa0
-; RV64IFD-NEXT: ret
+; CHECKIFD-LABEL: fcvt_s_d:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: fcvt.s.d fa0, fa0
+; CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fcvt_s_d:
; RV32I: # %bb.0:
@@ -48,15 +43,10 @@ define float @fcvt_s_d(double %a) nounwind strictfp {
declare float @llvm.experimental.constrained.fptrunc.f32.f64(double, metadata, metadata)
define double @fcvt_d_s(float %a) nounwind strictfp {
-; RV32IFD-LABEL: fcvt_d_s:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: fcvt.d.s fa0, fa0
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: fcvt_d_s:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fcvt.d.s fa0, fa0
-; RV64IFD-NEXT: ret
+; CHECKIFD-LABEL: fcvt_d_s:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: fcvt.d.s fa0, fa0
+; CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fcvt_d_s:
; RV32I: # %bb.0:
@@ -81,15 +71,10 @@ define double @fcvt_d_s(float %a) nounwind strictfp {
declare double @llvm.experimental.constrained.fpext.f64.f32(float, metadata)
define i32 @fcvt_w_d(double %a) nounwind strictfp {
-; RV32IFD-LABEL: fcvt_w_d:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: fcvt.w.d a0, fa0, rtz
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: fcvt_w_d:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fcvt.w.d a0, fa0, rtz
-; RV64IFD-NEXT: ret
+; CHECKIFD-LABEL: fcvt_w_d:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: fcvt.w.d a0, fa0, rtz
+; CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fcvt_w_d:
; RV32I: # %bb.0:
@@ -116,15 +101,10 @@ declare i32 @llvm.experimental.constrained.fptosi.i32.f64(double, metadata)
; For RV64D, fcvt.lu.d is semantically equivalent to fcvt.wu.d in this case
; because fptosi will produce poison if the result doesn't fit into an i32.
define i32 @fcvt_wu_d(double %a) nounwind strictfp {
-; RV32IFD-LABEL: fcvt_wu_d:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: fcvt.wu.d a0, fa0, rtz
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: fcvt_wu_d:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fcvt.wu.d a0, fa0, rtz
-; RV64IFD-NEXT: ret
+; CHECKIFD-LABEL: fcvt_wu_d:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: fcvt.wu.d a0, fa0, rtz
+; CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fcvt_wu_d:
; RV32I: # %bb.0:
@@ -151,25 +131,15 @@ declare i32 @llvm.experimental.constrained.fptoui.i32.f64(double, metadata)
; Test where the fptoui has multiple uses, one of which causes a sext to be
; inserted on RV64.
define i32 @fcvt_wu_d_multiple_use(double %x, i32* %y) nounwind {
-; RV32IFD-LABEL: fcvt_wu_d_multiple_use:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: fcvt.wu.d a1, fa0, rtz
-; RV32IFD-NEXT: li a0, 1
-; RV32IFD-NEXT: beqz a1, .LBB4_2
-; RV32IFD-NEXT: # %bb.1:
-; RV32IFD-NEXT: mv a0, a1
-; RV32IFD-NEXT: .LBB4_2:
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: fcvt_wu_d_multiple_use:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fcvt.wu.d a1, fa0, rtz
-; RV64IFD-NEXT: li a0, 1
-; RV64IFD-NEXT: beqz a1, .LBB4_2
-; RV64IFD-NEXT: # %bb.1:
-; RV64IFD-NEXT: mv a0, a1
-; RV64IFD-NEXT: .LBB4_2:
-; RV64IFD-NEXT: ret
+; CHECKIFD-LABEL: fcvt_wu_d_multiple_use:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: fcvt.wu.d a1, fa0, rtz
+; CHECKIFD-NEXT: li a0, 1
+; CHECKIFD-NEXT: beqz a1, .LBB4_2
+; CHECKIFD-NEXT: # %bb.1:
+; CHECKIFD-NEXT: mv a0, a1
+; CHECKIFD-NEXT: .LBB4_2:
+; CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fcvt_wu_d_multiple_use:
; RV32I: # %bb.0:
@@ -207,15 +177,10 @@ define i32 @fcvt_wu_d_multiple_use(double %x, i32* %y) nounwind {
}
define double @fcvt_d_w(i32 %a) nounwind strictfp {
-; RV32IFD-LABEL: fcvt_d_w:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: fcvt.d.w fa0, a0
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: fcvt_d_w:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fcvt.d.w fa0, a0
-; RV64IFD-NEXT: ret
+; CHECKIFD-LABEL: fcvt_d_w:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: fcvt.d.w fa0, a0
+; CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fcvt_d_w:
; RV32I: # %bb.0:
@@ -241,17 +206,11 @@ define double @fcvt_d_w(i32 %a) nounwind strictfp {
declare double @llvm.experimental.constrained.sitofp.f64.i32(i32, metadata, metadata)
define double @fcvt_d_w_load(i32* %p) nounwind strictfp {
-; RV32IFD-LABEL: fcvt_d_w_load:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: lw a0, 0(a0)
-; RV32IFD-NEXT: fcvt.d.w fa0, a0
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: fcvt_d_w_load:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: lw a0, 0(a0)
-; RV64IFD-NEXT: fcvt.d.w fa0, a0
-; RV64IFD-NEXT: ret
+; CHECKIFD-LABEL: fcvt_d_w_load:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: lw a0, 0(a0)
+; CHECKIFD-NEXT: fcvt.d.w fa0, a0
+; CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fcvt_d_w_load:
; RV32I: # %bb.0:
@@ -278,15 +237,10 @@ define double @fcvt_d_w_load(i32* %p) nounwind strictfp {
}
define double @fcvt_d_wu(i32 %a) nounwind strictfp {
-; RV32IFD-LABEL: fcvt_d_wu:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: fcvt.d.wu fa0, a0
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: fcvt_d_wu:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fcvt.d.wu fa0, a0
-; RV64IFD-NEXT: ret
+; CHECKIFD-LABEL: fcvt_d_wu:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: fcvt.d.wu fa0, a0
+; CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fcvt_d_wu:
; RV32I: # %bb.0:
@@ -497,15 +451,10 @@ define double @fcvt_d_lu(i64 %a) nounwind strictfp {
declare double @llvm.experimental.constrained.uitofp.f64.i64(i64, metadata, metadata)
define double @fcvt_d_w_i8(i8 signext %a) nounwind strictfp {
-; RV32IFD-LABEL: fcvt_d_w_i8:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: fcvt.d.w fa0, a0
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: fcvt_d_w_i8:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fcvt.d.w fa0, a0
-; RV64IFD-NEXT: ret
+; CHECKIFD-LABEL: fcvt_d_w_i8:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: fcvt.d.w fa0, a0
+; CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fcvt_d_w_i8:
; RV32I: # %bb.0:
@@ -530,15 +479,10 @@ define double @fcvt_d_w_i8(i8 signext %a) nounwind strictfp {
declare double @llvm.experimental.constrained.sitofp.f64.i8(i8, metadata, metadata)
define double @fcvt_d_wu_i8(i8 zeroext %a) nounwind strictfp {
-; RV32IFD-LABEL: fcvt_d_wu_i8:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: fcvt.d.wu fa0, a0
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: fcvt_d_wu_i8:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fcvt.d.wu fa0, a0
-; RV64IFD-NEXT: ret
+; CHECKIFD-LABEL: fcvt_d_wu_i8:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: fcvt.d.wu fa0, a0
+; CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fcvt_d_wu_i8:
; RV32I: # %bb.0:
@@ -563,15 +507,10 @@ define double @fcvt_d_wu_i8(i8 zeroext %a) nounwind strictfp {
declare double @llvm.experimental.constrained.uitofp.f64.i8(i8, metadata, metadata)
define double @fcvt_d_w_i16(i16 signext %a) nounwind strictfp {
-; RV32IFD-LABEL: fcvt_d_w_i16:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: fcvt.d.w fa0, a0
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: fcvt_d_w_i16:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fcvt.d.w fa0, a0
-; RV64IFD-NEXT: ret
+; CHECKIFD-LABEL: fcvt_d_w_i16:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: fcvt.d.w fa0, a0
+; CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fcvt_d_w_i16:
; RV32I: # %bb.0:
@@ -596,15 +535,10 @@ define double @fcvt_d_w_i16(i16 signext %a) nounwind strictfp {
declare double @llvm.experimental.constrained.sitofp.f64.i16(i16, metadata, metadata)
define double @fcvt_d_wu_i16(i16 zeroext %a) nounwind strictfp {
-; RV32IFD-LABEL: fcvt_d_wu_i16:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: fcvt.d.wu fa0, a0
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: fcvt_d_wu_i16:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fcvt.d.wu fa0, a0
-; RV64IFD-NEXT: ret
+; CHECKIFD-LABEL: fcvt_d_wu_i16:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: fcvt.d.wu fa0, a0
+; CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fcvt_d_wu_i16:
; RV32I: # %bb.0:
diff --git a/llvm/test/CodeGen/RISCV/double-convert.ll b/llvm/test/CodeGen/RISCV/double-convert.ll
index 46fb6cd9e52d..d413bd2fd4de 100644
--- a/llvm/test/CodeGen/RISCV/double-convert.ll
+++ b/llvm/test/CodeGen/RISCV/double-convert.ll
@@ -1,23 +1,18 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \
-; RUN: -target-abi=ilp32d | FileCheck -check-prefix=RV32IFD %s
+; RUN: -target-abi=ilp32d | FileCheck -check-prefixes=CHECKIFD,RV32IFD %s
; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \
-; RUN: -target-abi=lp64d | FileCheck -check-prefix=RV64IFD %s
+; RUN: -target-abi=lp64d | FileCheck -check-prefixes=CHECKIFD,RV64IFD %s
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32I %s
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64I %s
define float @fcvt_s_d(double %a) nounwind {
-; RV32IFD-LABEL: fcvt_s_d:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: fcvt.s.d fa0, fa0
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: fcvt_s_d:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fcvt.s.d fa0, fa0
-; RV64IFD-NEXT: ret
+; CHECKIFD-LABEL: fcvt_s_d:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: fcvt.s.d fa0, fa0
+; CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fcvt_s_d:
; RV32I: # %bb.0:
@@ -41,15 +36,10 @@ define float @fcvt_s_d(double %a) nounwind {
}
define double @fcvt_d_s(float %a) nounwind {
-; RV32IFD-LABEL: fcvt_d_s:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: fcvt.d.s fa0, fa0
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: fcvt_d_s:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fcvt.d.s fa0, fa0
-; RV64IFD-NEXT: ret
+; CHECKIFD-LABEL: fcvt_d_s:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: fcvt.d.s fa0, fa0
+; CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fcvt_d_s:
; RV32I: # %bb.0:
@@ -73,15 +63,10 @@ define double @fcvt_d_s(float %a) nounwind {
}
define i32 @fcvt_w_d(double %a) nounwind {
-; RV32IFD-LABEL: fcvt_w_d:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: fcvt.w.d a0, fa0, rtz
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: fcvt_w_d:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fcvt.w.d a0, fa0, rtz
-; RV64IFD-NEXT: ret
+; CHECKIFD-LABEL: fcvt_w_d:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: fcvt.w.d a0, fa0, rtz
+; CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fcvt_w_d:
; RV32I: # %bb.0:
@@ -105,23 +90,14 @@ define i32 @fcvt_w_d(double %a) nounwind {
}
define i32 @fcvt_w_d_sat(double %a) nounwind {
-; RV32IFD-LABEL: fcvt_w_d_sat:
-; RV32IFD: # %bb.0: # %start
-; RV32IFD-NEXT: feq.d a0, fa0, fa0
-; RV32IFD-NEXT: beqz a0, .LBB3_2
-; RV32IFD-NEXT: # %bb.1:
-; RV32IFD-NEXT: fcvt.w.d a0, fa0, rtz
-; RV32IFD-NEXT: .LBB3_2: # %start
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: fcvt_w_d_sat:
-; RV64IFD: # %bb.0: # %start
-; RV64IFD-NEXT: feq.d a0, fa0, fa0
-; RV64IFD-NEXT: beqz a0, .LBB3_2
-; RV64IFD-NEXT: # %bb.1:
-; RV64IFD-NEXT: fcvt.w.d a0, fa0, rtz
-; RV64IFD-NEXT: .LBB3_2: # %start
-; RV64IFD-NEXT: ret
+; CHECKIFD-LABEL: fcvt_w_d_sat:
+; CHECKIFD: # %bb.0: # %start
+; CHECKIFD-NEXT: feq.d a0, fa0, fa0
+; CHECKIFD-NEXT: beqz a0, .LBB3_2
+; CHECKIFD-NEXT: # %bb.1:
+; CHECKIFD-NEXT: fcvt.w.d a0, fa0, rtz
+; CHECKIFD-NEXT: .LBB3_2: # %start
+; CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fcvt_w_d_sat:
; RV32I: # %bb.0: # %start
@@ -238,15 +214,10 @@ declare i32 @llvm.fptosi.sat.i32.f64(double)
; For RV64D, fcvt.lu.d is semantically equivalent to fcvt.wu.d in this case
; because fptosi will produce poison if the result doesn't fit into an i32.
define i32 @fcvt_wu_d(double %a) nounwind {
-; RV32IFD-LABEL: fcvt_wu_d:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: fcvt.wu.d a0, fa0, rtz
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: fcvt_wu_d:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fcvt.wu.d a0, fa0, rtz
-; RV64IFD-NEXT: ret
+; CHECKIFD-LABEL: fcvt_wu_d:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: fcvt.wu.d a0, fa0, rtz
+; CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fcvt_wu_d:
; RV32I: # %bb.0:
@@ -272,25 +243,15 @@ define i32 @fcvt_wu_d(double %a) nounwind {
; Test where the fptoui has multiple uses, one of which causes a sext to be
; inserted on RV64.
define i32 @fcvt_wu_d_multiple_use(double %x, i32* %y) nounwind {
-; RV32IFD-LABEL: fcvt_wu_d_multiple_use:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: fcvt.wu.d a1, fa0, rtz
-; RV32IFD-NEXT: li a0, 1
-; RV32IFD-NEXT: beqz a1, .LBB5_2
-; RV32IFD-NEXT: # %bb.1:
-; RV32IFD-NEXT: mv a0, a1
-; RV32IFD-NEXT: .LBB5_2:
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: fcvt_wu_d_multiple_use:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fcvt.wu.d a1, fa0, rtz
-; RV64IFD-NEXT: li a0, 1
-; RV64IFD-NEXT: beqz a1, .LBB5_2
-; RV64IFD-NEXT: # %bb.1:
-; RV64IFD-NEXT: mv a0, a1
-; RV64IFD-NEXT: .LBB5_2:
-; RV64IFD-NEXT: ret
+; CHECKIFD-LABEL: fcvt_wu_d_multiple_use:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: fcvt.wu.d a1, fa0, rtz
+; CHECKIFD-NEXT: li a0, 1
+; CHECKIFD-NEXT: beqz a1, .LBB5_2
+; CHECKIFD-NEXT: # %bb.1:
+; CHECKIFD-NEXT: mv a0, a1
+; CHECKIFD-NEXT: .LBB5_2:
+; CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fcvt_wu_d_multiple_use:
; RV32I: # %bb.0:
@@ -328,23 +289,14 @@ define i32 @fcvt_wu_d_multiple_use(double %x, i32* %y) nounwind {
}
define i32 @fcvt_wu_d_sat(double %a) nounwind {
-; RV32IFD-LABEL: fcvt_wu_d_sat:
-; RV32IFD: # %bb.0: # %start
-; RV32IFD-NEXT: feq.d a0, fa0, fa0
-; RV32IFD-NEXT: beqz a0, .LBB6_2
-; RV32IFD-NEXT: # %bb.1:
-; RV32IFD-NEXT: fcvt.wu.d a0, fa0, rtz
-; RV32IFD-NEXT: .LBB6_2: # %start
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: fcvt_wu_d_sat:
-; RV64IFD: # %bb.0: # %start
-; RV64IFD-NEXT: feq.d a0, fa0, fa0
-; RV64IFD-NEXT: beqz a0, .LBB6_2
-; RV64IFD-NEXT: # %bb.1:
-; RV64IFD-NEXT: fcvt.wu.d a0, fa0, rtz
-; RV64IFD-NEXT: .LBB6_2: # %start
-; RV64IFD-NEXT: ret
+; CHECKIFD-LABEL: fcvt_wu_d_sat:
+; CHECKIFD: # %bb.0: # %start
+; CHECKIFD-NEXT: feq.d a0, fa0, fa0
+; CHECKIFD-NEXT: beqz a0, .LBB6_2
+; CHECKIFD-NEXT: # %bb.1:
+; CHECKIFD-NEXT: fcvt.wu.d a0, fa0, rtz
+; CHECKIFD-NEXT: .LBB6_2: # %start
+; CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fcvt_wu_d_sat:
; RV32I: # %bb.0: # %start
@@ -432,15 +384,10 @@ start:
declare i32 @llvm.fptoui.sat.i32.f64(double)
define double @fcvt_d_w(i32 %a) nounwind {
-; RV32IFD-LABEL: fcvt_d_w:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: fcvt.d.w fa0, a0
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: fcvt_d_w:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fcvt.d.w fa0, a0
-; RV64IFD-NEXT: ret
+; CHECKIFD-LABEL: fcvt_d_w:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: fcvt.d.w fa0, a0
+; CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fcvt_d_w:
; RV32I: # %bb.0:
@@ -465,17 +412,11 @@ define double @fcvt_d_w(i32 %a) nounwind {
}
define double @fcvt_d_w_load(i32* %p) nounwind {
-; RV32IFD-LABEL: fcvt_d_w_load:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: lw a0, 0(a0)
-; RV32IFD-NEXT: fcvt.d.w fa0, a0
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: fcvt_d_w_load:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: lw a0, 0(a0)
-; RV64IFD-NEXT: fcvt.d.w fa0, a0
-; RV64IFD-NEXT: ret
+; CHECKIFD-LABEL: fcvt_d_w_load:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: lw a0, 0(a0)
+; CHECKIFD-NEXT: fcvt.d.w fa0, a0
+; CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fcvt_d_w_load:
; RV32I: # %bb.0:
@@ -502,15 +443,10 @@ define double @fcvt_d_w_load(i32* %p) nounwind {
}
define double @fcvt_d_wu(i32 %a) nounwind {
-; RV32IFD-LABEL: fcvt_d_wu:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: fcvt.d.wu fa0, a0
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: fcvt_d_wu:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fcvt.d.wu fa0, a0
-; RV64IFD-NEXT: ret
+; CHECKIFD-LABEL: fcvt_d_wu:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: fcvt.d.wu fa0, a0
+; CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fcvt_d_wu:
; RV32I: # %bb.0:
@@ -1184,15 +1120,10 @@ define double @fmv_d_x(i64 %a, i64 %b) nounwind {
}
define double @fcvt_d_w_i8(i8 signext %a) nounwind {
-; RV32IFD-LABEL: fcvt_d_w_i8:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: fcvt.d.w fa0, a0
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: fcvt_d_w_i8:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fcvt.d.w fa0, a0
-; RV64IFD-NEXT: ret
+; CHECKIFD-LABEL: fcvt_d_w_i8:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: fcvt.d.w fa0, a0
+; CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fcvt_d_w_i8:
; RV32I: # %bb.0:
@@ -1216,15 +1147,10 @@ define double @fcvt_d_w_i8(i8 signext %a) nounwind {
}
define double @fcvt_d_wu_i8(i8 zeroext %a) nounwind {
-; RV32IFD-LABEL: fcvt_d_wu_i8:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: fcvt.d.wu fa0, a0
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: fcvt_d_wu_i8:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fcvt.d.wu fa0, a0
-; RV64IFD-NEXT: ret
+; CHECKIFD-LABEL: fcvt_d_wu_i8:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: fcvt.d.wu fa0, a0
+; CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fcvt_d_wu_i8:
; RV32I: # %bb.0:
@@ -1248,15 +1174,10 @@ define double @fcvt_d_wu_i8(i8 zeroext %a) nounwind {
}
define double @fcvt_d_w_i16(i16 signext %a) nounwind {
-; RV32IFD-LABEL: fcvt_d_w_i16:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: fcvt.d.w fa0, a0
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: fcvt_d_w_i16:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fcvt.d.w fa0, a0
-; RV64IFD-NEXT: ret
+; CHECKIFD-LABEL: fcvt_d_w_i16:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: fcvt.d.w fa0, a0
+; CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fcvt_d_w_i16:
; RV32I: # %bb.0:
@@ -1280,15 +1201,10 @@ define double @fcvt_d_w_i16(i16 signext %a) nounwind {
}
define double @fcvt_d_wu_i16(i16 zeroext %a) nounwind {
-; RV32IFD-LABEL: fcvt_d_wu_i16:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: fcvt.d.wu fa0, a0
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: fcvt_d_wu_i16:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fcvt.d.wu fa0, a0
-; RV64IFD-NEXT: ret
+; CHECKIFD-LABEL: fcvt_d_wu_i16:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: fcvt.d.wu fa0, a0
+; CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fcvt_d_wu_i16:
; RV32I: # %bb.0:
diff --git a/llvm/test/CodeGen/RISCV/double-fcmp-strict.ll b/llvm/test/CodeGen/RISCV/double-fcmp-strict.ll
index 254bd5c183bf..3aa6d54332bc 100644
--- a/llvm/test/CodeGen/RISCV/double-fcmp-strict.ll
+++ b/llvm/test/CodeGen/RISCV/double-fcmp-strict.ll
@@ -1,25 +1,20 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \
; RUN: -disable-strictnode-mutation -target-abi=ilp32d \
-; RUN: | FileCheck -check-prefix=RV32IFD %s
+; RUN: | FileCheck -check-prefix=CHECKIFD %s
; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \
; RUN: -disable-strictnode-mutation -target-abi=lp64d \
-; RUN: | FileCheck -check-prefix=RV64IFD %s
+; RUN: | FileCheck -check-prefix=CHECKIFD %s
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: -disable-strictnode-mutation | FileCheck -check-prefix=RV32I %s
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: -disable-strictnode-mutation | FileCheck -check-prefix=RV64I %s
define i32 @fcmp_oeq(double %a, double %b) nounwind strictfp {
-; RV32IFD-LABEL: fcmp_oeq:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: feq.d a0, fa0, fa1
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: fcmp_oeq:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: feq.d a0, fa0, fa1
-; RV64IFD-NEXT: ret
+; CHECKIFD-LABEL: fcmp_oeq:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: feq.d a0, fa0, fa1
+; CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fcmp_oeq:
; RV32I: # %bb.0:
@@ -47,21 +42,13 @@ define i32 @fcmp_oeq(double %a, double %b) nounwind strictfp {
declare i1 @llvm.experimental.constrained.fcmp.f64(double, double, metadata, metadata)
define i32 @fcmp_ogt(double %a, double %b) nounwind strictfp {
-; RV32IFD-LABEL: fcmp_ogt:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: frflags a1
-; RV32IFD-NEXT: flt.d a0, fa1, fa0
-; RV32IFD-NEXT: fsflags a1
-; RV32IFD-NEXT: feq.d zero, fa1, fa0
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: fcmp_ogt:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: frflags a1
-; RV64IFD-NEXT: flt.d a0, fa1, fa0
-; RV64IFD-NEXT: fsflags a1
-; RV64IFD-NEXT: feq.d zero, fa1, fa0
-; RV64IFD-NEXT: ret
+; CHECKIFD-LABEL: fcmp_ogt:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: frflags a1
+; CHECKIFD-NEXT: flt.d a0, fa1, fa0
+; CHECKIFD-NEXT: fsflags a1
+; CHECKIFD-NEXT: feq.d zero, fa1, fa0
+; CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fcmp_ogt:
; RV32I: # %bb.0:
@@ -88,21 +75,13 @@ define i32 @fcmp_ogt(double %a, double %b) nounwind strictfp {
}
define i32 @fcmp_oge(double %a, double %b) nounwind strictfp {
-; RV32IFD-LABEL: fcmp_oge:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: frflags a1
-; RV32IFD-NEXT: fle.d a0, fa1, fa0
-; RV32IFD-NEXT: fsflags a1
-; RV32IFD-NEXT: feq.d zero, fa1, fa0
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: fcmp_oge:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: frflags a1
-; RV64IFD-NEXT: fle.d a0, fa1, fa0
-; RV64IFD-NEXT: fsflags a1
-; RV64IFD-NEXT: feq.d zero, fa1, fa0
-; RV64IFD-NEXT: ret
+; CHECKIFD-LABEL: fcmp_oge:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: frflags a1
+; CHECKIFD-NEXT: fle.d a0, fa1, fa0
+; CHECKIFD-NEXT: fsflags a1
+; CHECKIFD-NEXT: feq.d zero, fa1, fa0
+; CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fcmp_oge:
; RV32I: # %bb.0:
@@ -131,21 +110,13 @@ define i32 @fcmp_oge(double %a, double %b) nounwind strictfp {
}
define i32 @fcmp_olt(double %a, double %b) nounwind strictfp {
-; RV32IFD-LABEL: fcmp_olt:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: frflags a1
-; RV32IFD-NEXT: flt.d a0, fa0, fa1
-; RV32IFD-NEXT: fsflags a1
-; RV32IFD-NEXT: feq.d zero, fa0, fa1
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: fcmp_olt:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: frflags a1
-; RV64IFD-NEXT: flt.d a0, fa0, fa1
-; RV64IFD-NEXT: fsflags a1
-; RV64IFD-NEXT: feq.d zero, fa0, fa1
-; RV64IFD-NEXT: ret
+; CHECKIFD-LABEL: fcmp_olt:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: frflags a1
+; CHECKIFD-NEXT: flt.d a0, fa0, fa1
+; CHECKIFD-NEXT: fsflags a1
+; CHECKIFD-NEXT: feq.d zero, fa0, fa1
+; CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fcmp_olt:
; RV32I: # %bb.0:
@@ -172,21 +143,13 @@ define i32 @fcmp_olt(double %a, double %b) nounwind strictfp {
}
define i32 @fcmp_ole(double %a, double %b) nounwind strictfp {
-; RV32IFD-LABEL: fcmp_ole:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: frflags a1
-; RV32IFD-NEXT: fle.d a0, fa0, fa1
-; RV32IFD-NEXT: fsflags a1
-; RV32IFD-NEXT: feq.d zero, fa0, fa1
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: fcmp_ole:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: frflags a1
-; RV64IFD-NEXT: fle.d a0, fa0, fa1
-; RV64IFD-NEXT: fsflags a1
-; RV64IFD-NEXT: feq.d zero, fa0, fa1
-; RV64IFD-NEXT: ret
+; CHECKIFD-LABEL: fcmp_ole:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: frflags a1
+; CHECKIFD-NEXT: fle.d a0, fa0, fa1
+; CHECKIFD-NEXT: fsflags a1
+; CHECKIFD-NEXT: feq.d zero, fa0, fa1
+; CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fcmp_ole:
; RV32I: # %bb.0:
@@ -215,31 +178,18 @@ define i32 @fcmp_ole(double %a, double %b) nounwind strictfp {
; FIXME: We only need one frflags before the two flts and one fsflags after the
; two flts.
define i32 @fcmp_one(double %a, double %b) nounwind strictfp {
-; RV32IFD-LABEL: fcmp_one:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: frflags a0
-; RV32IFD-NEXT: flt.d a1, fa0, fa1
-; RV32IFD-NEXT: fsflags a0
-; RV32IFD-NEXT: feq.d zero, fa0, fa1
-; RV32IFD-NEXT: frflags a0
-; RV32IFD-NEXT: flt.d a2, fa1, fa0
-; RV32IFD-NEXT: fsflags a0
-; RV32IFD-NEXT: or a0, a2, a1
-; RV32IFD-NEXT: feq.d zero, fa1, fa0
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: fcmp_one:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: frflags a0
-; RV64IFD-NEXT: flt.d a1, fa0, fa1
-; RV64IFD-NEXT: fsflags a0
-; RV64IFD-NEXT: feq.d zero, fa0, fa1
-; RV64IFD-NEXT: frflags a0
-; RV64IFD-NEXT: flt.d a2, fa1, fa0
-; RV64IFD-NEXT: fsflags a0
-; RV64IFD-NEXT: or a0, a2, a1
-; RV64IFD-NEXT: feq.d zero, fa1, fa0
-; RV64IFD-NEXT: ret
+; CHECKIFD-LABEL: fcmp_one:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: frflags a0
+; CHECKIFD-NEXT: flt.d a1, fa0, fa1
+; CHECKIFD-NEXT: fsflags a0
+; CHECKIFD-NEXT: feq.d zero, fa0, fa1
+; CHECKIFD-NEXT: frflags a0
+; CHECKIFD-NEXT: flt.d a2, fa1, fa0
+; CHECKIFD-NEXT: fsflags a0
+; CHECKIFD-NEXT: or a0, a2, a1
+; CHECKIFD-NEXT: feq.d zero, fa1, fa0
+; CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fcmp_one:
; RV32I: # %bb.0:
@@ -300,19 +250,12 @@ define i32 @fcmp_one(double %a, double %b) nounwind strictfp {
}
define i32 @fcmp_ord(double %a, double %b) nounwind strictfp {
-; RV32IFD-LABEL: fcmp_ord:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: feq.d a0, fa1, fa1
-; RV32IFD-NEXT: feq.d a1, fa0, fa0
-; RV32IFD-NEXT: and a0, a1, a0
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: fcmp_ord:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: feq.d a0, fa1, fa1
-; RV64IFD-NEXT: feq.d a1, fa0, fa0
-; RV64IFD-NEXT: and a0, a1, a0
-; RV64IFD-NEXT: ret
+; CHECKIFD-LABEL: fcmp_ord:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: feq.d a0, fa1, fa1
+; CHECKIFD-NEXT: feq.d a1, fa0, fa0
+; CHECKIFD-NEXT: and a0, a1, a0
+; CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fcmp_ord:
; RV32I: # %bb.0:
@@ -341,33 +284,19 @@ define i32 @fcmp_ord(double %a, double %b) nounwind strictfp {
; FIXME: We only need one frflags before the two flts and one fsflags after the
; two flts.
define i32 @fcmp_ueq(double %a, double %b) nounwind strictfp {
-; RV32IFD-LABEL: fcmp_ueq:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: frflags a0
-; RV32IFD-NEXT: flt.d a1, fa0, fa1
-; RV32IFD-NEXT: fsflags a0
-; RV32IFD-NEXT: feq.d zero, fa0, fa1
-; RV32IFD-NEXT: frflags a0
-; RV32IFD-NEXT: flt.d a2, fa1, fa0
-; RV32IFD-NEXT: fsflags a0
-; RV32IFD-NEXT: or a0, a2, a1
-; RV32IFD-NEXT: xori a0, a0, 1
-; RV32IFD-NEXT: feq.d zero, fa1, fa0
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: fcmp_ueq:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: frflags a0
-; RV64IFD-NEXT: flt.d a1, fa0, fa1
-; RV64IFD-NEXT: fsflags a0
-; RV64IFD-NEXT: feq.d zero, fa0, fa1
-; RV64IFD-NEXT: frflags a0
-; RV64IFD-NEXT: flt.d a2, fa1, fa0
-; RV64IFD-NEXT: fsflags a0
-; RV64IFD-NEXT: or a0, a2, a1
-; RV64IFD-NEXT: xori a0, a0, 1
-; RV64IFD-NEXT: feq.d zero, fa1, fa0
-; RV64IFD-NEXT: ret
+; CHECKIFD-LABEL: fcmp_ueq:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: frflags a0
+; CHECKIFD-NEXT: flt.d a1, fa0, fa1
+; CHECKIFD-NEXT: fsflags a0
+; CHECKIFD-NEXT: feq.d zero, fa0, fa1
+; CHECKIFD-NEXT: frflags a0
+; CHECKIFD-NEXT: flt.d a2, fa1, fa0
+; CHECKIFD-NEXT: fsflags a0
+; CHECKIFD-NEXT: or a0, a2, a1
+; CHECKIFD-NEXT: xori a0, a0, 1
+; CHECKIFD-NEXT: feq.d zero, fa1, fa0
+; CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fcmp_ueq:
; RV32I: # %bb.0:
@@ -428,23 +357,14 @@ define i32 @fcmp_ueq(double %a, double %b) nounwind strictfp {
}
define i32 @fcmp_ugt(double %a, double %b) nounwind strictfp {
-; RV32IFD-LABEL: fcmp_ugt:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: frflags a0
-; RV32IFD-NEXT: fle.d a1, fa0, fa1
-; RV32IFD-NEXT: fsflags a0
-; RV32IFD-NEXT: xori a0, a1, 1
-; RV32IFD-NEXT: feq.d zero, fa0, fa1
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: fcmp_ugt:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: frflags a0
-; RV64IFD-NEXT: fle.d a1, fa0, fa1
-; RV64IFD-NEXT: fsflags a0
-; RV64IFD-NEXT: xori a0, a1, 1
-; RV64IFD-NEXT: feq.d zero, fa0, fa1
-; RV64IFD-NEXT: ret
+; CHECKIFD-LABEL: fcmp_ugt:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: frflags a0
+; CHECKIFD-NEXT: fle.d a1, fa0, fa1
+; CHECKIFD-NEXT: fsflags a0
+; CHECKIFD-NEXT: xori a0, a1, 1
+; CHECKIFD-NEXT: feq.d zero, fa0, fa1
+; CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fcmp_ugt:
; RV32I: # %bb.0:
@@ -471,23 +391,14 @@ define i32 @fcmp_ugt(double %a, double %b) nounwind strictfp {
}
define i32 @fcmp_uge(double %a, double %b) nounwind strictfp {
-; RV32IFD-LABEL: fcmp_uge:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: frflags a0
-; RV32IFD-NEXT: flt.d a1, fa0, fa1
-; RV32IFD-NEXT: fsflags a0
-; RV32IFD-NEXT: xori a0, a1, 1
-; RV32IFD-NEXT: feq.d zero, fa0, fa1
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: fcmp_uge:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: frflags a0
-; RV64IFD-NEXT: flt.d a1, fa0, fa1
-; RV64IFD-NEXT: fsflags a0
-; RV64IFD-NEXT: xori a0, a1, 1
-; RV64IFD-NEXT: feq.d zero, fa0, fa1
-; RV64IFD-NEXT: ret
+; CHECKIFD-LABEL: fcmp_uge:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: frflags a0
+; CHECKIFD-NEXT: flt.d a1, fa0, fa1
+; CHECKIFD-NEXT: fsflags a0
+; CHECKIFD-NEXT: xori a0, a1, 1
+; CHECKIFD-NEXT: feq.d zero, fa0, fa1
+; CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fcmp_uge:
; RV32I: # %bb.0:
@@ -516,23 +427,14 @@ define i32 @fcmp_uge(double %a, double %b) nounwind strictfp {
}
define i32 @fcmp_ult(double %a, double %b) nounwind strictfp {
-; RV32IFD-LABEL: fcmp_ult:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: frflags a0
-; RV32IFD-NEXT: fle.d a1, fa1, fa0
-; RV32IFD-NEXT: fsflags a0
-; RV32IFD-NEXT: xori a0, a1, 1
-; RV32IFD-NEXT: feq.d zero, fa1, fa0
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: fcmp_ult:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: frflags a0
-; RV64IFD-NEXT: fle.d a1, fa1, fa0
-; RV64IFD-NEXT: fsflags a0
-; RV64IFD-NEXT: xori a0, a1, 1
-; RV64IFD-NEXT: feq.d zero, fa1, fa0
-; RV64IFD-NEXT: ret
+; CHECKIFD-LABEL: fcmp_ult:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: frflags a0
+; CHECKIFD-NEXT: fle.d a1, fa1, fa0
+; CHECKIFD-NEXT: fsflags a0
+; CHECKIFD-NEXT: xori a0, a1, 1
+; CHECKIFD-NEXT: feq.d zero, fa1, fa0
+; CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fcmp_ult:
; RV32I: # %bb.0:
@@ -559,23 +461,14 @@ define i32 @fcmp_ult(double %a, double %b) nounwind strictfp {
}
define i32 @fcmp_ule(double %a, double %b) nounwind strictfp {
-; RV32IFD-LABEL: fcmp_ule:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: frflags a0
-; RV32IFD-NEXT: flt.d a1, fa1, fa0
-; RV32IFD-NEXT: fsflags a0
-; RV32IFD-NEXT: xori a0, a1, 1
-; RV32IFD-NEXT: feq.d zero, fa1, fa0
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: fcmp_ule:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: frflags a0
-; RV64IFD-NEXT: flt.d a1, fa1, fa0
-; RV64IFD-NEXT: fsflags a0
-; RV64IFD-NEXT: xori a0, a1, 1
-; RV64IFD-NEXT: feq.d zero, fa1, fa0
-; RV64IFD-NEXT: ret
+; CHECKIFD-LABEL: fcmp_ule:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: frflags a0
+; CHECKIFD-NEXT: flt.d a1, fa1, fa0
+; CHECKIFD-NEXT: fsflags a0
+; CHECKIFD-NEXT: xori a0, a1, 1
+; CHECKIFD-NEXT: feq.d zero, fa1, fa0
+; CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fcmp_ule:
; RV32I: # %bb.0:
@@ -602,17 +495,11 @@ define i32 @fcmp_ule(double %a, double %b) nounwind strictfp {
}
define i32 @fcmp_une(double %a, double %b) nounwind strictfp {
-; RV32IFD-LABEL: fcmp_une:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: feq.d a0, fa0, fa1
-; RV32IFD-NEXT: xori a0, a0, 1
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: fcmp_une:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: feq.d a0, fa0, fa1
-; RV64IFD-NEXT: xori a0, a0, 1
-; RV64IFD-NEXT: ret
+; CHECKIFD-LABEL: fcmp_une:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: feq.d a0, fa0, fa1
+; CHECKIFD-NEXT: xori a0, a0, 1
+; CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fcmp_une:
; RV32I: # %bb.0:
@@ -639,21 +526,13 @@ define i32 @fcmp_une(double %a, double %b) nounwind strictfp {
}
define i32 @fcmp_uno(double %a, double %b) nounwind strictfp {
-; RV32IFD-LABEL: fcmp_uno:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: feq.d a0, fa1, fa1
-; RV32IFD-NEXT: feq.d a1, fa0, fa0
-; RV32IFD-NEXT: and a0, a1, a0
-; RV32IFD-NEXT: xori a0, a0, 1
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: fcmp_uno:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: feq.d a0, fa1, fa1
-; RV64IFD-NEXT: feq.d a1, fa0, fa0
-; RV64IFD-NEXT: and a0, a1, a0
-; RV64IFD-NEXT: xori a0, a0, 1
-; RV64IFD-NEXT: ret
+; CHECKIFD-LABEL: fcmp_uno:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: feq.d a0, fa1, fa1
+; CHECKIFD-NEXT: feq.d a1, fa0, fa0
+; CHECKIFD-NEXT: and a0, a1, a0
+; CHECKIFD-NEXT: xori a0, a0, 1
+; CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fcmp_uno:
; RV32I: # %bb.0:
@@ -680,19 +559,12 @@ define i32 @fcmp_uno(double %a, double %b) nounwind strictfp {
}
define i32 @fcmps_oeq(double %a, double %b) nounwind strictfp {
-; RV32IFD-LABEL: fcmps_oeq:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: fle.d a0, fa1, fa0
-; RV32IFD-NEXT: fle.d a1, fa0, fa1
-; RV32IFD-NEXT: and a0, a1, a0
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: fcmps_oeq:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fle.d a0, fa1, fa0
-; RV64IFD-NEXT: fle.d a1, fa0, fa1
-; RV64IFD-NEXT: and a0, a1, a0
-; RV64IFD-NEXT: ret
+; CHECKIFD-LABEL: fcmps_oeq:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: fle.d a0, fa1, fa0
+; CHECKIFD-NEXT: fle.d a1, fa0, fa1
+; CHECKIFD-NEXT: and a0, a1, a0
+; CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fcmps_oeq:
; RV32I: # %bb.0:
@@ -720,15 +592,10 @@ define i32 @fcmps_oeq(double %a, double %b) nounwind strictfp {
declare i1 @llvm.experimental.constrained.fcmps.f64(double, double, metadata, metadata)
define i32 @fcmps_ogt(double %a, double %b) nounwind strictfp {
-; RV32IFD-LABEL: fcmps_ogt:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: flt.d a0, fa1, fa0
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: fcmps_ogt:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: flt.d a0, fa1, fa0
-; RV64IFD-NEXT: ret
+; CHECKIFD-LABEL: fcmps_ogt:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: flt.d a0, fa1, fa0
+; CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fcmps_ogt:
; RV32I: # %bb.0:
@@ -755,15 +622,10 @@ define i32 @fcmps_ogt(double %a, double %b) nounwind strictfp {
}
define i32 @fcmps_oge(double %a, double %b) nounwind strictfp {
-; RV32IFD-LABEL: fcmps_oge:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: fle.d a0, fa1, fa0
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: fcmps_oge:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fle.d a0, fa1, fa0
-; RV64IFD-NEXT: ret
+; CHECKIFD-LABEL: fcmps_oge:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: fle.d a0, fa1, fa0
+; CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fcmps_oge:
; RV32I: # %bb.0:
@@ -792,15 +654,10 @@ define i32 @fcmps_oge(double %a, double %b) nounwind strictfp {
}
define i32 @fcmps_olt(double %a, double %b) nounwind strictfp {
-; RV32IFD-LABEL: fcmps_olt:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: flt.d a0, fa0, fa1
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: fcmps_olt:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: flt.d a0, fa0, fa1
-; RV64IFD-NEXT: ret
+; CHECKIFD-LABEL: fcmps_olt:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: flt.d a0, fa0, fa1
+; CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fcmps_olt:
; RV32I: # %bb.0:
@@ -827,15 +684,10 @@ define i32 @fcmps_olt(double %a, double %b) nounwind strictfp {
}
define i32 @fcmps_ole(double %a, double %b) nounwind strictfp {
-; RV32IFD-LABEL: fcmps_ole:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: fle.d a0, fa0, fa1
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: fcmps_ole:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fle.d a0, fa0, fa1
-; RV64IFD-NEXT: ret
+; CHECKIFD-LABEL: fcmps_ole:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: fle.d a0, fa0, fa1
+; CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fcmps_ole:
; RV32I: # %bb.0:
@@ -862,19 +714,12 @@ define i32 @fcmps_ole(double %a, double %b) nounwind strictfp {
}
define i32 @fcmps_one(double %a, double %b) nounwind strictfp {
-; RV32IFD-LABEL: fcmps_one:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: flt.d a0, fa0, fa1
-; RV32IFD-NEXT: flt.d a1, fa1, fa0
-; RV32IFD-NEXT: or a0, a1, a0
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: fcmps_one:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: flt.d a0, fa0, fa1
-; RV64IFD-NEXT: flt.d a1, fa1, fa0
-; RV64IFD-NEXT: or a0, a1, a0
-; RV64IFD-NEXT: ret
+; CHECKIFD-LABEL: fcmps_one:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: flt.d a0, fa0, fa1
+; CHECKIFD-NEXT: flt.d a1, fa1, fa0
+; CHECKIFD-NEXT: or a0, a1, a0
+; CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fcmps_one:
; RV32I: # %bb.0:
@@ -935,19 +780,12 @@ define i32 @fcmps_one(double %a, double %b) nounwind strictfp {
}
define i32 @fcmps_ord(double %a, double %b) nounwind strictfp {
-; RV32IFD-LABEL: fcmps_ord:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: fle.d a0, fa1, fa1
-; RV32IFD-NEXT: fle.d a1, fa0, fa0
-; RV32IFD-NEXT: and a0, a1, a0
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: fcmps_ord:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fle.d a0, fa1, fa1
-; RV64IFD-NEXT: fle.d a1, fa0, fa0
-; RV64IFD-NEXT: and a0, a1, a0
-; RV64IFD-NEXT: ret
+; CHECKIFD-LABEL: fcmps_ord:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: fle.d a0, fa1, fa1
+; CHECKIFD-NEXT: fle.d a1, fa0, fa0
+; CHECKIFD-NEXT: and a0, a1, a0
+; CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fcmps_ord:
; RV32I: # %bb.0:
@@ -974,21 +812,13 @@ define i32 @fcmps_ord(double %a, double %b) nounwind strictfp {
}
define i32 @fcmps_ueq(double %a, double %b) nounwind strictfp {
-; RV32IFD-LABEL: fcmps_ueq:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: flt.d a0, fa0, fa1
-; RV32IFD-NEXT: flt.d a1, fa1, fa0
-; RV32IFD-NEXT: or a0, a1, a0
-; RV32IFD-NEXT: xori a0, a0, 1
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: fcmps_ueq:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: flt.d a0, fa0, fa1
-; RV64IFD-NEXT: flt.d a1, fa1, fa0
-; RV64IFD-NEXT: or a0, a1, a0
-; RV64IFD-NEXT: xori a0, a0, 1
-; RV64IFD-NEXT: ret
+; CHECKIFD-LABEL: fcmps_ueq:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: flt.d a0, fa0, fa1
+; CHECKIFD-NEXT: flt.d a1, fa1, fa0
+; CHECKIFD-NEXT: or a0, a1, a0
+; CHECKIFD-NEXT: xori a0, a0, 1
+; CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fcmps_ueq:
; RV32I: # %bb.0:
@@ -1049,17 +879,11 @@ define i32 @fcmps_ueq(double %a, double %b) nounwind strictfp {
}
define i32 @fcmps_ugt(double %a, double %b) nounwind strictfp {
-; RV32IFD-LABEL: fcmps_ugt:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: fle.d a0, fa0, fa1
-; RV32IFD-NEXT: xori a0, a0, 1
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: fcmps_ugt:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fle.d a0, fa0, fa1
-; RV64IFD-NEXT: xori a0, a0, 1
-; RV64IFD-NEXT: ret
+; CHECKIFD-LABEL: fcmps_ugt:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: fle.d a0, fa0, fa1
+; CHECKIFD-NEXT: xori a0, a0, 1
+; CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fcmps_ugt:
; RV32I: # %bb.0:
@@ -1086,17 +910,11 @@ define i32 @fcmps_ugt(double %a, double %b) nounwind strictfp {
}
define i32 @fcmps_uge(double %a, double %b) nounwind strictfp {
-; RV32IFD-LABEL: fcmps_uge:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: flt.d a0, fa0, fa1
-; RV32IFD-NEXT: xori a0, a0, 1
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: fcmps_uge:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: flt.d a0, fa0, fa1
-; RV64IFD-NEXT: xori a0, a0, 1
-; RV64IFD-NEXT: ret
+; CHECKIFD-LABEL: fcmps_uge:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: flt.d a0, fa0, fa1
+; CHECKIFD-NEXT: xori a0, a0, 1
+; CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fcmps_uge:
; RV32I: # %bb.0:
@@ -1125,17 +943,11 @@ define i32 @fcmps_uge(double %a, double %b) nounwind strictfp {
}
define i32 @fcmps_ult(double %a, double %b) nounwind strictfp {
-; RV32IFD-LABEL: fcmps_ult:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: fle.d a0, fa1, fa0
-; RV32IFD-NEXT: xori a0, a0, 1
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: fcmps_ult:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fle.d a0, fa1, fa0
-; RV64IFD-NEXT: xori a0, a0, 1
-; RV64IFD-NEXT: ret
+; CHECKIFD-LABEL: fcmps_ult:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: fle.d a0, fa1, fa0
+; CHECKIFD-NEXT: xori a0, a0, 1
+; CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fcmps_ult:
; RV32I: # %bb.0:
@@ -1162,17 +974,11 @@ define i32 @fcmps_ult(double %a, double %b) nounwind strictfp {
}
define i32 @fcmps_ule(double %a, double %b) nounwind strictfp {
-; RV32IFD-LABEL: fcmps_ule:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: flt.d a0, fa1, fa0
-; RV32IFD-NEXT: xori a0, a0, 1
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: fcmps_ule:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: flt.d a0, fa1, fa0
-; RV64IFD-NEXT: xori a0, a0, 1
-; RV64IFD-NEXT: ret
+; CHECKIFD-LABEL: fcmps_ule:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: flt.d a0, fa1, fa0
+; CHECKIFD-NEXT: xori a0, a0, 1
+; CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fcmps_ule:
; RV32I: # %bb.0:
@@ -1199,21 +1005,13 @@ define i32 @fcmps_ule(double %a, double %b) nounwind strictfp {
}
define i32 @fcmps_une(double %a, double %b) nounwind strictfp {
-; RV32IFD-LABEL: fcmps_une:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: fle.d a0, fa1, fa0
-; RV32IFD-NEXT: fle.d a1, fa0, fa1
-; RV32IFD-NEXT: and a0, a1, a0
-; RV32IFD-NEXT: xori a0, a0, 1
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: fcmps_une:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fle.d a0, fa1, fa0
-; RV64IFD-NEXT: fle.d a1, fa0, fa1
-; RV64IFD-NEXT: and a0, a1, a0
-; RV64IFD-NEXT: xori a0, a0, 1
-; RV64IFD-NEXT: ret
+; CHECKIFD-LABEL: fcmps_une:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: fle.d a0, fa1, fa0
+; CHECKIFD-NEXT: fle.d a1, fa0, fa1
+; CHECKIFD-NEXT: and a0, a1, a0
+; CHECKIFD-NEXT: xori a0, a0, 1
+; CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fcmps_une:
; RV32I: # %bb.0:
@@ -1240,21 +1038,13 @@ define i32 @fcmps_une(double %a, double %b) nounwind strictfp {
}
define i32 @fcmps_uno(double %a, double %b) nounwind strictfp {
-; RV32IFD-LABEL: fcmps_uno:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: fle.d a0, fa1, fa1
-; RV32IFD-NEXT: fle.d a1, fa0, fa0
-; RV32IFD-NEXT: and a0, a1, a0
-; RV32IFD-NEXT: xori a0, a0, 1
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: fcmps_uno:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fle.d a0, fa1, fa1
-; RV64IFD-NEXT: fle.d a1, fa0, fa0
-; RV64IFD-NEXT: and a0, a1, a0
-; RV64IFD-NEXT: xori a0, a0, 1
-; RV64IFD-NEXT: ret
+; CHECKIFD-LABEL: fcmps_uno:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: fle.d a0, fa1, fa1
+; CHECKIFD-NEXT: fle.d a1, fa0, fa0
+; CHECKIFD-NEXT: and a0, a1, a0
+; CHECKIFD-NEXT: xori a0, a0, 1
+; CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fcmps_uno:
; RV32I: # %bb.0:
diff --git a/llvm/test/CodeGen/RISCV/double-fcmp.ll b/llvm/test/CodeGen/RISCV/double-fcmp.ll
index 3945fab8ca2a..146265953b7b 100644
--- a/llvm/test/CodeGen/RISCV/double-fcmp.ll
+++ b/llvm/test/CodeGen/RISCV/double-fcmp.ll
@@ -1,23 +1,18 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \
-; RUN: -target-abi=ilp32d | FileCheck -check-prefix=RV32IFD %s
+; RUN: -target-abi=ilp32d | FileCheck -check-prefix=CHECKIFD %s
; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \
-; RUN: -target-abi=lp64d | FileCheck -check-prefix=RV64IFD %s
+; RUN: -target-abi=lp64d | FileCheck -check-prefix=CHECKIFD %s
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32I %s
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64I %s
define i32 @fcmp_false(double %a, double %b) nounwind {
-; RV32IFD-LABEL: fcmp_false:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: li a0, 0
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: fcmp_false:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: li a0, 0
-; RV64IFD-NEXT: ret
+;CHECKIFD-LABEL: fcmp_false:
+;CHECKIFD: # %bb.0:
+;CHECKIFD-NEXT: li a0, 0
+;CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fcmp_false:
; RV32I: # %bb.0:
@@ -34,15 +29,10 @@ define i32 @fcmp_false(double %a, double %b) nounwind {
}
define i32 @fcmp_oeq(double %a, double %b) nounwind {
-; RV32IFD-LABEL: fcmp_oeq:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: feq.d a0, fa0, fa1
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: fcmp_oeq:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: feq.d a0, fa0, fa1
-; RV64IFD-NEXT: ret
+;CHECKIFD-LABEL: fcmp_oeq:
+;CHECKIFD: # %bb.0:
+;CHECKIFD-NEXT: feq.d a0, fa0, fa1
+;CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fcmp_oeq:
; RV32I: # %bb.0:
@@ -69,15 +59,10 @@ define i32 @fcmp_oeq(double %a, double %b) nounwind {
}
define i32 @fcmp_ogt(double %a, double %b) nounwind {
-; RV32IFD-LABEL: fcmp_ogt:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: flt.d a0, fa1, fa0
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: fcmp_ogt:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: flt.d a0, fa1, fa0
-; RV64IFD-NEXT: ret
+;CHECKIFD-LABEL: fcmp_ogt:
+;CHECKIFD: # %bb.0:
+;CHECKIFD-NEXT: flt.d a0, fa1, fa0
+;CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fcmp_ogt:
; RV32I: # %bb.0:
@@ -104,15 +89,10 @@ define i32 @fcmp_ogt(double %a, double %b) nounwind {
}
define i32 @fcmp_oge(double %a, double %b) nounwind {
-; RV32IFD-LABEL: fcmp_oge:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: fle.d a0, fa1, fa0
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: fcmp_oge:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fle.d a0, fa1, fa0
-; RV64IFD-NEXT: ret
+;CHECKIFD-LABEL: fcmp_oge:
+;CHECKIFD: # %bb.0:
+;CHECKIFD-NEXT: fle.d a0, fa1, fa0
+;CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fcmp_oge:
; RV32I: # %bb.0:
@@ -141,15 +121,10 @@ define i32 @fcmp_oge(double %a, double %b) nounwind {
}
define i32 @fcmp_olt(double %a, double %b) nounwind {
-; RV32IFD-LABEL: fcmp_olt:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: flt.d a0, fa0, fa1
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: fcmp_olt:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: flt.d a0, fa0, fa1
-; RV64IFD-NEXT: ret
+;CHECKIFD-LABEL: fcmp_olt:
+;CHECKIFD: # %bb.0:
+;CHECKIFD-NEXT: flt.d a0, fa0, fa1
+;CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fcmp_olt:
; RV32I: # %bb.0:
@@ -176,15 +151,10 @@ define i32 @fcmp_olt(double %a, double %b) nounwind {
}
define i32 @fcmp_ole(double %a, double %b) nounwind {
-; RV32IFD-LABEL: fcmp_ole:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: fle.d a0, fa0, fa1
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: fcmp_ole:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fle.d a0, fa0, fa1
-; RV64IFD-NEXT: ret
+;CHECKIFD-LABEL: fcmp_ole:
+;CHECKIFD: # %bb.0:
+;CHECKIFD-NEXT: fle.d a0, fa0, fa1
+;CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fcmp_ole:
; RV32I: # %bb.0:
@@ -211,19 +181,12 @@ define i32 @fcmp_ole(double %a, double %b) nounwind {
}
define i32 @fcmp_one(double %a, double %b) nounwind {
-; RV32IFD-LABEL: fcmp_one:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: flt.d a0, fa0, fa1
-; RV32IFD-NEXT: flt.d a1, fa1, fa0
-; RV32IFD-NEXT: or a0, a1, a0
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: fcmp_one:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: flt.d a0, fa0, fa1
-; RV64IFD-NEXT: flt.d a1, fa1, fa0
-; RV64IFD-NEXT: or a0, a1, a0
-; RV64IFD-NEXT: ret
+;CHECKIFD-LABEL: fcmp_one:
+;CHECKIFD: # %bb.0:
+;CHECKIFD-NEXT: flt.d a0, fa0, fa1
+;CHECKIFD-NEXT: flt.d a1, fa1, fa0
+;CHECKIFD-NEXT: or a0, a1, a0
+;CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fcmp_one:
; RV32I: # %bb.0:
@@ -284,19 +247,12 @@ define i32 @fcmp_one(double %a, double %b) nounwind {
}
define i32 @fcmp_ord(double %a, double %b) nounwind {
-; RV32IFD-LABEL: fcmp_ord:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: feq.d a0, fa1, fa1
-; RV32IFD-NEXT: feq.d a1, fa0, fa0
-; RV32IFD-NEXT: and a0, a1, a0
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: fcmp_ord:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: feq.d a0, fa1, fa1
-; RV64IFD-NEXT: feq.d a1, fa0, fa0
-; RV64IFD-NEXT: and a0, a1, a0
-; RV64IFD-NEXT: ret
+;CHECKIFD-LABEL: fcmp_ord:
+;CHECKIFD: # %bb.0:
+;CHECKIFD-NEXT: feq.d a0, fa1, fa1
+;CHECKIFD-NEXT: feq.d a1, fa0, fa0
+;CHECKIFD-NEXT: and a0, a1, a0
+;CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fcmp_ord:
; RV32I: # %bb.0:
@@ -323,21 +279,13 @@ define i32 @fcmp_ord(double %a, double %b) nounwind {
}
define i32 @fcmp_ueq(double %a, double %b) nounwind {
-; RV32IFD-LABEL: fcmp_ueq:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: flt.d a0, fa0, fa1
-; RV32IFD-NEXT: flt.d a1, fa1, fa0
-; RV32IFD-NEXT: or a0, a1, a0
-; RV32IFD-NEXT: xori a0, a0, 1
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: fcmp_ueq:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: flt.d a0, fa0, fa1
-; RV64IFD-NEXT: flt.d a1, fa1, fa0
-; RV64IFD-NEXT: or a0, a1, a0
-; RV64IFD-NEXT: xori a0, a0, 1
-; RV64IFD-NEXT: ret
+;CHECKIFD-LABEL: fcmp_ueq:
+;CHECKIFD: # %bb.0:
+;CHECKIFD-NEXT: flt.d a0, fa0, fa1
+;CHECKIFD-NEXT: flt.d a1, fa1, fa0
+;CHECKIFD-NEXT: or a0, a1, a0
+;CHECKIFD-NEXT: xori a0, a0, 1
+;CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fcmp_ueq:
; RV32I: # %bb.0:
@@ -398,17 +346,11 @@ define i32 @fcmp_ueq(double %a, double %b) nounwind {
}
define i32 @fcmp_ugt(double %a, double %b) nounwind {
-; RV32IFD-LABEL: fcmp_ugt:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: fle.d a0, fa0, fa1
-; RV32IFD-NEXT: xori a0, a0, 1
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: fcmp_ugt:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fle.d a0, fa0, fa1
-; RV64IFD-NEXT: xori a0, a0, 1
-; RV64IFD-NEXT: ret
+;CHECKIFD-LABEL: fcmp_ugt:
+;CHECKIFD: # %bb.0:
+;CHECKIFD-NEXT: fle.d a0, fa0, fa1
+;CHECKIFD-NEXT: xori a0, a0, 1
+;CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fcmp_ugt:
; RV32I: # %bb.0:
@@ -435,17 +377,11 @@ define i32 @fcmp_ugt(double %a, double %b) nounwind {
}
define i32 @fcmp_uge(double %a, double %b) nounwind {
-; RV32IFD-LABEL: fcmp_uge:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: flt.d a0, fa0, fa1
-; RV32IFD-NEXT: xori a0, a0, 1
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: fcmp_uge:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: flt.d a0, fa0, fa1
-; RV64IFD-NEXT: xori a0, a0, 1
-; RV64IFD-NEXT: ret
+;CHECKIFD-LABEL: fcmp_uge:
+;CHECKIFD: # %bb.0:
+;CHECKIFD-NEXT: flt.d a0, fa0, fa1
+;CHECKIFD-NEXT: xori a0, a0, 1
+;CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fcmp_uge:
; RV32I: # %bb.0:
@@ -474,17 +410,11 @@ define i32 @fcmp_uge(double %a, double %b) nounwind {
}
define i32 @fcmp_ult(double %a, double %b) nounwind {
-; RV32IFD-LABEL: fcmp_ult:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: fle.d a0, fa1, fa0
-; RV32IFD-NEXT: xori a0, a0, 1
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: fcmp_ult:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fle.d a0, fa1, fa0
-; RV64IFD-NEXT: xori a0, a0, 1
-; RV64IFD-NEXT: ret
+;CHECKIFD-LABEL: fcmp_ult:
+;CHECKIFD: # %bb.0:
+;CHECKIFD-NEXT: fle.d a0, fa1, fa0
+;CHECKIFD-NEXT: xori a0, a0, 1
+;CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fcmp_ult:
; RV32I: # %bb.0:
@@ -511,17 +441,11 @@ define i32 @fcmp_ult(double %a, double %b) nounwind {
}
define i32 @fcmp_ule(double %a, double %b) nounwind {
-; RV32IFD-LABEL: fcmp_ule:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: flt.d a0, fa1, fa0
-; RV32IFD-NEXT: xori a0, a0, 1
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: fcmp_ule:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: flt.d a0, fa1, fa0
-; RV64IFD-NEXT: xori a0, a0, 1
-; RV64IFD-NEXT: ret
+;CHECKIFD-LABEL: fcmp_ule:
+;CHECKIFD: # %bb.0:
+;CHECKIFD-NEXT: flt.d a0, fa1, fa0
+;CHECKIFD-NEXT: xori a0, a0, 1
+;CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fcmp_ule:
; RV32I: # %bb.0:
@@ -548,17 +472,11 @@ define i32 @fcmp_ule(double %a, double %b) nounwind {
}
define i32 @fcmp_une(double %a, double %b) nounwind {
-; RV32IFD-LABEL: fcmp_une:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: feq.d a0, fa0, fa1
-; RV32IFD-NEXT: xori a0, a0, 1
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: fcmp_une:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: feq.d a0, fa0, fa1
-; RV64IFD-NEXT: xori a0, a0, 1
-; RV64IFD-NEXT: ret
+;CHECKIFD-LABEL: fcmp_une:
+;CHECKIFD: # %bb.0:
+;CHECKIFD-NEXT: feq.d a0, fa0, fa1
+;CHECKIFD-NEXT: xori a0, a0, 1
+;CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fcmp_une:
; RV32I: # %bb.0:
@@ -585,21 +503,13 @@ define i32 @fcmp_une(double %a, double %b) nounwind {
}
define i32 @fcmp_uno(double %a, double %b) nounwind {
-; RV32IFD-LABEL: fcmp_uno:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: feq.d a0, fa1, fa1
-; RV32IFD-NEXT: feq.d a1, fa0, fa0
-; RV32IFD-NEXT: and a0, a1, a0
-; RV32IFD-NEXT: xori a0, a0, 1
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: fcmp_uno:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: feq.d a0, fa1, fa1
-; RV64IFD-NEXT: feq.d a1, fa0, fa0
-; RV64IFD-NEXT: and a0, a1, a0
-; RV64IFD-NEXT: xori a0, a0, 1
-; RV64IFD-NEXT: ret
+;CHECKIFD-LABEL: fcmp_uno:
+;CHECKIFD: # %bb.0:
+;CHECKIFD-NEXT: feq.d a0, fa1, fa1
+;CHECKIFD-NEXT: feq.d a1, fa0, fa0
+;CHECKIFD-NEXT: and a0, a1, a0
+;CHECKIFD-NEXT: xori a0, a0, 1
+;CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fcmp_uno:
; RV32I: # %bb.0:
@@ -626,15 +536,10 @@ define i32 @fcmp_uno(double %a, double %b) nounwind {
}
define i32 @fcmp_true(double %a, double %b) nounwind {
-; RV32IFD-LABEL: fcmp_true:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: li a0, 1
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: fcmp_true:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: li a0, 1
-; RV64IFD-NEXT: ret
+;CHECKIFD-LABEL: fcmp_true:
+;CHECKIFD: # %bb.0:
+;CHECKIFD-NEXT: li a0, 1
+;CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fcmp_true:
; RV32I: # %bb.0:
diff --git a/llvm/test/CodeGen/RISCV/double-imm.ll b/llvm/test/CodeGen/RISCV/double-imm.ll
index 5c764d9dece2..9e62920fd03d 100644
--- a/llvm/test/CodeGen/RISCV/double-imm.ll
+++ b/llvm/test/CodeGen/RISCV/double-imm.ll
@@ -1,38 +1,25 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \
-; RUN: -target-abi=ilp32d | FileCheck -check-prefix=RV32IFD %s
+; RUN: -target-abi=ilp32d | FileCheck %s
; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \
-; RUN: -target-abi=lp64d | FileCheck -check-prefix=RV64IFD %s
+; RUN: -target-abi=lp64d | FileCheck %s
define double @double_imm() nounwind {
-; RV32IFD-LABEL: double_imm:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: lui a0, %hi(.LCPI0_0)
-; RV32IFD-NEXT: fld fa0, %lo(.LCPI0_0)(a0)
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: double_imm:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: lui a0, %hi(.LCPI0_0)
-; RV64IFD-NEXT: fld fa0, %lo(.LCPI0_0)(a0)
-; RV64IFD-NEXT: ret
+; CHECK-LABEL: double_imm:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a0, %hi(.LCPI0_0)
+; CHECK-NEXT: fld fa0, %lo(.LCPI0_0)(a0)
+; CHECK-NEXT: ret
ret double 3.1415926535897931159979634685441851615905761718750
}
define double @double_imm_op(double %a) nounwind {
-; RV32IFD-LABEL: double_imm_op:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: lui a0, %hi(.LCPI1_0)
-; RV32IFD-NEXT: fld ft0, %lo(.LCPI1_0)(a0)
-; RV32IFD-NEXT: fadd.d fa0, fa0, ft0
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: double_imm_op:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: lui a0, %hi(.LCPI1_0)
-; RV64IFD-NEXT: fld ft0, %lo(.LCPI1_0)(a0)
-; RV64IFD-NEXT: fadd.d fa0, fa0, ft0
-; RV64IFD-NEXT: ret
+; CHECK-LABEL: double_imm_op:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a0, %hi(.LCPI1_0)
+; CHECK-NEXT: fld ft0, %lo(.LCPI1_0)(a0)
+; CHECK-NEXT: fadd.d fa0, fa0, ft0
+; CHECK-NEXT: ret
%1 = fadd double %a, 1.0
ret double %1
}
diff --git a/llvm/test/CodeGen/RISCV/double-intrinsics-strict.ll b/llvm/test/CodeGen/RISCV/double-intrinsics-strict.ll
index b1968fe83177..1ce3f57e9c95 100644
--- a/llvm/test/CodeGen/RISCV/double-intrinsics-strict.ll
+++ b/llvm/test/CodeGen/RISCV/double-intrinsics-strict.ll
@@ -1,10 +1,10 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+d \
; RUN: -verify-machineinstrs -disable-strictnode-mutation -target-abi=ilp32d \
-; RUN: | FileCheck -check-prefix=RV32IFD %s
+; RUN: | FileCheck -check-prefixes=CHECKIFD,RV32IFD %s
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+d \
; RUN: -verify-machineinstrs -disable-strictnode-mutation -target-abi=lp64d \
-; RUN: | FileCheck -check-prefix=RV64IFD %s
+; RUN: | FileCheck -check-prefixes=CHECKIFD,RV64IFD %s
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 \
; RUN: -verify-machineinstrs -disable-strictnode-mutation \
; RUN: | FileCheck -check-prefix=RV32I %s
@@ -15,15 +15,10 @@
declare double @llvm.experimental.constrained.sqrt.f64(double, metadata, metadata)
define double @sqrt_f64(double %a) nounwind strictfp {
-; RV32IFD-LABEL: sqrt_f64:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: fsqrt.d fa0, fa0
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: sqrt_f64:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fsqrt.d fa0, fa0
-; RV64IFD-NEXT: ret
+; CHECKIFD-LABEL: sqrt_f64:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: fsqrt.d fa0, fa0
+; CHECKIFD-NEXT: ret
;
; RV32I-LABEL: sqrt_f64:
; RV32I: # %bb.0:
@@ -521,15 +516,10 @@ define double @log2_f64(double %a) nounwind strictfp {
declare double @llvm.experimental.constrained.fma.f64(double, double, double, metadata, metadata)
define double @fma_f64(double %a, double %b, double %c) nounwind strictfp {
-; RV32IFD-LABEL: fma_f64:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: fmadd.d fa0, fa0, fa1, fa2
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: fma_f64:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fmadd.d fa0, fa0, fa1, fa2
-; RV64IFD-NEXT: ret
+; CHECKIFD-LABEL: fma_f64:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: fmadd.d fa0, fa0, fa1, fa2
+; CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fma_f64:
; RV32I: # %bb.0:
@@ -555,15 +545,10 @@ define double @fma_f64(double %a, double %b, double %c) nounwind strictfp {
declare double @llvm.experimental.constrained.fmuladd.f64(double, double, double, metadata, metadata)
define double @fmuladd_f64(double %a, double %b, double %c) nounwind strictfp {
-; RV32IFD-LABEL: fmuladd_f64:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: fmadd.d fa0, fa0, fa1, fa2
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: fmuladd_f64:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fmadd.d fa0, fa0, fa1, fa2
-; RV64IFD-NEXT: ret
+; CHECKIFD-LABEL: fmuladd_f64:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: fmadd.d fa0, fa0, fa1, fa2
+; CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fmuladd_f64:
; RV32I: # %bb.0:
diff --git a/llvm/test/CodeGen/RISCV/double-intrinsics.ll b/llvm/test/CodeGen/RISCV/double-intrinsics.ll
index 84b9c27bcee4..374d1308714a 100644
--- a/llvm/test/CodeGen/RISCV/double-intrinsics.ll
+++ b/llvm/test/CodeGen/RISCV/double-intrinsics.ll
@@ -1,10 +1,10 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+d \
; RUN: -verify-machineinstrs -target-abi=ilp32d \
-; RUN: | FileCheck -check-prefix=RV32IFD %s
+; RUN: | FileCheck -check-prefixes=CHECKIFD,RV32IFD %s
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+d \
; RUN: -verify-machineinstrs -target-abi=lp64d \
-; RUN: | FileCheck -check-prefix=RV64IFD %s
+; RUN: | FileCheck -check-prefixes=CHECKIFD,RV64IFD %s
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 \
; RUN: -verify-machineinstrs | FileCheck -check-prefix=RV32I %s
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 \
@@ -13,15 +13,10 @@
declare double @llvm.sqrt.f64(double)
define double @sqrt_f64(double %a) nounwind {
-; RV32IFD-LABEL: sqrt_f64:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: fsqrt.d fa0, fa0
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: sqrt_f64:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fsqrt.d fa0, fa0
-; RV64IFD-NEXT: ret
+; CHECKIFD-LABEL: sqrt_f64:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: fsqrt.d fa0, fa0
+; CHECKIFD-NEXT: ret
;
; RV32I-LABEL: sqrt_f64:
; RV32I: # %bb.0:
@@ -519,15 +514,10 @@ define double @log2_f64(double %a) nounwind {
declare double @llvm.fma.f64(double, double, double)
define double @fma_f64(double %a, double %b, double %c) nounwind {
-; RV32IFD-LABEL: fma_f64:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: fmadd.d fa0, fa0, fa1, fa2
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: fma_f64:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fmadd.d fa0, fa0, fa1, fa2
-; RV64IFD-NEXT: ret
+; CHECKIFD-LABEL: fma_f64:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: fmadd.d fa0, fa0, fa1, fa2
+; CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fma_f64:
; RV32I: # %bb.0:
@@ -553,15 +543,10 @@ define double @fma_f64(double %a, double %b, double %c) nounwind {
declare double @llvm.fmuladd.f64(double, double, double)
define double @fmuladd_f64(double %a, double %b, double %c) nounwind {
-; RV32IFD-LABEL: fmuladd_f64:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: fmadd.d fa0, fa0, fa1, fa2
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: fmuladd_f64:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fmadd.d fa0, fa0, fa1, fa2
-; RV64IFD-NEXT: ret
+; CHECKIFD-LABEL: fmuladd_f64:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: fmadd.d fa0, fa0, fa1, fa2
+; CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fmuladd_f64:
; RV32I: # %bb.0:
@@ -601,15 +586,10 @@ define double @fmuladd_f64(double %a, double %b, double %c) nounwind {
declare double @llvm.fabs.f64(double)
define double @fabs_f64(double %a) nounwind {
-; RV32IFD-LABEL: fabs_f64:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: fabs.d fa0, fa0
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: fabs_f64:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fabs.d fa0, fa0
-; RV64IFD-NEXT: ret
+; CHECKIFD-LABEL: fabs_f64:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: fabs.d fa0, fa0
+; CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fabs_f64:
; RV32I: # %bb.0:
@@ -629,15 +609,10 @@ define double @fabs_f64(double %a) nounwind {
declare double @llvm.minnum.f64(double, double)
define double @minnum_f64(double %a, double %b) nounwind {
-; RV32IFD-LABEL: minnum_f64:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: fmin.d fa0, fa0, fa1
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: minnum_f64:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fmin.d fa0, fa0, fa1
-; RV64IFD-NEXT: ret
+; CHECKIFD-LABEL: minnum_f64:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: fmin.d fa0, fa0, fa1
+; CHECKIFD-NEXT: ret
;
; RV32I-LABEL: minnum_f64:
; RV32I: # %bb.0:
@@ -663,15 +638,10 @@ define double @minnum_f64(double %a, double %b) nounwind {
declare double @llvm.maxnum.f64(double, double)
define double @maxnum_f64(double %a, double %b) nounwind {
-; RV32IFD-LABEL: maxnum_f64:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: fmax.d fa0, fa0, fa1
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: maxnum_f64:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fmax.d fa0, fa0, fa1
-; RV64IFD-NEXT: ret
+; CHECKIFD-LABEL: maxnum_f64:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: fmax.d fa0, fa0, fa1
+; CHECKIFD-NEXT: ret
;
; RV32I-LABEL: maxnum_f64:
; RV32I: # %bb.0:
@@ -714,15 +684,10 @@ define double @maxnum_f64(double %a, double %b) nounwind {
declare double @llvm.copysign.f64(double, double)
define double @copysign_f64(double %a, double %b) nounwind {
-; RV32IFD-LABEL: copysign_f64:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: fsgnj.d fa0, fa0, fa1
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: copysign_f64:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fsgnj.d fa0, fa0, fa1
-; RV64IFD-NEXT: ret
+; CHECKIFD-LABEL: copysign_f64:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: fsgnj.d fa0, fa0, fa1
+; CHECKIFD-NEXT: ret
;
; RV32I-LABEL: copysign_f64:
; RV32I: # %bb.0:
diff --git a/llvm/test/CodeGen/RISCV/double-isnan.ll b/llvm/test/CodeGen/RISCV/double-isnan.ll
index 4729ca2c40a1..b0bc37738037 100644
--- a/llvm/test/CodeGen/RISCV/double-isnan.ll
+++ b/llvm/test/CodeGen/RISCV/double-isnan.ll
@@ -1,35 +1,24 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi ilp32d -verify-machineinstrs \
-; RUN: < %s | FileCheck -check-prefix=RV32IFD %s
+; RUN: < %s | FileCheck %s
; RUN: llc -mtriple=riscv64 -mattr=+d -target-abi lp64d -verify-machineinstrs \
-; RUN: < %s | FileCheck -check-prefix=RV64IFD %s
+; RUN: < %s | FileCheck %s
define zeroext i1 @double_is_nan(double %a) nounwind {
-; RV32IFD-LABEL: double_is_nan:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: feq.d a0, fa0, fa0
-; RV32IFD-NEXT: xori a0, a0, 1
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: double_is_nan:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: feq.d a0, fa0, fa0
-; RV64IFD-NEXT: xori a0, a0, 1
-; RV64IFD-NEXT: ret
+; CHECK-LABEL: double_is_nan:
+; CHECK: # %bb.0:
+; CHECK-NEXT: feq.d a0, fa0, fa0
+; CHECK-NEXT: xori a0, a0, 1
+; CHECK-NEXT: ret
%1 = fcmp uno double %a, 0.000000e+00
ret i1 %1
}
define zeroext i1 @double_not_nan(double %a) nounwind {
-; RV32IFD-LABEL: double_not_nan:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: feq.d a0, fa0, fa0
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: double_not_nan:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: feq.d a0, fa0, fa0
-; RV64IFD-NEXT: ret
+; CHECK-LABEL: double_not_nan:
+; CHECK: # %bb.0:
+; CHECK-NEXT: feq.d a0, fa0, fa0
+; CHECK-NEXT: ret
%1 = fcmp ord double %a, 0.000000e+00
ret i1 %1
}
diff --git a/llvm/test/CodeGen/RISCV/double-mem.ll b/llvm/test/CodeGen/RISCV/double-mem.ll
index fc42f2a23645..e43376e6eeaa 100644
--- a/llvm/test/CodeGen/RISCV/double-mem.ll
+++ b/llvm/test/CodeGen/RISCV/double-mem.ll
@@ -1,23 +1,16 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \
-; RUN: -target-abi=ilp32d | FileCheck -check-prefix=RV32IFD %s
+; RUN: -target-abi=ilp32d | FileCheck -check-prefixes=CHECKIFD,RV32IFD %s
; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \
-; RUN: -target-abi=lp64d | FileCheck -check-prefix=RV64IFD %s
+; RUN: -target-abi=lp64d | FileCheck -check-prefixes=CHECKIFD,RV64IFD %s
define dso_local double @fld(double *%a) nounwind {
-; RV32IFD-LABEL: fld:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: fld ft0, 0(a0)
-; RV32IFD-NEXT: fld ft1, 24(a0)
-; RV32IFD-NEXT: fadd.d fa0, ft0, ft1
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: fld:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fld ft0, 0(a0)
-; RV64IFD-NEXT: fld ft1, 24(a0)
-; RV64IFD-NEXT: fadd.d fa0, ft0, ft1
-; RV64IFD-NEXT: ret
+; CHECKIFD-LABEL: fld:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: fld ft0, 0(a0)
+; CHECKIFD-NEXT: fld ft1, 24(a0)
+; CHECKIFD-NEXT: fadd.d fa0, ft0, ft1
+; CHECKIFD-NEXT: ret
%1 = load double, double* %a
%2 = getelementptr double, double* %a, i32 3
%3 = load double, double* %2
@@ -28,19 +21,12 @@ define dso_local double @fld(double *%a) nounwind {
}
define dso_local void @fsd(double *%a, double %b, double %c) nounwind {
-; RV32IFD-LABEL: fsd:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: fadd.d ft0, fa0, fa1
-; RV32IFD-NEXT: fsd ft0, 0(a0)
-; RV32IFD-NEXT: fsd ft0, 64(a0)
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: fsd:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fadd.d ft0, fa0, fa1
-; RV64IFD-NEXT: fsd ft0, 0(a0)
-; RV64IFD-NEXT: fsd ft0, 64(a0)
-; RV64IFD-NEXT: ret
+; CHECKIFD-LABEL: fsd:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: fadd.d ft0, fa0, fa1
+; CHECKIFD-NEXT: fsd ft0, 0(a0)
+; CHECKIFD-NEXT: fsd ft0, 64(a0)
+; CHECKIFD-NEXT: ret
; Use %b and %c in an FP op to ensure floating point registers are used, even
; for the soft float ABI
%1 = fadd double %b, %c
@@ -54,27 +40,16 @@ define dso_local void @fsd(double *%a, double %b, double %c) nounwind {
@G = dso_local global double 0.0
define dso_local double @fld_fsd_global(double %a, double %b) nounwind {
-; RV32IFD-LABEL: fld_fsd_global:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: fadd.d fa0, fa0, fa1
-; RV32IFD-NEXT: lui a0, %hi(G)
-; RV32IFD-NEXT: fld ft0, %lo(G)(a0)
-; RV32IFD-NEXT: addi a1, a0, %lo(G)
-; RV32IFD-NEXT: fsd fa0, %lo(G)(a0)
-; RV32IFD-NEXT: fld ft0, 72(a1)
-; RV32IFD-NEXT: fsd fa0, 72(a1)
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: fld_fsd_global:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fadd.d fa0, fa0, fa1
-; RV64IFD-NEXT: lui a0, %hi(G)
-; RV64IFD-NEXT: fld ft0, %lo(G)(a0)
-; RV64IFD-NEXT: addi a1, a0, %lo(G)
-; RV64IFD-NEXT: fsd fa0, %lo(G)(a0)
-; RV64IFD-NEXT: fld ft0, 72(a1)
-; RV64IFD-NEXT: fsd fa0, 72(a1)
-; RV64IFD-NEXT: ret
+; CHECKIFD-LABEL: fld_fsd_global:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: fadd.d fa0, fa0, fa1
+; CHECKIFD-NEXT: lui a0, %hi(G)
+; CHECKIFD-NEXT: fld ft0, %lo(G)(a0)
+; CHECKIFD-NEXT: addi a1, a0, %lo(G)
+; CHECKIFD-NEXT: fsd fa0, %lo(G)(a0)
+; CHECKIFD-NEXT: fld ft0, 72(a1)
+; CHECKIFD-NEXT: fsd fa0, 72(a1)
+; CHECKIFD-NEXT: ret
; Use %a and %b in an FP op to ensure floating point registers are used, even
; for the soft float ABI
%1 = fadd double %a, %b
@@ -185,17 +160,11 @@ define dso_local void @fsd_stack(double %a, double %b) nounwind {
; Test selection of store<ST4[%a], trunc to f32>, ..
define dso_local void @fsd_trunc(float* %a, double %b) nounwind noinline optnone {
-; RV32IFD-LABEL: fsd_trunc:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: fcvt.s.d ft0, fa0
-; RV32IFD-NEXT: fsw ft0, 0(a0)
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: fsd_trunc:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fcvt.s.d ft0, fa0
-; RV64IFD-NEXT: fsw ft0, 0(a0)
-; RV64IFD-NEXT: ret
+; CHECKIFD-LABEL: fsd_trunc:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: fcvt.s.d ft0, fa0
+; CHECKIFD-NEXT: fsw ft0, 0(a0)
+; CHECKIFD-NEXT: ret
%1 = fptrunc double %b to float
store float %1, float* %a, align 4
ret void
diff --git a/llvm/test/CodeGen/RISCV/double-round-conv-sat.ll b/llvm/test/CodeGen/RISCV/double-round-conv-sat.ll
index 022705474451..787269f71950 100644
--- a/llvm/test/CodeGen/RISCV/double-round-conv-sat.ll
+++ b/llvm/test/CodeGen/RISCV/double-round-conv-sat.ll
@@ -1,27 +1,18 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \
-; RUN: -target-abi=ilp32d | FileCheck -check-prefix=RV32IFD %s
+; RUN: -target-abi=ilp32d | FileCheck -check-prefixes=CHECKIFD,RV32IFD %s
; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \
-; RUN: -target-abi=lp64d | FileCheck -check-prefix=RV64IFD %s
+; RUN: -target-abi=lp64d | FileCheck -check-prefixes=CHECKIFD,RV64IFD %s
define signext i32 @test_floor_si32(double %x) {
-; RV32IFD-LABEL: test_floor_si32:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: feq.d a0, fa0, fa0
-; RV32IFD-NEXT: beqz a0, .LBB0_2
-; RV32IFD-NEXT: # %bb.1:
-; RV32IFD-NEXT: fcvt.w.d a0, fa0, rdn
-; RV32IFD-NEXT: .LBB0_2:
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: test_floor_si32:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: feq.d a0, fa0, fa0
-; RV64IFD-NEXT: beqz a0, .LBB0_2
-; RV64IFD-NEXT: # %bb.1:
-; RV64IFD-NEXT: fcvt.w.d a0, fa0, rdn
-; RV64IFD-NEXT: .LBB0_2:
-; RV64IFD-NEXT: ret
+; CHECKIFD-LABEL: test_floor_si32:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: feq.d a0, fa0, fa0
+; CHECKIFD-NEXT: beqz a0, .LBB0_2
+; CHECKIFD-NEXT: # %bb.1:
+; CHECKIFD-NEXT: fcvt.w.d a0, fa0, rdn
+; CHECKIFD-NEXT: .LBB0_2:
+; CHECKIFD-NEXT: ret
%a = call double @llvm.floor.f64(double %x)
%b = call i32 @llvm.fptosi.sat.i32.f64(double %a)
ret i32 %b
@@ -98,23 +89,14 @@ define i64 @test_floor_si64(double %x) nounwind {
}
define signext i32 @test_floor_ui32(double %x) {
-; RV32IFD-LABEL: test_floor_ui32:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: feq.d a0, fa0, fa0
-; RV32IFD-NEXT: beqz a0, .LBB2_2
-; RV32IFD-NEXT: # %bb.1:
-; RV32IFD-NEXT: fcvt.wu.d a0, fa0, rdn
-; RV32IFD-NEXT: .LBB2_2:
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: test_floor_ui32:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: feq.d a0, fa0, fa0
-; RV64IFD-NEXT: beqz a0, .LBB2_2
-; RV64IFD-NEXT: # %bb.1:
-; RV64IFD-NEXT: fcvt.wu.d a0, fa0, rdn
-; RV64IFD-NEXT: .LBB2_2:
-; RV64IFD-NEXT: ret
+; CHECKIFD-LABEL: test_floor_ui32:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: feq.d a0, fa0, fa0
+; CHECKIFD-NEXT: beqz a0, .LBB2_2
+; CHECKIFD-NEXT: # %bb.1:
+; CHECKIFD-NEXT: fcvt.wu.d a0, fa0, rdn
+; CHECKIFD-NEXT: .LBB2_2:
+; CHECKIFD-NEXT: ret
%a = call double @llvm.floor.f64(double %x)
%b = call i32 @llvm.fptoui.sat.i32.f64(double %a)
ret i32 %b
@@ -178,23 +160,14 @@ define i64 @test_floor_ui64(double %x) nounwind {
}
define signext i32 @test_ceil_si32(double %x) {
-; RV32IFD-LABEL: test_ceil_si32:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: feq.d a0, fa0, fa0
-; RV32IFD-NEXT: beqz a0, .LBB4_2
-; RV32IFD-NEXT: # %bb.1:
-; RV32IFD-NEXT: fcvt.w.d a0, fa0, rup
-; RV32IFD-NEXT: .LBB4_2:
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: test_ceil_si32:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: feq.d a0, fa0, fa0
-; RV64IFD-NEXT: beqz a0, .LBB4_2
-; RV64IFD-NEXT: # %bb.1:
-; RV64IFD-NEXT: fcvt.w.d a0, fa0, rup
-; RV64IFD-NEXT: .LBB4_2:
-; RV64IFD-NEXT: ret
+; CHECKIFD-LABEL: test_ceil_si32:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: feq.d a0, fa0, fa0
+; CHECKIFD-NEXT: beqz a0, .LBB4_2
+; CHECKIFD-NEXT: # %bb.1:
+; CHECKIFD-NEXT: fcvt.w.d a0, fa0, rup
+; CHECKIFD-NEXT: .LBB4_2:
+; CHECKIFD-NEXT: ret
%a = call double @llvm.ceil.f64(double %x)
%b = call i32 @llvm.fptosi.sat.i32.f64(double %a)
ret i32 %b
@@ -271,23 +244,14 @@ define i64 @test_ceil_si64(double %x) nounwind {
}
define signext i32 @test_ceil_ui32(double %x) {
-; RV32IFD-LABEL: test_ceil_ui32:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: feq.d a0, fa0, fa0
-; RV32IFD-NEXT: beqz a0, .LBB6_2
-; RV32IFD-NEXT: # %bb.1:
-; RV32IFD-NEXT: fcvt.wu.d a0, fa0, rup
-; RV32IFD-NEXT: .LBB6_2:
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: test_ceil_ui32:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: feq.d a0, fa0, fa0
-; RV64IFD-NEXT: beqz a0, .LBB6_2
-; RV64IFD-NEXT: # %bb.1:
-; RV64IFD-NEXT: fcvt.wu.d a0, fa0, rup
-; RV64IFD-NEXT: .LBB6_2:
-; RV64IFD-NEXT: ret
+; CHECKIFD-LABEL: test_ceil_ui32:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: feq.d a0, fa0, fa0
+; CHECKIFD-NEXT: beqz a0, .LBB6_2
+; CHECKIFD-NEXT: # %bb.1:
+; CHECKIFD-NEXT: fcvt.wu.d a0, fa0, rup
+; CHECKIFD-NEXT: .LBB6_2:
+; CHECKIFD-NEXT: ret
%a = call double @llvm.ceil.f64(double %x)
%b = call i32 @llvm.fptoui.sat.i32.f64(double %a)
ret i32 %b
@@ -351,23 +315,14 @@ define i64 @test_ceil_ui64(double %x) nounwind {
}
define signext i32 @test_trunc_si32(double %x) {
-; RV32IFD-LABEL: test_trunc_si32:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: feq.d a0, fa0, fa0
-; RV32IFD-NEXT: beqz a0, .LBB8_2
-; RV32IFD-NEXT: # %bb.1:
-; RV32IFD-NEXT: fcvt.w.d a0, fa0, rtz
-; RV32IFD-NEXT: .LBB8_2:
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: test_trunc_si32:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: feq.d a0, fa0, fa0
-; RV64IFD-NEXT: beqz a0, .LBB8_2
-; RV64IFD-NEXT: # %bb.1:
-; RV64IFD-NEXT: fcvt.w.d a0, fa0, rtz
-; RV64IFD-NEXT: .LBB8_2:
-; RV64IFD-NEXT: ret
+; CHECKIFD-LABEL: test_trunc_si32:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: feq.d a0, fa0, fa0
+; CHECKIFD-NEXT: beqz a0, .LBB8_2
+; CHECKIFD-NEXT: # %bb.1:
+; CHECKIFD-NEXT: fcvt.w.d a0, fa0, rtz
+; CHECKIFD-NEXT: .LBB8_2:
+; CHECKIFD-NEXT: ret
%a = call double @llvm.trunc.f64(double %x)
%b = call i32 @llvm.fptosi.sat.i32.f64(double %a)
ret i32 %b
@@ -444,23 +399,14 @@ define i64 @test_trunc_si64(double %x) nounwind {
}
define signext i32 @test_trunc_ui32(double %x) {
-; RV32IFD-LABEL: test_trunc_ui32:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: feq.d a0, fa0, fa0
-; RV32IFD-NEXT: beqz a0, .LBB10_2
-; RV32IFD-NEXT: # %bb.1:
-; RV32IFD-NEXT: fcvt.wu.d a0, fa0, rtz
-; RV32IFD-NEXT: .LBB10_2:
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: test_trunc_ui32:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: feq.d a0, fa0, fa0
-; RV64IFD-NEXT: beqz a0, .LBB10_2
-; RV64IFD-NEXT: # %bb.1:
-; RV64IFD-NEXT: fcvt.wu.d a0, fa0, rtz
-; RV64IFD-NEXT: .LBB10_2:
-; RV64IFD-NEXT: ret
+; CHECKIFD-LABEL: test_trunc_ui32:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: feq.d a0, fa0, fa0
+; CHECKIFD-NEXT: beqz a0, .LBB10_2
+; CHECKIFD-NEXT: # %bb.1:
+; CHECKIFD-NEXT: fcvt.wu.d a0, fa0, rtz
+; CHECKIFD-NEXT: .LBB10_2:
+; CHECKIFD-NEXT: ret
%a = call double @llvm.trunc.f64(double %x)
%b = call i32 @llvm.fptoui.sat.i32.f64(double %a)
ret i32 %b
@@ -524,23 +470,14 @@ define i64 @test_trunc_ui64(double %x) nounwind {
}
define signext i32 @test_round_si32(double %x) {
-; RV32IFD-LABEL: test_round_si32:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: feq.d a0, fa0, fa0
-; RV32IFD-NEXT: beqz a0, .LBB12_2
-; RV32IFD-NEXT: # %bb.1:
-; RV32IFD-NEXT: fcvt.w.d a0, fa0, rmm
-; RV32IFD-NEXT: .LBB12_2:
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: test_round_si32:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: feq.d a0, fa0, fa0
-; RV64IFD-NEXT: beqz a0, .LBB12_2
-; RV64IFD-NEXT: # %bb.1:
-; RV64IFD-NEXT: fcvt.w.d a0, fa0, rmm
-; RV64IFD-NEXT: .LBB12_2:
-; RV64IFD-NEXT: ret
+; CHECKIFD-LABEL: test_round_si32:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: feq.d a0, fa0, fa0
+; CHECKIFD-NEXT: beqz a0, .LBB12_2
+; CHECKIFD-NEXT: # %bb.1:
+; CHECKIFD-NEXT: fcvt.w.d a0, fa0, rmm
+; CHECKIFD-NEXT: .LBB12_2:
+; CHECKIFD-NEXT: ret
%a = call double @llvm.round.f64(double %x)
%b = call i32 @llvm.fptosi.sat.i32.f64(double %a)
ret i32 %b
@@ -617,23 +554,14 @@ define i64 @test_round_si64(double %x) nounwind {
}
define signext i32 @test_round_ui32(double %x) {
-; RV32IFD-LABEL: test_round_ui32:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: feq.d a0, fa0, fa0
-; RV32IFD-NEXT: beqz a0, .LBB14_2
-; RV32IFD-NEXT: # %bb.1:
-; RV32IFD-NEXT: fcvt.wu.d a0, fa0, rmm
-; RV32IFD-NEXT: .LBB14_2:
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: test_round_ui32:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: feq.d a0, fa0, fa0
-; RV64IFD-NEXT: beqz a0, .LBB14_2
-; RV64IFD-NEXT: # %bb.1:
-; RV64IFD-NEXT: fcvt.wu.d a0, fa0, rmm
-; RV64IFD-NEXT: .LBB14_2:
-; RV64IFD-NEXT: ret
+; CHECKIFD-LABEL: test_round_ui32:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: feq.d a0, fa0, fa0
+; CHECKIFD-NEXT: beqz a0, .LBB14_2
+; CHECKIFD-NEXT: # %bb.1:
+; CHECKIFD-NEXT: fcvt.wu.d a0, fa0, rmm
+; CHECKIFD-NEXT: .LBB14_2:
+; CHECKIFD-NEXT: ret
%a = call double @llvm.round.f64(double %x)
%b = call i32 @llvm.fptoui.sat.i32.f64(double %a)
ret i32 %b
@@ -697,23 +625,14 @@ define i64 @test_round_ui64(double %x) nounwind {
}
define signext i32 @test_roundeven_si32(double %x) {
-; RV32IFD-LABEL: test_roundeven_si32:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: feq.d a0, fa0, fa0
-; RV32IFD-NEXT: beqz a0, .LBB16_2
-; RV32IFD-NEXT: # %bb.1:
-; RV32IFD-NEXT: fcvt.w.d a0, fa0, rne
-; RV32IFD-NEXT: .LBB16_2:
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: test_roundeven_si32:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: feq.d a0, fa0, fa0
-; RV64IFD-NEXT: beqz a0, .LBB16_2
-; RV64IFD-NEXT: # %bb.1:
-; RV64IFD-NEXT: fcvt.w.d a0, fa0, rne
-; RV64IFD-NEXT: .LBB16_2:
-; RV64IFD-NEXT: ret
+; CHECKIFD-LABEL: test_roundeven_si32:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: feq.d a0, fa0, fa0
+; CHECKIFD-NEXT: beqz a0, .LBB16_2
+; CHECKIFD-NEXT: # %bb.1:
+; CHECKIFD-NEXT: fcvt.w.d a0, fa0, rne
+; CHECKIFD-NEXT: .LBB16_2:
+; CHECKIFD-NEXT: ret
%a = call double @llvm.roundeven.f64(double %x)
%b = call i32 @llvm.fptosi.sat.i32.f64(double %a)
ret i32 %b
@@ -790,23 +709,14 @@ define i64 @test_roundeven_si64(double %x) nounwind {
}
define signext i32 @test_roundeven_ui32(double %x) {
-; RV32IFD-LABEL: test_roundeven_ui32:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: feq.d a0, fa0, fa0
-; RV32IFD-NEXT: beqz a0, .LBB18_2
-; RV32IFD-NEXT: # %bb.1:
-; RV32IFD-NEXT: fcvt.wu.d a0, fa0, rne
-; RV32IFD-NEXT: .LBB18_2:
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: test_roundeven_ui32:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: feq.d a0, fa0, fa0
-; RV64IFD-NEXT: beqz a0, .LBB18_2
-; RV64IFD-NEXT: # %bb.1:
-; RV64IFD-NEXT: fcvt.wu.d a0, fa0, rne
-; RV64IFD-NEXT: .LBB18_2:
-; RV64IFD-NEXT: ret
+; CHECKIFD-LABEL: test_roundeven_ui32:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: feq.d a0, fa0, fa0
+; CHECKIFD-NEXT: beqz a0, .LBB18_2
+; CHECKIFD-NEXT: # %bb.1:
+; CHECKIFD-NEXT: fcvt.wu.d a0, fa0, rne
+; CHECKIFD-NEXT: .LBB18_2:
+; CHECKIFD-NEXT: ret
%a = call double @llvm.roundeven.f64(double %x)
%b = call i32 @llvm.fptoui.sat.i32.f64(double %a)
ret i32 %b
diff --git a/llvm/test/CodeGen/RISCV/double-round-conv.ll b/llvm/test/CodeGen/RISCV/double-round-conv.ll
index f83a0fcb86a6..2bf5b6c2e2d7 100644
--- a/llvm/test/CodeGen/RISCV/double-round-conv.ll
+++ b/llvm/test/CodeGen/RISCV/double-round-conv.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \
-; RUN: -target-abi=ilp32d | FileCheck -check-prefix=RV32IFD %s
+; RUN: -target-abi=ilp32d | FileCheck -check-prefixes=CHECKIFD,RV32IFD %s
; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \
-; RUN: -target-abi=lp64d | FileCheck -check-prefix=RV64IFD %s
+; RUN: -target-abi=lp64d | FileCheck -check-prefixes=CHECKIFD,RV64IFD %s
define signext i8 @test_floor_si8(double %x) {
; RV32IFD-LABEL: test_floor_si8:
@@ -35,15 +35,10 @@ define signext i16 @test_floor_si16(double %x) {
}
define signext i32 @test_floor_si32(double %x) {
-; RV32IFD-LABEL: test_floor_si32:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: fcvt.w.d a0, fa0, rdn
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: test_floor_si32:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fcvt.w.d a0, fa0, rdn
-; RV64IFD-NEXT: ret
+; CHECKIFD-LABEL: test_floor_si32:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: fcvt.w.d a0, fa0, rdn
+; CHECKIFD-NEXT: ret
%a = call double @llvm.floor.f64(double %x)
%b = fptosi double %a to i32
ret i32 %b
@@ -102,15 +97,10 @@ define zeroext i16 @test_floor_ui16(double %x) {
}
define signext i32 @test_floor_ui32(double %x) {
-; RV32IFD-LABEL: test_floor_ui32:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: fcvt.wu.d a0, fa0, rdn
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: test_floor_ui32:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fcvt.wu.d a0, fa0, rdn
-; RV64IFD-NEXT: ret
+; CHECKIFD-LABEL: test_floor_ui32:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: fcvt.wu.d a0, fa0, rdn
+; CHECKIFD-NEXT: ret
%a = call double @llvm.floor.f64(double %x)
%b = fptoui double %a to i32
ret i32 %b
@@ -169,15 +159,10 @@ define signext i16 @test_ceil_si16(double %x) {
}
define signext i32 @test_ceil_si32(double %x) {
-; RV32IFD-LABEL: test_ceil_si32:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: fcvt.w.d a0, fa0, rup
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: test_ceil_si32:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fcvt.w.d a0, fa0, rup
-; RV64IFD-NEXT: ret
+; CHECKIFD-LABEL: test_ceil_si32:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: fcvt.w.d a0, fa0, rup
+; CHECKIFD-NEXT: ret
%a = call double @llvm.ceil.f64(double %x)
%b = fptosi double %a to i32
ret i32 %b
@@ -236,15 +221,10 @@ define zeroext i16 @test_ceil_ui16(double %x) {
}
define signext i32 @test_ceil_ui32(double %x) {
-; RV32IFD-LABEL: test_ceil_ui32:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: fcvt.wu.d a0, fa0, rup
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: test_ceil_ui32:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fcvt.wu.d a0, fa0, rup
-; RV64IFD-NEXT: ret
+; CHECKIFD-LABEL: test_ceil_ui32:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: fcvt.wu.d a0, fa0, rup
+; CHECKIFD-NEXT: ret
%a = call double @llvm.ceil.f64(double %x)
%b = fptoui double %a to i32
ret i32 %b
@@ -303,15 +283,10 @@ define signext i16 @test_trunc_si16(double %x) {
}
define signext i32 @test_trunc_si32(double %x) {
-; RV32IFD-LABEL: test_trunc_si32:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: fcvt.w.d a0, fa0, rtz
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: test_trunc_si32:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fcvt.w.d a0, fa0, rtz
-; RV64IFD-NEXT: ret
+; CHECKIFD-LABEL: test_trunc_si32:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: fcvt.w.d a0, fa0, rtz
+; CHECKIFD-NEXT: ret
%a = call double @llvm.trunc.f64(double %x)
%b = fptosi double %a to i32
ret i32 %b
@@ -370,15 +345,10 @@ define zeroext i16 @test_trunc_ui16(double %x) {
}
define signext i32 @test_trunc_ui32(double %x) {
-; RV32IFD-LABEL: test_trunc_ui32:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: fcvt.wu.d a0, fa0, rtz
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: test_trunc_ui32:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fcvt.wu.d a0, fa0, rtz
-; RV64IFD-NEXT: ret
+; CHECKIFD-LABEL: test_trunc_ui32:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: fcvt.wu.d a0, fa0, rtz
+; CHECKIFD-NEXT: ret
%a = call double @llvm.trunc.f64(double %x)
%b = fptoui double %a to i32
ret i32 %b
@@ -437,15 +407,10 @@ define signext i16 @test_round_si16(double %x) {
}
define signext i32 @test_round_si32(double %x) {
-; RV32IFD-LABEL: test_round_si32:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: fcvt.w.d a0, fa0, rmm
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: test_round_si32:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fcvt.w.d a0, fa0, rmm
-; RV64IFD-NEXT: ret
+; CHECKIFD-LABEL: test_round_si32:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: fcvt.w.d a0, fa0, rmm
+; CHECKIFD-NEXT: ret
%a = call double @llvm.round.f64(double %x)
%b = fptosi double %a to i32
ret i32 %b
@@ -504,15 +469,10 @@ define zeroext i16 @test_round_ui16(double %x) {
}
define signext i32 @test_round_ui32(double %x) {
-; RV32IFD-LABEL: test_round_ui32:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: fcvt.wu.d a0, fa0, rmm
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: test_round_ui32:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fcvt.wu.d a0, fa0, rmm
-; RV64IFD-NEXT: ret
+; CHECKIFD-LABEL: test_round_ui32:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: fcvt.wu.d a0, fa0, rmm
+; CHECKIFD-NEXT: ret
%a = call double @llvm.round.f64(double %x)
%b = fptoui double %a to i32
ret i32 %b
@@ -571,15 +531,10 @@ define signext i16 @test_roundeven_si16(double %x) {
}
define signext i32 @test_roundeven_si32(double %x) {
-; RV32IFD-LABEL: test_roundeven_si32:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: fcvt.w.d a0, fa0, rne
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: test_roundeven_si32:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fcvt.w.d a0, fa0, rne
-; RV64IFD-NEXT: ret
+; CHECKIFD-LABEL: test_roundeven_si32:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: fcvt.w.d a0, fa0, rne
+; CHECKIFD-NEXT: ret
%a = call double @llvm.roundeven.f64(double %x)
%b = fptosi double %a to i32
ret i32 %b
@@ -638,15 +593,10 @@ define zeroext i16 @test_roundeven_ui16(double %x) {
}
define signext i32 @test_roundeven_ui32(double %x) {
-; RV32IFD-LABEL: test_roundeven_ui32:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: fcvt.wu.d a0, fa0, rne
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: test_roundeven_ui32:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fcvt.wu.d a0, fa0, rne
-; RV64IFD-NEXT: ret
+; CHECKIFD-LABEL: test_roundeven_ui32:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: fcvt.wu.d a0, fa0, rne
+; CHECKIFD-NEXT: ret
%a = call double @llvm.roundeven.f64(double %x)
%b = fptoui double %a to i32
ret i32 %b
diff --git a/llvm/test/CodeGen/RISCV/double-select-fcmp.ll b/llvm/test/CodeGen/RISCV/double-select-fcmp.ll
index 3442c334d744..926bb92a2977 100644
--- a/llvm/test/CodeGen/RISCV/double-select-fcmp.ll
+++ b/llvm/test/CodeGen/RISCV/double-select-fcmp.ll
@@ -1,370 +1,227 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \
-; RUN: -target-abi=ilp32d | FileCheck -check-prefix=RV32IFD %s
+; RUN: -target-abi=ilp32d | FileCheck %s
; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \
-; RUN: -target-abi=lp64d | FileCheck -check-prefix=RV64IFD %s
+; RUN: -target-abi=lp64d | FileCheck %s
define double @select_fcmp_false(double %a, double %b) nounwind {
-; RV32IFD-LABEL: select_fcmp_false:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: fmv.d fa0, fa1
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: select_fcmp_false:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fmv.d fa0, fa1
-; RV64IFD-NEXT: ret
+; CHECK-LABEL: select_fcmp_false:
+; CHECK: # %bb.0:
+; CHECK-NEXT: fmv.d fa0, fa1
+; CHECK-NEXT: ret
%1 = fcmp false double %a, %b
%2 = select i1 %1, double %a, double %b
ret double %2
}
define double @select_fcmp_oeq(double %a, double %b) nounwind {
-; RV32IFD-LABEL: select_fcmp_oeq:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: feq.d a0, fa0, fa1
-; RV32IFD-NEXT: bnez a0, .LBB1_2
-; RV32IFD-NEXT: # %bb.1:
-; RV32IFD-NEXT: fmv.d fa0, fa1
-; RV32IFD-NEXT: .LBB1_2:
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: select_fcmp_oeq:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: feq.d a0, fa0, fa1
-; RV64IFD-NEXT: bnez a0, .LBB1_2
-; RV64IFD-NEXT: # %bb.1:
-; RV64IFD-NEXT: fmv.d fa0, fa1
-; RV64IFD-NEXT: .LBB1_2:
-; RV64IFD-NEXT: ret
+; CHECK-LABEL: select_fcmp_oeq:
+; CHECK: # %bb.0:
+; CHECK-NEXT: feq.d a0, fa0, fa1
+; CHECK-NEXT: bnez a0, .LBB1_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: fmv.d fa0, fa1
+; CHECK-NEXT: .LBB1_2:
+; CHECK-NEXT: ret
%1 = fcmp oeq double %a, %b
%2 = select i1 %1, double %a, double %b
ret double %2
}
define double @select_fcmp_ogt(double %a, double %b) nounwind {
-; RV32IFD-LABEL: select_fcmp_ogt:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: flt.d a0, fa1, fa0
-; RV32IFD-NEXT: bnez a0, .LBB2_2
-; RV32IFD-NEXT: # %bb.1:
-; RV32IFD-NEXT: fmv.d fa0, fa1
-; RV32IFD-NEXT: .LBB2_2:
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: select_fcmp_ogt:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: flt.d a0, fa1, fa0
-; RV64IFD-NEXT: bnez a0, .LBB2_2
-; RV64IFD-NEXT: # %bb.1:
-; RV64IFD-NEXT: fmv.d fa0, fa1
-; RV64IFD-NEXT: .LBB2_2:
-; RV64IFD-NEXT: ret
+; CHECK-LABEL: select_fcmp_ogt:
+; CHECK: # %bb.0:
+; CHECK-NEXT: flt.d a0, fa1, fa0
+; CHECK-NEXT: bnez a0, .LBB2_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: fmv.d fa0, fa1
+; CHECK-NEXT: .LBB2_2:
+; CHECK-NEXT: ret
%1 = fcmp ogt double %a, %b
%2 = select i1 %1, double %a, double %b
ret double %2
}
define double @select_fcmp_oge(double %a, double %b) nounwind {
-; RV32IFD-LABEL: select_fcmp_oge:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: fle.d a0, fa1, fa0
-; RV32IFD-NEXT: bnez a0, .LBB3_2
-; RV32IFD-NEXT: # %bb.1:
-; RV32IFD-NEXT: fmv.d fa0, fa1
-; RV32IFD-NEXT: .LBB3_2:
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: select_fcmp_oge:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fle.d a0, fa1, fa0
-; RV64IFD-NEXT: bnez a0, .LBB3_2
-; RV64IFD-NEXT: # %bb.1:
-; RV64IFD-NEXT: fmv.d fa0, fa1
-; RV64IFD-NEXT: .LBB3_2:
-; RV64IFD-NEXT: ret
+; CHECK-LABEL: select_fcmp_oge:
+; CHECK: # %bb.0:
+; CHECK-NEXT: fle.d a0, fa1, fa0
+; CHECK-NEXT: bnez a0, .LBB3_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: fmv.d fa0, fa1
+; CHECK-NEXT: .LBB3_2:
+; CHECK-NEXT: ret
%1 = fcmp oge double %a, %b
%2 = select i1 %1, double %a, double %b
ret double %2
}
define double @select_fcmp_olt(double %a, double %b) nounwind {
-; RV32IFD-LABEL: select_fcmp_olt:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: flt.d a0, fa0, fa1
-; RV32IFD-NEXT: bnez a0, .LBB4_2
-; RV32IFD-NEXT: # %bb.1:
-; RV32IFD-NEXT: fmv.d fa0, fa1
-; RV32IFD-NEXT: .LBB4_2:
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: select_fcmp_olt:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: flt.d a0, fa0, fa1
-; RV64IFD-NEXT: bnez a0, .LBB4_2
-; RV64IFD-NEXT: # %bb.1:
-; RV64IFD-NEXT: fmv.d fa0, fa1
-; RV64IFD-NEXT: .LBB4_2:
-; RV64IFD-NEXT: ret
+; CHECK-LABEL: select_fcmp_olt:
+; CHECK: # %bb.0:
+; CHECK-NEXT: flt.d a0, fa0, fa1
+; CHECK-NEXT: bnez a0, .LBB4_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: fmv.d fa0, fa1
+; CHECK-NEXT: .LBB4_2:
+; CHECK-NEXT: ret
%1 = fcmp olt double %a, %b
%2 = select i1 %1, double %a, double %b
ret double %2
}
define double @select_fcmp_ole(double %a, double %b) nounwind {
-; RV32IFD-LABEL: select_fcmp_ole:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: fle.d a0, fa0, fa1
-; RV32IFD-NEXT: bnez a0, .LBB5_2
-; RV32IFD-NEXT: # %bb.1:
-; RV32IFD-NEXT: fmv.d fa0, fa1
-; RV32IFD-NEXT: .LBB5_2:
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: select_fcmp_ole:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fle.d a0, fa0, fa1
-; RV64IFD-NEXT: bnez a0, .LBB5_2
-; RV64IFD-NEXT: # %bb.1:
-; RV64IFD-NEXT: fmv.d fa0, fa1
-; RV64IFD-NEXT: .LBB5_2:
-; RV64IFD-NEXT: ret
+; CHECK-LABEL: select_fcmp_ole:
+; CHECK: # %bb.0:
+; CHECK-NEXT: fle.d a0, fa0, fa1
+; CHECK-NEXT: bnez a0, .LBB5_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: fmv.d fa0, fa1
+; CHECK-NEXT: .LBB5_2:
+; CHECK-NEXT: ret
%1 = fcmp ole double %a, %b
%2 = select i1 %1, double %a, double %b
ret double %2
}
define double @select_fcmp_one(double %a, double %b) nounwind {
-; RV32IFD-LABEL: select_fcmp_one:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: flt.d a0, fa0, fa1
-; RV32IFD-NEXT: flt.d a1, fa1, fa0
-; RV32IFD-NEXT: or a0, a1, a0
-; RV32IFD-NEXT: bnez a0, .LBB6_2
-; RV32IFD-NEXT: # %bb.1:
-; RV32IFD-NEXT: fmv.d fa0, fa1
-; RV32IFD-NEXT: .LBB6_2:
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: select_fcmp_one:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: flt.d a0, fa0, fa1
-; RV64IFD-NEXT: flt.d a1, fa1, fa0
-; RV64IFD-NEXT: or a0, a1, a0
-; RV64IFD-NEXT: bnez a0, .LBB6_2
-; RV64IFD-NEXT: # %bb.1:
-; RV64IFD-NEXT: fmv.d fa0, fa1
-; RV64IFD-NEXT: .LBB6_2:
-; RV64IFD-NEXT: ret
+; CHECK-LABEL: select_fcmp_one:
+; CHECK: # %bb.0:
+; CHECK-NEXT: flt.d a0, fa0, fa1
+; CHECK-NEXT: flt.d a1, fa1, fa0
+; CHECK-NEXT: or a0, a1, a0
+; CHECK-NEXT: bnez a0, .LBB6_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: fmv.d fa0, fa1
+; CHECK-NEXT: .LBB6_2:
+; CHECK-NEXT: ret
%1 = fcmp one double %a, %b
%2 = select i1 %1, double %a, double %b
ret double %2
}
define double @select_fcmp_ord(double %a, double %b) nounwind {
-; RV32IFD-LABEL: select_fcmp_ord:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: feq.d a0, fa1, fa1
-; RV32IFD-NEXT: feq.d a1, fa0, fa0
-; RV32IFD-NEXT: and a0, a1, a0
-; RV32IFD-NEXT: bnez a0, .LBB7_2
-; RV32IFD-NEXT: # %bb.1:
-; RV32IFD-NEXT: fmv.d fa0, fa1
-; RV32IFD-NEXT: .LBB7_2:
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: select_fcmp_ord:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: feq.d a0, fa1, fa1
-; RV64IFD-NEXT: feq.d a1, fa0, fa0
-; RV64IFD-NEXT: and a0, a1, a0
-; RV64IFD-NEXT: bnez a0, .LBB7_2
-; RV64IFD-NEXT: # %bb.1:
-; RV64IFD-NEXT: fmv.d fa0, fa1
-; RV64IFD-NEXT: .LBB7_2:
-; RV64IFD-NEXT: ret
+; CHECK-LABEL: select_fcmp_ord:
+; CHECK: # %bb.0:
+; CHECK-NEXT: feq.d a0, fa1, fa1
+; CHECK-NEXT: feq.d a1, fa0, fa0
+; CHECK-NEXT: and a0, a1, a0
+; CHECK-NEXT: bnez a0, .LBB7_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: fmv.d fa0, fa1
+; CHECK-NEXT: .LBB7_2:
+; CHECK-NEXT: ret
%1 = fcmp ord double %a, %b
%2 = select i1 %1, double %a, double %b
ret double %2
}
define double @select_fcmp_ueq(double %a, double %b) nounwind {
-; RV32IFD-LABEL: select_fcmp_ueq:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: flt.d a0, fa0, fa1
-; RV32IFD-NEXT: flt.d a1, fa1, fa0
-; RV32IFD-NEXT: or a0, a1, a0
-; RV32IFD-NEXT: beqz a0, .LBB8_2
-; RV32IFD-NEXT: # %bb.1:
-; RV32IFD-NEXT: fmv.d fa0, fa1
-; RV32IFD-NEXT: .LBB8_2:
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: select_fcmp_ueq:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: flt.d a0, fa0, fa1
-; RV64IFD-NEXT: flt.d a1, fa1, fa0
-; RV64IFD-NEXT: or a0, a1, a0
-; RV64IFD-NEXT: beqz a0, .LBB8_2
-; RV64IFD-NEXT: # %bb.1:
-; RV64IFD-NEXT: fmv.d fa0, fa1
-; RV64IFD-NEXT: .LBB8_2:
-; RV64IFD-NEXT: ret
+; CHECK-LABEL: select_fcmp_ueq:
+; CHECK: # %bb.0:
+; CHECK-NEXT: flt.d a0, fa0, fa1
+; CHECK-NEXT: flt.d a1, fa1, fa0
+; CHECK-NEXT: or a0, a1, a0
+; CHECK-NEXT: beqz a0, .LBB8_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: fmv.d fa0, fa1
+; CHECK-NEXT: .LBB8_2:
+; CHECK-NEXT: ret
%1 = fcmp ueq double %a, %b
%2 = select i1 %1, double %a, double %b
ret double %2
}
define double @select_fcmp_ugt(double %a, double %b) nounwind {
-; RV32IFD-LABEL: select_fcmp_ugt:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: fle.d a0, fa0, fa1
-; RV32IFD-NEXT: beqz a0, .LBB9_2
-; RV32IFD-NEXT: # %bb.1:
-; RV32IFD-NEXT: fmv.d fa0, fa1
-; RV32IFD-NEXT: .LBB9_2:
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: select_fcmp_ugt:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fle.d a0, fa0, fa1
-; RV64IFD-NEXT: beqz a0, .LBB9_2
-; RV64IFD-NEXT: # %bb.1:
-; RV64IFD-NEXT: fmv.d fa0, fa1
-; RV64IFD-NEXT: .LBB9_2:
-; RV64IFD-NEXT: ret
+; CHECK-LABEL: select_fcmp_ugt:
+; CHECK: # %bb.0:
+; CHECK-NEXT: fle.d a0, fa0, fa1
+; CHECK-NEXT: beqz a0, .LBB9_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: fmv.d fa0, fa1
+; CHECK-NEXT: .LBB9_2:
+; CHECK-NEXT: ret
%1 = fcmp ugt double %a, %b
%2 = select i1 %1, double %a, double %b
ret double %2
}
define double @select_fcmp_uge(double %a, double %b) nounwind {
-; RV32IFD-LABEL: select_fcmp_uge:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: flt.d a0, fa0, fa1
-; RV32IFD-NEXT: beqz a0, .LBB10_2
-; RV32IFD-NEXT: # %bb.1:
-; RV32IFD-NEXT: fmv.d fa0, fa1
-; RV32IFD-NEXT: .LBB10_2:
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: select_fcmp_uge:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: flt.d a0, fa0, fa1
-; RV64IFD-NEXT: beqz a0, .LBB10_2
-; RV64IFD-NEXT: # %bb.1:
-; RV64IFD-NEXT: fmv.d fa0, fa1
-; RV64IFD-NEXT: .LBB10_2:
-; RV64IFD-NEXT: ret
+; CHECK-LABEL: select_fcmp_uge:
+; CHECK: # %bb.0:
+; CHECK-NEXT: flt.d a0, fa0, fa1
+; CHECK-NEXT: beqz a0, .LBB10_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: fmv.d fa0, fa1
+; CHECK-NEXT: .LBB10_2:
+; CHECK-NEXT: ret
%1 = fcmp uge double %a, %b
%2 = select i1 %1, double %a, double %b
ret double %2
}
define double @select_fcmp_ult(double %a, double %b) nounwind {
-; RV32IFD-LABEL: select_fcmp_ult:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: fle.d a0, fa1, fa0
-; RV32IFD-NEXT: beqz a0, .LBB11_2
-; RV32IFD-NEXT: # %bb.1:
-; RV32IFD-NEXT: fmv.d fa0, fa1
-; RV32IFD-NEXT: .LBB11_2:
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: select_fcmp_ult:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fle.d a0, fa1, fa0
-; RV64IFD-NEXT: beqz a0, .LBB11_2
-; RV64IFD-NEXT: # %bb.1:
-; RV64IFD-NEXT: fmv.d fa0, fa1
-; RV64IFD-NEXT: .LBB11_2:
-; RV64IFD-NEXT: ret
+; CHECK-LABEL: select_fcmp_ult:
+; CHECK: # %bb.0:
+; CHECK-NEXT: fle.d a0, fa1, fa0
+; CHECK-NEXT: beqz a0, .LBB11_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: fmv.d fa0, fa1
+; CHECK-NEXT: .LBB11_2:
+; CHECK-NEXT: ret
%1 = fcmp ult double %a, %b
%2 = select i1 %1, double %a, double %b
ret double %2
}
define double @select_fcmp_ule(double %a, double %b) nounwind {
-; RV32IFD-LABEL: select_fcmp_ule:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: flt.d a0, fa1, fa0
-; RV32IFD-NEXT: beqz a0, .LBB12_2
-; RV32IFD-NEXT: # %bb.1:
-; RV32IFD-NEXT: fmv.d fa0, fa1
-; RV32IFD-NEXT: .LBB12_2:
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: select_fcmp_ule:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: flt.d a0, fa1, fa0
-; RV64IFD-NEXT: beqz a0, .LBB12_2
-; RV64IFD-NEXT: # %bb.1:
-; RV64IFD-NEXT: fmv.d fa0, fa1
-; RV64IFD-NEXT: .LBB12_2:
-; RV64IFD-NEXT: ret
+; CHECK-LABEL: select_fcmp_ule:
+; CHECK: # %bb.0:
+; CHECK-NEXT: flt.d a0, fa1, fa0
+; CHECK-NEXT: beqz a0, .LBB12_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: fmv.d fa0, fa1
+; CHECK-NEXT: .LBB12_2:
+; CHECK-NEXT: ret
%1 = fcmp ule double %a, %b
%2 = select i1 %1, double %a, double %b
ret double %2
}
define double @select_fcmp_une(double %a, double %b) nounwind {
-; RV32IFD-LABEL: select_fcmp_une:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: feq.d a0, fa0, fa1
-; RV32IFD-NEXT: beqz a0, .LBB13_2
-; RV32IFD-NEXT: # %bb.1:
-; RV32IFD-NEXT: fmv.d fa0, fa1
-; RV32IFD-NEXT: .LBB13_2:
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: select_fcmp_une:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: feq.d a0, fa0, fa1
-; RV64IFD-NEXT: beqz a0, .LBB13_2
-; RV64IFD-NEXT: # %bb.1:
-; RV64IFD-NEXT: fmv.d fa0, fa1
-; RV64IFD-NEXT: .LBB13_2:
-; RV64IFD-NEXT: ret
+; CHECK-LABEL: select_fcmp_une:
+; CHECK: # %bb.0:
+; CHECK-NEXT: feq.d a0, fa0, fa1
+; CHECK-NEXT: beqz a0, .LBB13_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: fmv.d fa0, fa1
+; CHECK-NEXT: .LBB13_2:
+; CHECK-NEXT: ret
%1 = fcmp une double %a, %b
%2 = select i1 %1, double %a, double %b
ret double %2
}
define double @select_fcmp_uno(double %a, double %b) nounwind {
-; RV32IFD-LABEL: select_fcmp_uno:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: feq.d a0, fa1, fa1
-; RV32IFD-NEXT: feq.d a1, fa0, fa0
-; RV32IFD-NEXT: and a0, a1, a0
-; RV32IFD-NEXT: beqz a0, .LBB14_2
-; RV32IFD-NEXT: # %bb.1:
-; RV32IFD-NEXT: fmv.d fa0, fa1
-; RV32IFD-NEXT: .LBB14_2:
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: select_fcmp_uno:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: feq.d a0, fa1, fa1
-; RV64IFD-NEXT: feq.d a1, fa0, fa0
-; RV64IFD-NEXT: and a0, a1, a0
-; RV64IFD-NEXT: beqz a0, .LBB14_2
-; RV64IFD-NEXT: # %bb.1:
-; RV64IFD-NEXT: fmv.d fa0, fa1
-; RV64IFD-NEXT: .LBB14_2:
-; RV64IFD-NEXT: ret
+; CHECK-LABEL: select_fcmp_uno:
+; CHECK: # %bb.0:
+; CHECK-NEXT: feq.d a0, fa1, fa1
+; CHECK-NEXT: feq.d a1, fa0, fa0
+; CHECK-NEXT: and a0, a1, a0
+; CHECK-NEXT: beqz a0, .LBB14_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: fmv.d fa0, fa1
+; CHECK-NEXT: .LBB14_2:
+; CHECK-NEXT: ret
%1 = fcmp uno double %a, %b
%2 = select i1 %1, double %a, double %b
ret double %2
}
define double @select_fcmp_true(double %a, double %b) nounwind {
-; RV32IFD-LABEL: select_fcmp_true:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: select_fcmp_true:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: ret
+; CHECK-LABEL: select_fcmp_true:
+; CHECK: # %bb.0:
+; CHECK-NEXT: ret
%1 = fcmp true double %a, %b
%2 = select i1 %1, double %a, double %b
ret double %2
@@ -372,23 +229,14 @@ define double @select_fcmp_true(double %a, double %b) nounwind {
; Ensure that ISel succeeds for a select+fcmp that has an i32 result type.
define i32 @i32_select_fcmp_oeq(double %a, double %b, i32 %c, i32 %d) nounwind {
-; RV32IFD-LABEL: i32_select_fcmp_oeq:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: feq.d a2, fa0, fa1
-; RV32IFD-NEXT: bnez a2, .LBB16_2
-; RV32IFD-NEXT: # %bb.1:
-; RV32IFD-NEXT: mv a0, a1
-; RV32IFD-NEXT: .LBB16_2:
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: i32_select_fcmp_oeq:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: feq.d a2, fa0, fa1
-; RV64IFD-NEXT: bnez a2, .LBB16_2
-; RV64IFD-NEXT: # %bb.1:
-; RV64IFD-NEXT: mv a0, a1
-; RV64IFD-NEXT: .LBB16_2:
-; RV64IFD-NEXT: ret
+; CHECK-LABEL: i32_select_fcmp_oeq:
+; CHECK: # %bb.0:
+; CHECK-NEXT: feq.d a2, fa0, fa1
+; CHECK-NEXT: bnez a2, .LBB16_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: mv a0, a1
+; CHECK-NEXT: .LBB16_2:
+; CHECK-NEXT: ret
%1 = fcmp oeq double %a, %b
%2 = select i1 %1, i32 %c, i32 %d
ret i32 %2
diff --git a/llvm/test/CodeGen/RISCV/float-arith-strict.ll b/llvm/test/CodeGen/RISCV/float-arith-strict.ll
index e58110dca92c..89226ceab9e1 100644
--- a/llvm/test/CodeGen/RISCV/float-arith-strict.ll
+++ b/llvm/test/CodeGen/RISCV/float-arith-strict.ll
@@ -1,25 +1,20 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
; RUN: -disable-strictnode-mutation -target-abi=ilp32f \
-; RUN: | FileCheck -check-prefix=RV32IF %s
+; RUN: | FileCheck -check-prefixes=CHECKIF,RV32IF %s
; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
; RUN: -disable-strictnode-mutation -target-abi=lp64f \
-; RUN: | FileCheck -check-prefix=RV64IF %s
+; RUN: | FileCheck -check-prefixes=CHECKIF,RV64IF %s
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: -disable-strictnode-mutation | FileCheck -check-prefix=RV32I %s
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: -disable-strictnode-mutation | FileCheck -check-prefix=RV64I %s
define float @fadd_s(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fadd_s:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: fadd.s fa0, fa0, fa1
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: fadd_s:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: fadd.s fa0, fa0, fa1
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: fadd_s:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: fadd.s fa0, fa0, fa1
+; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fadd_s:
; RV32I: # %bb.0:
@@ -44,15 +39,10 @@ define float @fadd_s(float %a, float %b) nounwind strictfp {
declare float @llvm.experimental.constrained.fadd.f32(float, float, metadata, metadata)
define float @fsub_s(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fsub_s:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: fsub.s fa0, fa0, fa1
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: fsub_s:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: fsub.s fa0, fa0, fa1
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: fsub_s:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: fsub.s fa0, fa0, fa1
+; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fsub_s:
; RV32I: # %bb.0:
@@ -77,15 +67,10 @@ define float @fsub_s(float %a, float %b) nounwind strictfp {
declare float @llvm.experimental.constrained.fsub.f32(float, float, metadata, metadata)
define float @fmul_s(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fmul_s:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: fmul.s fa0, fa0, fa1
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: fmul_s:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: fmul.s fa0, fa0, fa1
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: fmul_s:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: fmul.s fa0, fa0, fa1
+; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fmul_s:
; RV32I: # %bb.0:
@@ -110,15 +95,10 @@ define float @fmul_s(float %a, float %b) nounwind strictfp {
declare float @llvm.experimental.constrained.fmul.f32(float, float, metadata, metadata)
define float @fdiv_s(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fdiv_s:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: fdiv.s fa0, fa0, fa1
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: fdiv_s:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: fdiv.s fa0, fa0, fa1
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: fdiv_s:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: fdiv.s fa0, fa0, fa1
+; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fdiv_s:
; RV32I: # %bb.0:
@@ -143,15 +123,10 @@ define float @fdiv_s(float %a, float %b) nounwind strictfp {
declare float @llvm.experimental.constrained.fdiv.f32(float, float, metadata, metadata)
define float @fsqrt_s(float %a) nounwind strictfp {
-; RV32IF-LABEL: fsqrt_s:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: fsqrt.s fa0, fa0
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: fsqrt_s:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: fsqrt.s fa0, fa0
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: fsqrt_s:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: fsqrt.s fa0, fa0
+; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fsqrt_s:
; RV32I: # %bb.0:
@@ -258,15 +233,10 @@ define float @fmax_s(float %a, float %b) nounwind strictfp {
declare float @llvm.experimental.constrained.maxnum.f32(float, float, metadata) strictfp
define float @fmadd_s(float %a, float %b, float %c) nounwind strictfp {
-; RV32IF-LABEL: fmadd_s:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: fmadd.s fa0, fa0, fa1, fa2
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: fmadd_s:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: fmadd.s fa0, fa0, fa1, fa2
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: fmadd_s:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: fmadd.s fa0, fa0, fa1, fa2
+; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fmadd_s:
; RV32I: # %bb.0:
@@ -291,19 +261,12 @@ define float @fmadd_s(float %a, float %b, float %c) nounwind strictfp {
declare float @llvm.experimental.constrained.fma.f32(float, float, float, metadata, metadata) strictfp
define float @fmsub_s(float %a, float %b, float %c) nounwind strictfp {
-; RV32IF-LABEL: fmsub_s:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: fmv.w.x ft0, zero
-; RV32IF-NEXT: fadd.s ft0, fa2, ft0
-; RV32IF-NEXT: fmsub.s fa0, fa0, fa1, ft0
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: fmsub_s:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: fmv.w.x ft0, zero
-; RV64IF-NEXT: fadd.s ft0, fa2, ft0
-; RV64IF-NEXT: fmsub.s fa0, fa0, fa1, ft0
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: fmsub_s:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: fmv.w.x ft0, zero
+; CHECKIF-NEXT: fadd.s ft0, fa2, ft0
+; CHECKIF-NEXT: fmsub.s fa0, fa0, fa1, ft0
+; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fmsub_s:
; RV32I: # %bb.0:
@@ -355,21 +318,13 @@ define float @fmsub_s(float %a, float %b, float %c) nounwind strictfp {
}
define float @fnmadd_s(float %a, float %b, float %c) nounwind strictfp {
-; RV32IF-LABEL: fnmadd_s:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: fmv.w.x ft0, zero
-; RV32IF-NEXT: fadd.s ft1, fa0, ft0
-; RV32IF-NEXT: fadd.s ft0, fa2, ft0
-; RV32IF-NEXT: fnmadd.s fa0, ft1, fa1, ft0
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: fnmadd_s:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: fmv.w.x ft0, zero
-; RV64IF-NEXT: fadd.s ft1, fa0, ft0
-; RV64IF-NEXT: fadd.s ft0, fa2, ft0
-; RV64IF-NEXT: fnmadd.s fa0, ft1, fa1, ft0
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: fnmadd_s:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: fmv.w.x ft0, zero
+; CHECKIF-NEXT: fadd.s ft1, fa0, ft0
+; CHECKIF-NEXT: fadd.s ft0, fa2, ft0
+; CHECKIF-NEXT: fnmadd.s fa0, ft1, fa1, ft0
+; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fnmadd_s:
; RV32I: # %bb.0:
@@ -435,21 +390,13 @@ define float @fnmadd_s(float %a, float %b, float %c) nounwind strictfp {
}
define float @fnmadd_s_2(float %a, float %b, float %c) nounwind strictfp {
-; RV32IF-LABEL: fnmadd_s_2:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: fmv.w.x ft0, zero
-; RV32IF-NEXT: fadd.s ft1, fa1, ft0
-; RV32IF-NEXT: fadd.s ft0, fa2, ft0
-; RV32IF-NEXT: fnmadd.s fa0, ft1, fa0, ft0
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: fnmadd_s_2:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: fmv.w.x ft0, zero
-; RV64IF-NEXT: fadd.s ft1, fa1, ft0
-; RV64IF-NEXT: fadd.s ft0, fa2, ft0
-; RV64IF-NEXT: fnmadd.s fa0, ft1, fa0, ft0
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: fnmadd_s_2:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: fmv.w.x ft0, zero
+; CHECKIF-NEXT: fadd.s ft1, fa1, ft0
+; CHECKIF-NEXT: fadd.s ft0, fa2, ft0
+; CHECKIF-NEXT: fnmadd.s fa0, ft1, fa0, ft0
+; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fnmadd_s_2:
; RV32I: # %bb.0:
@@ -515,19 +462,12 @@ define float @fnmadd_s_2(float %a, float %b, float %c) nounwind strictfp {
}
define float @fnmsub_s(float %a, float %b, float %c) nounwind strictfp {
-; RV32IF-LABEL: fnmsub_s:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: fmv.w.x ft0, zero
-; RV32IF-NEXT: fadd.s ft0, fa0, ft0
-; RV32IF-NEXT: fnmsub.s fa0, ft0, fa1, fa2
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: fnmsub_s:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: fmv.w.x ft0, zero
-; RV64IF-NEXT: fadd.s ft0, fa0, ft0
-; RV64IF-NEXT: fnmsub.s fa0, ft0, fa1, fa2
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: fnmsub_s:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: fmv.w.x ft0, zero
+; CHECKIF-NEXT: fadd.s ft0, fa0, ft0
+; CHECKIF-NEXT: fnmsub.s fa0, ft0, fa1, fa2
+; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fnmsub_s:
; RV32I: # %bb.0:
@@ -577,19 +517,12 @@ define float @fnmsub_s(float %a, float %b, float %c) nounwind strictfp {
}
define float @fnmsub_s_2(float %a, float %b, float %c) nounwind strictfp {
-; RV32IF-LABEL: fnmsub_s_2:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: fmv.w.x ft0, zero
-; RV32IF-NEXT: fadd.s ft0, fa1, ft0
-; RV32IF-NEXT: fnmsub.s fa0, ft0, fa0, fa2
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: fnmsub_s_2:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: fmv.w.x ft0, zero
-; RV64IF-NEXT: fadd.s ft0, fa1, ft0
-; RV64IF-NEXT: fnmsub.s fa0, ft0, fa0, fa2
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: fnmsub_s_2:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: fmv.w.x ft0, zero
+; CHECKIF-NEXT: fadd.s ft0, fa1, ft0
+; CHECKIF-NEXT: fnmsub.s fa0, ft0, fa0, fa2
+; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fnmsub_s_2:
; RV32I: # %bb.0:
diff --git a/llvm/test/CodeGen/RISCV/float-arith.ll b/llvm/test/CodeGen/RISCV/float-arith.ll
index 70ba36ee5a3b..66f60c0288ab 100644
--- a/llvm/test/CodeGen/RISCV/float-arith.ll
+++ b/llvm/test/CodeGen/RISCV/float-arith.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
-; RUN: -target-abi=ilp32f | FileCheck -check-prefix=RV32IF %s
+; RUN: -target-abi=ilp32f | FileCheck -check-prefix=CHECKIF %s
; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
-; RUN: -target-abi=lp64f | FileCheck -check-prefix=RV64IF %s
+; RUN: -target-abi=lp64f | FileCheck -check-prefix=CHECKIF %s
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32I %s
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
@@ -14,15 +14,10 @@
; instructions that don't directly match a RISC-V instruction.
define float @fadd_s(float %a, float %b) nounwind {
-; RV32IF-LABEL: fadd_s:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: fadd.s fa0, fa0, fa1
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: fadd_s:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: fadd.s fa0, fa0, fa1
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: fadd_s:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: fadd.s fa0, fa0, fa1
+; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fadd_s:
; RV32I: # %bb.0:
@@ -46,15 +41,10 @@ define float @fadd_s(float %a, float %b) nounwind {
}
define float @fsub_s(float %a, float %b) nounwind {
-; RV32IF-LABEL: fsub_s:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: fsub.s fa0, fa0, fa1
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: fsub_s:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: fsub.s fa0, fa0, fa1
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: fsub_s:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: fsub.s fa0, fa0, fa1
+; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fsub_s:
; RV32I: # %bb.0:
@@ -78,15 +68,10 @@ define float @fsub_s(float %a, float %b) nounwind {
}
define float @fmul_s(float %a, float %b) nounwind {
-; RV32IF-LABEL: fmul_s:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: fmul.s fa0, fa0, fa1
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: fmul_s:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: fmul.s fa0, fa0, fa1
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: fmul_s:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: fmul.s fa0, fa0, fa1
+; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fmul_s:
; RV32I: # %bb.0:
@@ -110,15 +95,10 @@ define float @fmul_s(float %a, float %b) nounwind {
}
define float @fdiv_s(float %a, float %b) nounwind {
-; RV32IF-LABEL: fdiv_s:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: fdiv.s fa0, fa0, fa1
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: fdiv_s:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: fdiv.s fa0, fa0, fa1
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: fdiv_s:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: fdiv.s fa0, fa0, fa1
+; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fdiv_s:
; RV32I: # %bb.0:
@@ -144,15 +124,10 @@ define float @fdiv_s(float %a, float %b) nounwind {
declare float @llvm.sqrt.f32(float)
define float @fsqrt_s(float %a) nounwind {
-; RV32IF-LABEL: fsqrt_s:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: fsqrt.s fa0, fa0
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: fsqrt_s:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: fsqrt.s fa0, fa0
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: fsqrt_s:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: fsqrt.s fa0, fa0
+; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fsqrt_s:
; RV32I: # %bb.0:
@@ -178,15 +153,10 @@ define float @fsqrt_s(float %a) nounwind {
declare float @llvm.copysign.f32(float, float)
define float @fsgnj_s(float %a, float %b) nounwind {
-; RV32IF-LABEL: fsgnj_s:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: fsgnj.s fa0, fa0, fa1
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: fsgnj_s:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: fsgnj.s fa0, fa0, fa1
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: fsgnj_s:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: fsgnj.s fa0, fa0, fa1
+; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fsgnj_s:
; RV32I: # %bb.0:
@@ -209,22 +179,13 @@ define float @fsgnj_s(float %a, float %b) nounwind {
ret float %1
}
-; This function performs extra work to ensure that
-; DAGCombiner::visitBITCAST doesn't replace the fneg with an xor.
define i32 @fneg_s(float %a, float %b) nounwind {
-; RV32IF-LABEL: fneg_s:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: fadd.s ft0, fa0, fa0
-; RV32IF-NEXT: fneg.s ft1, ft0
-; RV32IF-NEXT: feq.s a0, ft0, ft1
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: fneg_s:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: fadd.s ft0, fa0, fa0
-; RV64IF-NEXT: fneg.s ft1, ft0
-; RV64IF-NEXT: feq.s a0, ft0, ft1
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: fneg_s:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: fadd.s ft0, fa0, fa0
+; CHECKIF-NEXT: fneg.s ft1, ft0
+; CHECKIF-NEXT: feq.s a0, ft0, ft1
+; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fneg_s:
; RV32I: # %bb.0:
@@ -260,20 +221,12 @@ define i32 @fneg_s(float %a, float %b) nounwind {
ret i32 %4
}
-; This function performs extra work to ensure that
-; DAGCombiner::visitBITCAST doesn't replace the fneg with an xor.
define float @fsgnjn_s(float %a, float %b) nounwind {
-; RV32IF-LABEL: fsgnjn_s:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: fadd.s ft0, fa0, fa1
-; RV32IF-NEXT: fsgnjn.s fa0, fa0, ft0
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: fsgnjn_s:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: fadd.s ft0, fa0, fa1
-; RV64IF-NEXT: fsgnjn.s fa0, fa0, ft0
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: fsgnjn_s:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: fadd.s ft0, fa0, fa1
+; CHECKIF-NEXT: fsgnjn.s fa0, fa0, ft0
+; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fsgnjn_s:
; RV32I: # %bb.0:
@@ -318,22 +271,13 @@ define float @fsgnjn_s(float %a, float %b) nounwind {
declare float @llvm.fabs.f32(float)
-; This function performs extra work to ensure that
-; DAGCombiner::visitBITCAST doesn't replace the fabs with an and.
define float @fabs_s(float %a, float %b) nounwind {
-; RV32IF-LABEL: fabs_s:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: fadd.s ft0, fa0, fa1
-; RV32IF-NEXT: fabs.s ft1, ft0
-; RV32IF-NEXT: fadd.s fa0, ft1, ft0
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: fabs_s:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: fadd.s ft0, fa0, fa1
-; RV64IF-NEXT: fabs.s ft1, ft0
-; RV64IF-NEXT: fadd.s fa0, ft1, ft0
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: fabs_s:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: fadd.s ft0, fa0, fa1
+; CHECKIF-NEXT: fabs.s ft1, ft0
+; CHECKIF-NEXT: fadd.s fa0, ft1, ft0
+; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fabs_s:
; RV32I: # %bb.0:
@@ -369,15 +313,10 @@ define float @fabs_s(float %a, float %b) nounwind {
declare float @llvm.minnum.f32(float, float)
define float @fmin_s(float %a, float %b) nounwind {
-; RV32IF-LABEL: fmin_s:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: fmin.s fa0, fa0, fa1
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: fmin_s:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: fmin.s fa0, fa0, fa1
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: fmin_s:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: fmin.s fa0, fa0, fa1
+; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fmin_s:
; RV32I: # %bb.0:
@@ -403,15 +342,10 @@ define float @fmin_s(float %a, float %b) nounwind {
declare float @llvm.maxnum.f32(float, float)
define float @fmax_s(float %a, float %b) nounwind {
-; RV32IF-LABEL: fmax_s:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: fmax.s fa0, fa0, fa1
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: fmax_s:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: fmax.s fa0, fa0, fa1
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: fmax_s:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: fmax.s fa0, fa0, fa1
+; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fmax_s:
; RV32I: # %bb.0:
@@ -437,15 +371,10 @@ define float @fmax_s(float %a, float %b) nounwind {
declare float @llvm.fma.f32(float, float, float)
define float @fmadd_s(float %a, float %b, float %c) nounwind {
-; RV32IF-LABEL: fmadd_s:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: fmadd.s fa0, fa0, fa1, fa2
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: fmadd_s:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: fmadd.s fa0, fa0, fa1, fa2
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: fmadd_s:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: fmadd.s fa0, fa0, fa1, fa2
+; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fmadd_s:
; RV32I: # %bb.0:
@@ -469,19 +398,12 @@ define float @fmadd_s(float %a, float %b, float %c) nounwind {
}
define float @fmsub_s(float %a, float %b, float %c) nounwind {
-; RV32IF-LABEL: fmsub_s:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: fmv.w.x ft0, zero
-; RV32IF-NEXT: fadd.s ft0, fa2, ft0
-; RV32IF-NEXT: fmsub.s fa0, fa0, fa1, ft0
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: fmsub_s:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: fmv.w.x ft0, zero
-; RV64IF-NEXT: fadd.s ft0, fa2, ft0
-; RV64IF-NEXT: fmsub.s fa0, fa0, fa1, ft0
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: fmsub_s:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: fmv.w.x ft0, zero
+; CHECKIF-NEXT: fadd.s ft0, fa2, ft0
+; CHECKIF-NEXT: fmsub.s fa0, fa0, fa1, ft0
+; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fmsub_s:
; RV32I: # %bb.0:
@@ -533,21 +455,13 @@ define float @fmsub_s(float %a, float %b, float %c) nounwind {
}
define float @fnmadd_s(float %a, float %b, float %c) nounwind {
-; RV32IF-LABEL: fnmadd_s:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: fmv.w.x ft0, zero
-; RV32IF-NEXT: fadd.s ft1, fa0, ft0
-; RV32IF-NEXT: fadd.s ft0, fa2, ft0
-; RV32IF-NEXT: fnmadd.s fa0, ft1, fa1, ft0
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: fnmadd_s:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: fmv.w.x ft0, zero
-; RV64IF-NEXT: fadd.s ft1, fa0, ft0
-; RV64IF-NEXT: fadd.s ft0, fa2, ft0
-; RV64IF-NEXT: fnmadd.s fa0, ft1, fa1, ft0
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: fnmadd_s:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: fmv.w.x ft0, zero
+; CHECKIF-NEXT: fadd.s ft1, fa0, ft0
+; CHECKIF-NEXT: fadd.s ft0, fa2, ft0
+; CHECKIF-NEXT: fnmadd.s fa0, ft1, fa1, ft0
+; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fnmadd_s:
; RV32I: # %bb.0:
@@ -613,21 +527,13 @@ define float @fnmadd_s(float %a, float %b, float %c) nounwind {
}
define float @fnmadd_s_2(float %a, float %b, float %c) nounwind {
-; RV32IF-LABEL: fnmadd_s_2:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: fmv.w.x ft0, zero
-; RV32IF-NEXT: fadd.s ft1, fa1, ft0
-; RV32IF-NEXT: fadd.s ft0, fa2, ft0
-; RV32IF-NEXT: fnmadd.s fa0, ft1, fa0, ft0
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: fnmadd_s_2:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: fmv.w.x ft0, zero
-; RV64IF-NEXT: fadd.s ft1, fa1, ft0
-; RV64IF-NEXT: fadd.s ft0, fa2, ft0
-; RV64IF-NEXT: fnmadd.s fa0, ft1, fa0, ft0
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: fnmadd_s_2:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: fmv.w.x ft0, zero
+; CHECKIF-NEXT: fadd.s ft1, fa1, ft0
+; CHECKIF-NEXT: fadd.s ft0, fa2, ft0
+; CHECKIF-NEXT: fnmadd.s fa0, ft1, fa0, ft0
+; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fnmadd_s_2:
; RV32I: # %bb.0:
@@ -769,19 +675,12 @@ define float @fnmadd_nsz(float %a, float %b, float %c) nounwind {
}
define float @fnmsub_s(float %a, float %b, float %c) nounwind {
-; RV32IF-LABEL: fnmsub_s:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: fmv.w.x ft0, zero
-; RV32IF-NEXT: fadd.s ft0, fa0, ft0
-; RV32IF-NEXT: fnmsub.s fa0, ft0, fa1, fa2
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: fnmsub_s:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: fmv.w.x ft0, zero
-; RV64IF-NEXT: fadd.s ft0, fa0, ft0
-; RV64IF-NEXT: fnmsub.s fa0, ft0, fa1, fa2
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: fnmsub_s:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: fmv.w.x ft0, zero
+; CHECKIF-NEXT: fadd.s ft0, fa0, ft0
+; CHECKIF-NEXT: fnmsub.s fa0, ft0, fa1, fa2
+; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fnmsub_s:
; RV32I: # %bb.0:
@@ -831,19 +730,12 @@ define float @fnmsub_s(float %a, float %b, float %c) nounwind {
}
define float @fnmsub_s_2(float %a, float %b, float %c) nounwind {
-; RV32IF-LABEL: fnmsub_s_2:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: fmv.w.x ft0, zero
-; RV32IF-NEXT: fadd.s ft0, fa1, ft0
-; RV32IF-NEXT: fnmsub.s fa0, ft0, fa0, fa2
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: fnmsub_s_2:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: fmv.w.x ft0, zero
-; RV64IF-NEXT: fadd.s ft0, fa1, ft0
-; RV64IF-NEXT: fnmsub.s fa0, ft0, fa0, fa2
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: fnmsub_s_2:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: fmv.w.x ft0, zero
+; CHECKIF-NEXT: fadd.s ft0, fa1, ft0
+; CHECKIF-NEXT: fnmsub.s fa0, ft0, fa0, fa2
+; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fnmsub_s_2:
; RV32I: # %bb.0:
@@ -895,15 +787,10 @@ define float @fnmsub_s_2(float %a, float %b, float %c) nounwind {
}
define float @fmadd_s_contract(float %a, float %b, float %c) nounwind {
-; RV32IF-LABEL: fmadd_s_contract:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: fmadd.s fa0, fa0, fa1, fa2
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: fmadd_s_contract:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: fmadd.s fa0, fa0, fa1, fa2
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: fmadd_s_contract:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: fmadd.s fa0, fa0, fa1, fa2
+; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fmadd_s_contract:
; RV32I: # %bb.0:
@@ -938,19 +825,12 @@ define float @fmadd_s_contract(float %a, float %b, float %c) nounwind {
}
define float @fmsub_s_contract(float %a, float %b, float %c) nounwind {
-; RV32IF-LABEL: fmsub_s_contract:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: fmv.w.x ft0, zero
-; RV32IF-NEXT: fadd.s ft0, fa2, ft0
-; RV32IF-NEXT: fmsub.s fa0, fa0, fa1, ft0
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: fmsub_s_contract:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: fmv.w.x ft0, zero
-; RV64IF-NEXT: fadd.s ft0, fa2, ft0
-; RV64IF-NEXT: fmsub.s fa0, fa0, fa1, ft0
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: fmsub_s_contract:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: fmv.w.x ft0, zero
+; CHECKIF-NEXT: fadd.s ft0, fa2, ft0
+; CHECKIF-NEXT: fmsub.s fa0, fa0, fa1, ft0
+; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fmsub_s_contract:
; RV32I: # %bb.0:
@@ -1008,23 +888,14 @@ define float @fmsub_s_contract(float %a, float %b, float %c) nounwind {
}
define float @fnmadd_s_contract(float %a, float %b, float %c) nounwind {
-; RV32IF-LABEL: fnmadd_s_contract:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: fmv.w.x ft0, zero
-; RV32IF-NEXT: fadd.s ft1, fa0, ft0
-; RV32IF-NEXT: fadd.s ft2, fa1, ft0
-; RV32IF-NEXT: fadd.s ft0, fa2, ft0
-; RV32IF-NEXT: fnmadd.s fa0, ft1, ft2, ft0
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: fnmadd_s_contract:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: fmv.w.x ft0, zero
-; RV64IF-NEXT: fadd.s ft1, fa0, ft0
-; RV64IF-NEXT: fadd.s ft2, fa1, ft0
-; RV64IF-NEXT: fadd.s ft0, fa2, ft0
-; RV64IF-NEXT: fnmadd.s fa0, ft1, ft2, ft0
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: fnmadd_s_contract:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: fmv.w.x ft0, zero
+; CHECKIF-NEXT: fadd.s ft1, fa0, ft0
+; CHECKIF-NEXT: fadd.s ft2, fa1, ft0
+; CHECKIF-NEXT: fadd.s ft0, fa2, ft0
+; CHECKIF-NEXT: fnmadd.s fa0, ft1, ft2, ft0
+; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fnmadd_s_contract:
; RV32I: # %bb.0:
@@ -1103,21 +974,13 @@ define float @fnmadd_s_contract(float %a, float %b, float %c) nounwind {
}
define float @fnmsub_s_contract(float %a, float %b, float %c) nounwind {
-; RV32IF-LABEL: fnmsub_s_contract:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: fmv.w.x ft0, zero
-; RV32IF-NEXT: fadd.s ft1, fa0, ft0
-; RV32IF-NEXT: fadd.s ft0, fa1, ft0
-; RV32IF-NEXT: fnmsub.s fa0, ft1, ft0, fa2
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: fnmsub_s_contract:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: fmv.w.x ft0, zero
-; RV64IF-NEXT: fadd.s ft1, fa0, ft0
-; RV64IF-NEXT: fadd.s ft0, fa1, ft0
-; RV64IF-NEXT: fnmsub.s fa0, ft1, ft0, fa2
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: fnmsub_s_contract:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: fmv.w.x ft0, zero
+; CHECKIF-NEXT: fadd.s ft1, fa0, ft0
+; CHECKIF-NEXT: fadd.s ft0, fa1, ft0
+; CHECKIF-NEXT: fnmsub.s fa0, ft1, ft0, fa2
+; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fnmsub_s_contract:
; RV32I: # %bb.0:
diff --git a/llvm/test/CodeGen/RISCV/float-convert-strict.ll b/llvm/test/CodeGen/RISCV/float-convert-strict.ll
index b391dbdffa47..d92fb35828c5 100644
--- a/llvm/test/CodeGen/RISCV/float-convert-strict.ll
+++ b/llvm/test/CodeGen/RISCV/float-convert-strict.ll
@@ -1,10 +1,10 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
; RUN: -disable-strictnode-mutation -target-abi=ilp32f \
-; RUN: | FileCheck -check-prefix=RV32IF %s
+; RUN: | FileCheck -check-prefixes=CHECKIF,RV32IF %s
; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
; RUN: -disable-strictnode-mutation -target-abi=lp64f \
-; RUN: | FileCheck -check-prefix=RV64IF %s
+; RUN: | FileCheck -check-prefixes=CHECKIF,RV64IF %s
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: -disable-strictnode-mutation | FileCheck -check-prefix=RV32I %s
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
@@ -15,15 +15,10 @@
; support rounding mode.
define i32 @fcvt_w_s(float %a) nounwind strictfp {
-; RV32IF-LABEL: fcvt_w_s:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: fcvt.w.s a0, fa0, rtz
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: fcvt_w_s:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: fcvt.w.s a0, fa0, rtz
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: fcvt_w_s:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: fcvt.w.s a0, fa0, rtz
+; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fcvt_w_s:
; RV32I: # %bb.0:
@@ -48,15 +43,10 @@ define i32 @fcvt_w_s(float %a) nounwind strictfp {
declare i32 @llvm.experimental.constrained.fptosi.i32.f32(float, metadata)
define i32 @fcvt_wu_s(float %a) nounwind strictfp {
-; RV32IF-LABEL: fcvt_wu_s:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: fcvt.wu.s a0, fa0, rtz
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: fcvt_wu_s:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: fcvt.wu.s a0, fa0, rtz
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: fcvt_wu_s:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: fcvt.wu.s a0, fa0, rtz
+; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fcvt_wu_s:
; RV32I: # %bb.0:
@@ -83,25 +73,15 @@ declare i32 @llvm.experimental.constrained.fptoui.i32.f32(float, metadata)
; Test where the fptoui has multiple uses, one of which causes a sext to be
; inserted on RV64.
define i32 @fcvt_wu_s_multiple_use(float %x, i32* %y) nounwind {
-; RV32IF-LABEL: fcvt_wu_s_multiple_use:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: fcvt.wu.s a1, fa0, rtz
-; RV32IF-NEXT: li a0, 1
-; RV32IF-NEXT: beqz a1, .LBB2_2
-; RV32IF-NEXT: # %bb.1:
-; RV32IF-NEXT: mv a0, a1
-; RV32IF-NEXT: .LBB2_2:
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: fcvt_wu_s_multiple_use:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: fcvt.wu.s a1, fa0, rtz
-; RV64IF-NEXT: li a0, 1
-; RV64IF-NEXT: beqz a1, .LBB2_2
-; RV64IF-NEXT: # %bb.1:
-; RV64IF-NEXT: mv a0, a1
-; RV64IF-NEXT: .LBB2_2:
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: fcvt_wu_s_multiple_use:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: fcvt.wu.s a1, fa0, rtz
+; CHECKIF-NEXT: li a0, 1
+; CHECKIF-NEXT: beqz a1, .LBB2_2
+; CHECKIF-NEXT: # %bb.1:
+; CHECKIF-NEXT: mv a0, a1
+; CHECKIF-NEXT: .LBB2_2:
+; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fcvt_wu_s_multiple_use:
; RV32I: # %bb.0:
@@ -139,15 +119,10 @@ define i32 @fcvt_wu_s_multiple_use(float %x, i32* %y) nounwind {
}
define float @fcvt_s_w(i32 %a) nounwind strictfp {
-; RV32IF-LABEL: fcvt_s_w:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: fcvt.s.w fa0, a0
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: fcvt_s_w:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: fcvt.s.w fa0, a0
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: fcvt_s_w:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: fcvt.s.w fa0, a0
+; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fcvt_s_w:
; RV32I: # %bb.0:
@@ -173,17 +148,11 @@ define float @fcvt_s_w(i32 %a) nounwind strictfp {
declare float @llvm.experimental.constrained.sitofp.f32.i32(i32, metadata, metadata)
define float @fcvt_s_w_load(i32* %p) nounwind strictfp {
-; RV32IF-LABEL: fcvt_s_w_load:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: lw a0, 0(a0)
-; RV32IF-NEXT: fcvt.s.w fa0, a0
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: fcvt_s_w_load:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: lw a0, 0(a0)
-; RV64IF-NEXT: fcvt.s.w fa0, a0
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: fcvt_s_w_load:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: lw a0, 0(a0)
+; CHECKIF-NEXT: fcvt.s.w fa0, a0
+; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fcvt_s_w_load:
; RV32I: # %bb.0:
@@ -210,15 +179,10 @@ define float @fcvt_s_w_load(i32* %p) nounwind strictfp {
}
define float @fcvt_s_wu(i32 %a) nounwind strictfp {
-; RV32IF-LABEL: fcvt_s_wu:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: fcvt.s.wu fa0, a0
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: fcvt_s_wu:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: fcvt.s.wu fa0, a0
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: fcvt_s_wu:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: fcvt.s.wu fa0, a0
+; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fcvt_s_wu:
; RV32I: # %bb.0:
@@ -429,15 +393,10 @@ define float @fcvt_s_lu(i64 %a) nounwind strictfp {
declare float @llvm.experimental.constrained.uitofp.f32.i64(i64, metadata, metadata)
define float @fcvt_s_w_i8(i8 signext %a) nounwind strictfp {
-; RV32IF-LABEL: fcvt_s_w_i8:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: fcvt.s.w fa0, a0
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: fcvt_s_w_i8:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: fcvt.s.w fa0, a0
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: fcvt_s_w_i8:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: fcvt.s.w fa0, a0
+; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fcvt_s_w_i8:
; RV32I: # %bb.0:
@@ -462,15 +421,10 @@ define float @fcvt_s_w_i8(i8 signext %a) nounwind strictfp {
declare float @llvm.experimental.constrained.sitofp.f32.i8(i8, metadata, metadata)
define float @fcvt_s_wu_i8(i8 zeroext %a) nounwind strictfp {
-; RV32IF-LABEL: fcvt_s_wu_i8:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: fcvt.s.wu fa0, a0
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: fcvt_s_wu_i8:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: fcvt.s.wu fa0, a0
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: fcvt_s_wu_i8:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: fcvt.s.wu fa0, a0
+; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fcvt_s_wu_i8:
; RV32I: # %bb.0:
@@ -495,15 +449,10 @@ define float @fcvt_s_wu_i8(i8 zeroext %a) nounwind strictfp {
declare float @llvm.experimental.constrained.uitofp.f32.i8(i8, metadata, metadata)
define float @fcvt_s_w_i16(i16 signext %a) nounwind strictfp {
-; RV32IF-LABEL: fcvt_s_w_i16:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: fcvt.s.w fa0, a0
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: fcvt_s_w_i16:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: fcvt.s.w fa0, a0
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: fcvt_s_w_i16:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: fcvt.s.w fa0, a0
+; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fcvt_s_w_i16:
; RV32I: # %bb.0:
@@ -528,15 +477,10 @@ define float @fcvt_s_w_i16(i16 signext %a) nounwind strictfp {
declare float @llvm.experimental.constrained.sitofp.f32.i16(i16, metadata, metadata)
define float @fcvt_s_wu_i16(i16 zeroext %a) nounwind strictfp {
-; RV32IF-LABEL: fcvt_s_wu_i16:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: fcvt.s.wu fa0, a0
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: fcvt_s_wu_i16:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: fcvt.s.wu fa0, a0
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: fcvt_s_wu_i16:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: fcvt.s.wu fa0, a0
+; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fcvt_s_wu_i16:
; RV32I: # %bb.0:
diff --git a/llvm/test/CodeGen/RISCV/float-convert.ll b/llvm/test/CodeGen/RISCV/float-convert.ll
index 97ec565448b0..f96558444d06 100644
--- a/llvm/test/CodeGen/RISCV/float-convert.ll
+++ b/llvm/test/CodeGen/RISCV/float-convert.ll
@@ -1,23 +1,18 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
-; RUN: -target-abi=ilp32f | FileCheck -check-prefix=RV32IF %s
+; RUN: -target-abi=ilp32f | FileCheck -check-prefixes=CHECKIF,RV32IF %s
; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
-; RUN: -target-abi=lp64f | FileCheck -check-prefix=RV64IF %s
+; RUN: -target-abi=lp64f | FileCheck -check-prefixes=CHECKIF,RV64IF %s
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32I %s
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64I %s
define i32 @fcvt_w_s(float %a) nounwind {
-; RV32IF-LABEL: fcvt_w_s:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: fcvt.w.s a0, fa0, rtz
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: fcvt_w_s:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: fcvt.w.s a0, fa0, rtz
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: fcvt_w_s:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: fcvt.w.s a0, fa0, rtz
+; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fcvt_w_s:
; RV32I: # %bb.0:
@@ -41,23 +36,14 @@ define i32 @fcvt_w_s(float %a) nounwind {
}
define i32 @fcvt_w_s_sat(float %a) nounwind {
-; RV32IF-LABEL: fcvt_w_s_sat:
-; RV32IF: # %bb.0: # %start
-; RV32IF-NEXT: feq.s a0, fa0, fa0
-; RV32IF-NEXT: beqz a0, .LBB1_2
-; RV32IF-NEXT: # %bb.1:
-; RV32IF-NEXT: fcvt.w.s a0, fa0, rtz
-; RV32IF-NEXT: .LBB1_2: # %start
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: fcvt_w_s_sat:
-; RV64IF: # %bb.0: # %start
-; RV64IF-NEXT: feq.s a0, fa0, fa0
-; RV64IF-NEXT: beqz a0, .LBB1_2
-; RV64IF-NEXT: # %bb.1:
-; RV64IF-NEXT: fcvt.w.s a0, fa0, rtz
-; RV64IF-NEXT: .LBB1_2: # %start
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: fcvt_w_s_sat:
+; CHECKIF: # %bb.0: # %start
+; CHECKIF-NEXT: feq.s a0, fa0, fa0
+; CHECKIF-NEXT: beqz a0, .LBB1_2
+; CHECKIF-NEXT: # %bb.1:
+; CHECKIF-NEXT: fcvt.w.s a0, fa0, rtz
+; CHECKIF-NEXT: .LBB1_2: # %start
+; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fcvt_w_s_sat:
; RV32I: # %bb.0: # %start
@@ -159,15 +145,10 @@ start:
declare i32 @llvm.fptosi.sat.i32.f32(float)
define i32 @fcvt_wu_s(float %a) nounwind {
-; RV32IF-LABEL: fcvt_wu_s:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: fcvt.wu.s a0, fa0, rtz
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: fcvt_wu_s:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: fcvt.wu.s a0, fa0, rtz
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: fcvt_wu_s:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: fcvt.wu.s a0, fa0, rtz
+; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fcvt_wu_s:
; RV32I: # %bb.0:
@@ -193,25 +174,15 @@ define i32 @fcvt_wu_s(float %a) nounwind {
; Test where the fptoui has multiple uses, one of which causes a sext to be
; inserted on RV64.
define i32 @fcvt_wu_s_multiple_use(float %x, i32* %y) nounwind {
-; RV32IF-LABEL: fcvt_wu_s_multiple_use:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: fcvt.wu.s a1, fa0, rtz
-; RV32IF-NEXT: li a0, 1
-; RV32IF-NEXT: beqz a1, .LBB3_2
-; RV32IF-NEXT: # %bb.1:
-; RV32IF-NEXT: mv a0, a1
-; RV32IF-NEXT: .LBB3_2:
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: fcvt_wu_s_multiple_use:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: fcvt.wu.s a1, fa0, rtz
-; RV64IF-NEXT: li a0, 1
-; RV64IF-NEXT: beqz a1, .LBB3_2
-; RV64IF-NEXT: # %bb.1:
-; RV64IF-NEXT: mv a0, a1
-; RV64IF-NEXT: .LBB3_2:
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: fcvt_wu_s_multiple_use:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: fcvt.wu.s a1, fa0, rtz
+; CHECKIF-NEXT: li a0, 1
+; CHECKIF-NEXT: beqz a1, .LBB3_2
+; CHECKIF-NEXT: # %bb.1:
+; CHECKIF-NEXT: mv a0, a1
+; CHECKIF-NEXT: .LBB3_2:
+; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fcvt_wu_s_multiple_use:
; RV32I: # %bb.0:
@@ -249,23 +220,14 @@ define i32 @fcvt_wu_s_multiple_use(float %x, i32* %y) nounwind {
}
define i32 @fcvt_wu_s_sat(float %a) nounwind {
-; RV32IF-LABEL: fcvt_wu_s_sat:
-; RV32IF: # %bb.0: # %start
-; RV32IF-NEXT: feq.s a0, fa0, fa0
-; RV32IF-NEXT: beqz a0, .LBB4_2
-; RV32IF-NEXT: # %bb.1:
-; RV32IF-NEXT: fcvt.wu.s a0, fa0, rtz
-; RV32IF-NEXT: .LBB4_2: # %start
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: fcvt_wu_s_sat:
-; RV64IF: # %bb.0: # %start
-; RV64IF-NEXT: feq.s a0, fa0, fa0
-; RV64IF-NEXT: beqz a0, .LBB4_2
-; RV64IF-NEXT: # %bb.1:
-; RV64IF-NEXT: fcvt.wu.s a0, fa0, rtz
-; RV64IF-NEXT: .LBB4_2: # %start
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: fcvt_wu_s_sat:
+; CHECKIF: # %bb.0: # %start
+; CHECKIF-NEXT: feq.s a0, fa0, fa0
+; CHECKIF-NEXT: beqz a0, .LBB4_2
+; CHECKIF-NEXT: # %bb.1:
+; CHECKIF-NEXT: fcvt.wu.s a0, fa0, rtz
+; CHECKIF-NEXT: .LBB4_2: # %start
+; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fcvt_wu_s_sat:
; RV32I: # %bb.0: # %start
@@ -343,17 +305,11 @@ start:
declare i32 @llvm.fptoui.sat.i32.f32(float)
define i32 @fmv_x_w(float %a, float %b) nounwind {
-; RV32IF-LABEL: fmv_x_w:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: fadd.s ft0, fa0, fa1
-; RV32IF-NEXT: fmv.x.w a0, ft0
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: fmv_x_w:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: fadd.s ft0, fa0, fa1
-; RV64IF-NEXT: fmv.x.w a0, ft0
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: fmv_x_w:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: fadd.s ft0, fa0, fa1
+; CHECKIF-NEXT: fmv.x.w a0, ft0
+; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fmv_x_w:
; RV32I: # %bb.0:
@@ -379,15 +335,10 @@ define i32 @fmv_x_w(float %a, float %b) nounwind {
}
define float @fcvt_s_w(i32 %a) nounwind {
-; RV32IF-LABEL: fcvt_s_w:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: fcvt.s.w fa0, a0
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: fcvt_s_w:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: fcvt.s.w fa0, a0
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: fcvt_s_w:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: fcvt.s.w fa0, a0
+; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fcvt_s_w:
; RV32I: # %bb.0:
@@ -412,17 +363,11 @@ define float @fcvt_s_w(i32 %a) nounwind {
}
define float @fcvt_s_w_load(i32* %p) nounwind {
-; RV32IF-LABEL: fcvt_s_w_load:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: lw a0, 0(a0)
-; RV32IF-NEXT: fcvt.s.w fa0, a0
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: fcvt_s_w_load:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: lw a0, 0(a0)
-; RV64IF-NEXT: fcvt.s.w fa0, a0
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: fcvt_s_w_load:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: lw a0, 0(a0)
+; CHECKIF-NEXT: fcvt.s.w fa0, a0
+; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fcvt_s_w_load:
; RV32I: # %bb.0:
@@ -449,15 +394,10 @@ define float @fcvt_s_w_load(i32* %p) nounwind {
}
define float @fcvt_s_wu(i32 %a) nounwind {
-; RV32IF-LABEL: fcvt_s_wu:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: fcvt.s.wu fa0, a0
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: fcvt_s_wu:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: fcvt.s.wu fa0, a0
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: fcvt_s_wu:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: fcvt.s.wu fa0, a0
+; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fcvt_s_wu:
; RV32I: # %bb.0:
@@ -519,19 +459,12 @@ define float @fcvt_s_wu_load(i32* %p) nounwind {
}
define float @fmv_w_x(i32 %a, i32 %b) nounwind {
-; RV32IF-LABEL: fmv_w_x:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: fmv.w.x ft0, a0
-; RV32IF-NEXT: fmv.w.x ft1, a1
-; RV32IF-NEXT: fadd.s fa0, ft0, ft1
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: fmv_w_x:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: fmv.w.x ft0, a0
-; RV64IF-NEXT: fmv.w.x ft1, a1
-; RV64IF-NEXT: fadd.s fa0, ft0, ft1
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: fmv_w_x:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: fmv.w.x ft0, a0
+; CHECKIF-NEXT: fmv.w.x ft1, a1
+; CHECKIF-NEXT: fadd.s fa0, ft0, ft1
+; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fmv_w_x:
; RV32I: # %bb.0:
@@ -1051,15 +984,10 @@ define float @fcvt_s_lu(i64 %a) nounwind {
}
define float @fcvt_s_w_i8(i8 signext %a) nounwind {
-; RV32IF-LABEL: fcvt_s_w_i8:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: fcvt.s.w fa0, a0
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: fcvt_s_w_i8:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: fcvt.s.w fa0, a0
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: fcvt_s_w_i8:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: fcvt.s.w fa0, a0
+; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fcvt_s_w_i8:
; RV32I: # %bb.0:
@@ -1083,15 +1011,10 @@ define float @fcvt_s_w_i8(i8 signext %a) nounwind {
}
define float @fcvt_s_wu_i8(i8 zeroext %a) nounwind {
-; RV32IF-LABEL: fcvt_s_wu_i8:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: fcvt.s.wu fa0, a0
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: fcvt_s_wu_i8:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: fcvt.s.wu fa0, a0
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: fcvt_s_wu_i8:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: fcvt.s.wu fa0, a0
+; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fcvt_s_wu_i8:
; RV32I: # %bb.0:
@@ -1115,15 +1038,10 @@ define float @fcvt_s_wu_i8(i8 zeroext %a) nounwind {
}
define float @fcvt_s_w_i16(i16 signext %a) nounwind {
-; RV32IF-LABEL: fcvt_s_w_i16:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: fcvt.s.w fa0, a0
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: fcvt_s_w_i16:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: fcvt.s.w fa0, a0
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: fcvt_s_w_i16:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: fcvt.s.w fa0, a0
+; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fcvt_s_w_i16:
; RV32I: # %bb.0:
@@ -1147,15 +1065,10 @@ define float @fcvt_s_w_i16(i16 signext %a) nounwind {
}
define float @fcvt_s_wu_i16(i16 zeroext %a) nounwind {
-; RV32IF-LABEL: fcvt_s_wu_i16:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: fcvt.s.wu fa0, a0
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: fcvt_s_wu_i16:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: fcvt.s.wu fa0, a0
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: fcvt_s_wu_i16:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: fcvt.s.wu fa0, a0
+; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fcvt_s_wu_i16:
; RV32I: # %bb.0:
diff --git a/llvm/test/CodeGen/RISCV/float-fcmp-strict.ll b/llvm/test/CodeGen/RISCV/float-fcmp-strict.ll
index 64b57cedaf14..de9ed5e25821 100644
--- a/llvm/test/CodeGen/RISCV/float-fcmp-strict.ll
+++ b/llvm/test/CodeGen/RISCV/float-fcmp-strict.ll
@@ -1,25 +1,20 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
; RUN: -disable-strictnode-mutation -target-abi=ilp32f \
-; RUN: | FileCheck -check-prefix=RV32IF %s
+; RUN: | FileCheck -check-prefix=CHECKIF %s
; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
; RUN: -disable-strictnode-mutation -target-abi=lp64f \
-; RUN: | FileCheck -check-prefix=RV64IF %s
+; RUN: | FileCheck -check-prefix=CHECKIF %s
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: -disable-strictnode-mutation | FileCheck -check-prefix=RV32I %s
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: -disable-strictnode-mutation | FileCheck -check-prefix=RV64I %s
define i32 @fcmp_oeq(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fcmp_oeq:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: feq.s a0, fa0, fa1
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: fcmp_oeq:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: feq.s a0, fa0, fa1
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: fcmp_oeq:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: feq.s a0, fa0, fa1
+; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fcmp_oeq:
; RV32I: # %bb.0:
@@ -47,21 +42,13 @@ define i32 @fcmp_oeq(float %a, float %b) nounwind strictfp {
declare i1 @llvm.experimental.constrained.fcmp.f32(float, float, metadata, metadata)
define i32 @fcmp_ogt(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fcmp_ogt:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: frflags a1
-; RV32IF-NEXT: flt.s a0, fa1, fa0
-; RV32IF-NEXT: fsflags a1
-; RV32IF-NEXT: feq.s zero, fa1, fa0
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: fcmp_ogt:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: frflags a1
-; RV64IF-NEXT: flt.s a0, fa1, fa0
-; RV64IF-NEXT: fsflags a1
-; RV64IF-NEXT: feq.s zero, fa1, fa0
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: fcmp_ogt:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: frflags a1
+; CHECKIF-NEXT: flt.s a0, fa1, fa0
+; CHECKIF-NEXT: fsflags a1
+; CHECKIF-NEXT: feq.s zero, fa1, fa0
+; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fcmp_ogt:
; RV32I: # %bb.0:
@@ -88,21 +75,13 @@ define i32 @fcmp_ogt(float %a, float %b) nounwind strictfp {
}
define i32 @fcmp_oge(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fcmp_oge:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: frflags a1
-; RV32IF-NEXT: fle.s a0, fa1, fa0
-; RV32IF-NEXT: fsflags a1
-; RV32IF-NEXT: feq.s zero, fa1, fa0
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: fcmp_oge:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: frflags a1
-; RV64IF-NEXT: fle.s a0, fa1, fa0
-; RV64IF-NEXT: fsflags a1
-; RV64IF-NEXT: feq.s zero, fa1, fa0
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: fcmp_oge:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: frflags a1
+; CHECKIF-NEXT: fle.s a0, fa1, fa0
+; CHECKIF-NEXT: fsflags a1
+; CHECKIF-NEXT: feq.s zero, fa1, fa0
+; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fcmp_oge:
; RV32I: # %bb.0:
@@ -131,21 +110,13 @@ define i32 @fcmp_oge(float %a, float %b) nounwind strictfp {
}
define i32 @fcmp_olt(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fcmp_olt:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: frflags a1
-; RV32IF-NEXT: flt.s a0, fa0, fa1
-; RV32IF-NEXT: fsflags a1
-; RV32IF-NEXT: feq.s zero, fa0, fa1
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: fcmp_olt:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: frflags a1
-; RV64IF-NEXT: flt.s a0, fa0, fa1
-; RV64IF-NEXT: fsflags a1
-; RV64IF-NEXT: feq.s zero, fa0, fa1
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: fcmp_olt:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: frflags a1
+; CHECKIF-NEXT: flt.s a0, fa0, fa1
+; CHECKIF-NEXT: fsflags a1
+; CHECKIF-NEXT: feq.s zero, fa0, fa1
+; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fcmp_olt:
; RV32I: # %bb.0:
@@ -172,21 +143,13 @@ define i32 @fcmp_olt(float %a, float %b) nounwind strictfp {
}
define i32 @fcmp_ole(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fcmp_ole:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: frflags a1
-; RV32IF-NEXT: fle.s a0, fa0, fa1
-; RV32IF-NEXT: fsflags a1
-; RV32IF-NEXT: feq.s zero, fa0, fa1
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: fcmp_ole:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: frflags a1
-; RV64IF-NEXT: fle.s a0, fa0, fa1
-; RV64IF-NEXT: fsflags a1
-; RV64IF-NEXT: feq.s zero, fa0, fa1
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: fcmp_ole:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: frflags a1
+; CHECKIF-NEXT: fle.s a0, fa0, fa1
+; CHECKIF-NEXT: fsflags a1
+; CHECKIF-NEXT: feq.s zero, fa0, fa1
+; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fcmp_ole:
; RV32I: # %bb.0:
@@ -215,31 +178,18 @@ define i32 @fcmp_ole(float %a, float %b) nounwind strictfp {
; FIXME: We only need one frflags before the two flts and one fsflags after the
; two flts.
define i32 @fcmp_one(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fcmp_one:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: frflags a0
-; RV32IF-NEXT: flt.s a1, fa0, fa1
-; RV32IF-NEXT: fsflags a0
-; RV32IF-NEXT: feq.s zero, fa0, fa1
-; RV32IF-NEXT: frflags a0
-; RV32IF-NEXT: flt.s a2, fa1, fa0
-; RV32IF-NEXT: fsflags a0
-; RV32IF-NEXT: or a0, a2, a1
-; RV32IF-NEXT: feq.s zero, fa1, fa0
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: fcmp_one:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: frflags a0
-; RV64IF-NEXT: flt.s a1, fa0, fa1
-; RV64IF-NEXT: fsflags a0
-; RV64IF-NEXT: feq.s zero, fa0, fa1
-; RV64IF-NEXT: frflags a0
-; RV64IF-NEXT: flt.s a2, fa1, fa0
-; RV64IF-NEXT: fsflags a0
-; RV64IF-NEXT: or a0, a2, a1
-; RV64IF-NEXT: feq.s zero, fa1, fa0
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: fcmp_one:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: frflags a0
+; CHECKIF-NEXT: flt.s a1, fa0, fa1
+; CHECKIF-NEXT: fsflags a0
+; CHECKIF-NEXT: feq.s zero, fa0, fa1
+; CHECKIF-NEXT: frflags a0
+; CHECKIF-NEXT: flt.s a2, fa1, fa0
+; CHECKIF-NEXT: fsflags a0
+; CHECKIF-NEXT: or a0, a2, a1
+; CHECKIF-NEXT: feq.s zero, fa1, fa0
+; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fcmp_one:
; RV32I: # %bb.0:
@@ -292,19 +242,12 @@ define i32 @fcmp_one(float %a, float %b) nounwind strictfp {
}
define i32 @fcmp_ord(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fcmp_ord:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: feq.s a0, fa1, fa1
-; RV32IF-NEXT: feq.s a1, fa0, fa0
-; RV32IF-NEXT: and a0, a1, a0
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: fcmp_ord:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: feq.s a0, fa1, fa1
-; RV64IF-NEXT: feq.s a1, fa0, fa0
-; RV64IF-NEXT: and a0, a1, a0
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: fcmp_ord:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: feq.s a0, fa1, fa1
+; CHECKIF-NEXT: feq.s a1, fa0, fa0
+; CHECKIF-NEXT: and a0, a1, a0
+; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fcmp_ord:
; RV32I: # %bb.0:
@@ -333,33 +276,19 @@ define i32 @fcmp_ord(float %a, float %b) nounwind strictfp {
; FIXME: We only need one frflags before the two flts and one fsflags after the
; two flts.
define i32 @fcmp_ueq(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fcmp_ueq:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: frflags a0
-; RV32IF-NEXT: flt.s a1, fa0, fa1
-; RV32IF-NEXT: fsflags a0
-; RV32IF-NEXT: feq.s zero, fa0, fa1
-; RV32IF-NEXT: frflags a0
-; RV32IF-NEXT: flt.s a2, fa1, fa0
-; RV32IF-NEXT: fsflags a0
-; RV32IF-NEXT: or a0, a2, a1
-; RV32IF-NEXT: xori a0, a0, 1
-; RV32IF-NEXT: feq.s zero, fa1, fa0
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: fcmp_ueq:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: frflags a0
-; RV64IF-NEXT: flt.s a1, fa0, fa1
-; RV64IF-NEXT: fsflags a0
-; RV64IF-NEXT: feq.s zero, fa0, fa1
-; RV64IF-NEXT: frflags a0
-; RV64IF-NEXT: flt.s a2, fa1, fa0
-; RV64IF-NEXT: fsflags a0
-; RV64IF-NEXT: or a0, a2, a1
-; RV64IF-NEXT: xori a0, a0, 1
-; RV64IF-NEXT: feq.s zero, fa1, fa0
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: fcmp_ueq:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: frflags a0
+; CHECKIF-NEXT: flt.s a1, fa0, fa1
+; CHECKIF-NEXT: fsflags a0
+; CHECKIF-NEXT: feq.s zero, fa0, fa1
+; CHECKIF-NEXT: frflags a0
+; CHECKIF-NEXT: flt.s a2, fa1, fa0
+; CHECKIF-NEXT: fsflags a0
+; CHECKIF-NEXT: or a0, a2, a1
+; CHECKIF-NEXT: xori a0, a0, 1
+; CHECKIF-NEXT: feq.s zero, fa1, fa0
+; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fcmp_ueq:
; RV32I: # %bb.0:
@@ -412,23 +341,14 @@ define i32 @fcmp_ueq(float %a, float %b) nounwind strictfp {
}
define i32 @fcmp_ugt(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fcmp_ugt:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: frflags a0
-; RV32IF-NEXT: fle.s a1, fa0, fa1
-; RV32IF-NEXT: fsflags a0
-; RV32IF-NEXT: xori a0, a1, 1
-; RV32IF-NEXT: feq.s zero, fa0, fa1
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: fcmp_ugt:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: frflags a0
-; RV64IF-NEXT: fle.s a1, fa0, fa1
-; RV64IF-NEXT: fsflags a0
-; RV64IF-NEXT: xori a0, a1, 1
-; RV64IF-NEXT: feq.s zero, fa0, fa1
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: fcmp_ugt:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: frflags a0
+; CHECKIF-NEXT: fle.s a1, fa0, fa1
+; CHECKIF-NEXT: fsflags a0
+; CHECKIF-NEXT: xori a0, a1, 1
+; CHECKIF-NEXT: feq.s zero, fa0, fa1
+; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fcmp_ugt:
; RV32I: # %bb.0:
@@ -455,23 +375,14 @@ define i32 @fcmp_ugt(float %a, float %b) nounwind strictfp {
}
define i32 @fcmp_uge(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fcmp_uge:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: frflags a0
-; RV32IF-NEXT: flt.s a1, fa0, fa1
-; RV32IF-NEXT: fsflags a0
-; RV32IF-NEXT: xori a0, a1, 1
-; RV32IF-NEXT: feq.s zero, fa0, fa1
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: fcmp_uge:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: frflags a0
-; RV64IF-NEXT: flt.s a1, fa0, fa1
-; RV64IF-NEXT: fsflags a0
-; RV64IF-NEXT: xori a0, a1, 1
-; RV64IF-NEXT: feq.s zero, fa0, fa1
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: fcmp_uge:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: frflags a0
+; CHECKIF-NEXT: flt.s a1, fa0, fa1
+; CHECKIF-NEXT: fsflags a0
+; CHECKIF-NEXT: xori a0, a1, 1
+; CHECKIF-NEXT: feq.s zero, fa0, fa1
+; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fcmp_uge:
; RV32I: # %bb.0:
@@ -500,23 +411,14 @@ define i32 @fcmp_uge(float %a, float %b) nounwind strictfp {
}
define i32 @fcmp_ult(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fcmp_ult:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: frflags a0
-; RV32IF-NEXT: fle.s a1, fa1, fa0
-; RV32IF-NEXT: fsflags a0
-; RV32IF-NEXT: xori a0, a1, 1
-; RV32IF-NEXT: feq.s zero, fa1, fa0
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: fcmp_ult:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: frflags a0
-; RV64IF-NEXT: fle.s a1, fa1, fa0
-; RV64IF-NEXT: fsflags a0
-; RV64IF-NEXT: xori a0, a1, 1
-; RV64IF-NEXT: feq.s zero, fa1, fa0
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: fcmp_ult:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: frflags a0
+; CHECKIF-NEXT: fle.s a1, fa1, fa0
+; CHECKIF-NEXT: fsflags a0
+; CHECKIF-NEXT: xori a0, a1, 1
+; CHECKIF-NEXT: feq.s zero, fa1, fa0
+; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fcmp_ult:
; RV32I: # %bb.0:
@@ -543,23 +445,14 @@ define i32 @fcmp_ult(float %a, float %b) nounwind strictfp {
}
define i32 @fcmp_ule(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fcmp_ule:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: frflags a0
-; RV32IF-NEXT: flt.s a1, fa1, fa0
-; RV32IF-NEXT: fsflags a0
-; RV32IF-NEXT: xori a0, a1, 1
-; RV32IF-NEXT: feq.s zero, fa1, fa0
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: fcmp_ule:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: frflags a0
-; RV64IF-NEXT: flt.s a1, fa1, fa0
-; RV64IF-NEXT: fsflags a0
-; RV64IF-NEXT: xori a0, a1, 1
-; RV64IF-NEXT: feq.s zero, fa1, fa0
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: fcmp_ule:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: frflags a0
+; CHECKIF-NEXT: flt.s a1, fa1, fa0
+; CHECKIF-NEXT: fsflags a0
+; CHECKIF-NEXT: xori a0, a1, 1
+; CHECKIF-NEXT: feq.s zero, fa1, fa0
+; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fcmp_ule:
; RV32I: # %bb.0:
@@ -586,17 +479,11 @@ define i32 @fcmp_ule(float %a, float %b) nounwind strictfp {
}
define i32 @fcmp_une(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fcmp_une:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: feq.s a0, fa0, fa1
-; RV32IF-NEXT: xori a0, a0, 1
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: fcmp_une:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: feq.s a0, fa0, fa1
-; RV64IF-NEXT: xori a0, a0, 1
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: fcmp_une:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: feq.s a0, fa0, fa1
+; CHECKIF-NEXT: xori a0, a0, 1
+; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fcmp_une:
; RV32I: # %bb.0:
@@ -623,21 +510,13 @@ define i32 @fcmp_une(float %a, float %b) nounwind strictfp {
}
define i32 @fcmp_uno(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fcmp_uno:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: feq.s a0, fa1, fa1
-; RV32IF-NEXT: feq.s a1, fa0, fa0
-; RV32IF-NEXT: and a0, a1, a0
-; RV32IF-NEXT: xori a0, a0, 1
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: fcmp_uno:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: feq.s a0, fa1, fa1
-; RV64IF-NEXT: feq.s a1, fa0, fa0
-; RV64IF-NEXT: and a0, a1, a0
-; RV64IF-NEXT: xori a0, a0, 1
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: fcmp_uno:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: feq.s a0, fa1, fa1
+; CHECKIF-NEXT: feq.s a1, fa0, fa0
+; CHECKIF-NEXT: and a0, a1, a0
+; CHECKIF-NEXT: xori a0, a0, 1
+; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fcmp_uno:
; RV32I: # %bb.0:
@@ -664,19 +543,12 @@ define i32 @fcmp_uno(float %a, float %b) nounwind strictfp {
}
define i32 @fcmps_oeq(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fcmps_oeq:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: fle.s a0, fa1, fa0
-; RV32IF-NEXT: fle.s a1, fa0, fa1
-; RV32IF-NEXT: and a0, a1, a0
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: fcmps_oeq:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: fle.s a0, fa1, fa0
-; RV64IF-NEXT: fle.s a1, fa0, fa1
-; RV64IF-NEXT: and a0, a1, a0
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: fcmps_oeq:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: fle.s a0, fa1, fa0
+; CHECKIF-NEXT: fle.s a1, fa0, fa1
+; CHECKIF-NEXT: and a0, a1, a0
+; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fcmps_oeq:
; RV32I: # %bb.0:
@@ -704,15 +576,10 @@ define i32 @fcmps_oeq(float %a, float %b) nounwind strictfp {
declare i1 @llvm.experimental.constrained.fcmps.f32(float, float, metadata, metadata)
define i32 @fcmps_ogt(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fcmps_ogt:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: flt.s a0, fa1, fa0
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: fcmps_ogt:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: flt.s a0, fa1, fa0
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: fcmps_ogt:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: flt.s a0, fa1, fa0
+; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fcmps_ogt:
; RV32I: # %bb.0:
@@ -739,15 +606,10 @@ define i32 @fcmps_ogt(float %a, float %b) nounwind strictfp {
}
define i32 @fcmps_oge(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fcmps_oge:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: fle.s a0, fa1, fa0
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: fcmps_oge:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: fle.s a0, fa1, fa0
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: fcmps_oge:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: fle.s a0, fa1, fa0
+; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fcmps_oge:
; RV32I: # %bb.0:
@@ -776,15 +638,10 @@ define i32 @fcmps_oge(float %a, float %b) nounwind strictfp {
}
define i32 @fcmps_olt(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fcmps_olt:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: flt.s a0, fa0, fa1
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: fcmps_olt:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: flt.s a0, fa0, fa1
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: fcmps_olt:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: flt.s a0, fa0, fa1
+; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fcmps_olt:
; RV32I: # %bb.0:
@@ -811,15 +668,10 @@ define i32 @fcmps_olt(float %a, float %b) nounwind strictfp {
}
define i32 @fcmps_ole(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fcmps_ole:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: fle.s a0, fa0, fa1
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: fcmps_ole:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: fle.s a0, fa0, fa1
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: fcmps_ole:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: fle.s a0, fa0, fa1
+; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fcmps_ole:
; RV32I: # %bb.0:
@@ -846,19 +698,12 @@ define i32 @fcmps_ole(float %a, float %b) nounwind strictfp {
}
define i32 @fcmps_one(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fcmps_one:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: flt.s a0, fa0, fa1
-; RV32IF-NEXT: flt.s a1, fa1, fa0
-; RV32IF-NEXT: or a0, a1, a0
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: fcmps_one:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: flt.s a0, fa0, fa1
-; RV64IF-NEXT: flt.s a1, fa1, fa0
-; RV64IF-NEXT: or a0, a1, a0
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: fcmps_one:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: flt.s a0, fa0, fa1
+; CHECKIF-NEXT: flt.s a1, fa1, fa0
+; CHECKIF-NEXT: or a0, a1, a0
+; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fcmps_one:
; RV32I: # %bb.0:
@@ -911,19 +756,12 @@ define i32 @fcmps_one(float %a, float %b) nounwind strictfp {
}
define i32 @fcmps_ord(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fcmps_ord:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: fle.s a0, fa1, fa1
-; RV32IF-NEXT: fle.s a1, fa0, fa0
-; RV32IF-NEXT: and a0, a1, a0
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: fcmps_ord:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: fle.s a0, fa1, fa1
-; RV64IF-NEXT: fle.s a1, fa0, fa0
-; RV64IF-NEXT: and a0, a1, a0
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: fcmps_ord:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: fle.s a0, fa1, fa1
+; CHECKIF-NEXT: fle.s a1, fa0, fa0
+; CHECKIF-NEXT: and a0, a1, a0
+; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fcmps_ord:
; RV32I: # %bb.0:
@@ -950,21 +788,13 @@ define i32 @fcmps_ord(float %a, float %b) nounwind strictfp {
}
define i32 @fcmps_ueq(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fcmps_ueq:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: flt.s a0, fa0, fa1
-; RV32IF-NEXT: flt.s a1, fa1, fa0
-; RV32IF-NEXT: or a0, a1, a0
-; RV32IF-NEXT: xori a0, a0, 1
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: fcmps_ueq:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: flt.s a0, fa0, fa1
-; RV64IF-NEXT: flt.s a1, fa1, fa0
-; RV64IF-NEXT: or a0, a1, a0
-; RV64IF-NEXT: xori a0, a0, 1
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: fcmps_ueq:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: flt.s a0, fa0, fa1
+; CHECKIF-NEXT: flt.s a1, fa1, fa0
+; CHECKIF-NEXT: or a0, a1, a0
+; CHECKIF-NEXT: xori a0, a0, 1
+; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fcmps_ueq:
; RV32I: # %bb.0:
@@ -1017,17 +847,11 @@ define i32 @fcmps_ueq(float %a, float %b) nounwind strictfp {
}
define i32 @fcmps_ugt(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fcmps_ugt:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: fle.s a0, fa0, fa1
-; RV32IF-NEXT: xori a0, a0, 1
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: fcmps_ugt:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: fle.s a0, fa0, fa1
-; RV64IF-NEXT: xori a0, a0, 1
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: fcmps_ugt:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: fle.s a0, fa0, fa1
+; CHECKIF-NEXT: xori a0, a0, 1
+; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fcmps_ugt:
; RV32I: # %bb.0:
@@ -1054,17 +878,11 @@ define i32 @fcmps_ugt(float %a, float %b) nounwind strictfp {
}
define i32 @fcmps_uge(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fcmps_uge:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: flt.s a0, fa0, fa1
-; RV32IF-NEXT: xori a0, a0, 1
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: fcmps_uge:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: flt.s a0, fa0, fa1
-; RV64IF-NEXT: xori a0, a0, 1
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: fcmps_uge:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: flt.s a0, fa0, fa1
+; CHECKIF-NEXT: xori a0, a0, 1
+; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fcmps_uge:
; RV32I: # %bb.0:
@@ -1093,17 +911,11 @@ define i32 @fcmps_uge(float %a, float %b) nounwind strictfp {
}
define i32 @fcmps_ult(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fcmps_ult:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: fle.s a0, fa1, fa0
-; RV32IF-NEXT: xori a0, a0, 1
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: fcmps_ult:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: fle.s a0, fa1, fa0
-; RV64IF-NEXT: xori a0, a0, 1
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: fcmps_ult:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: fle.s a0, fa1, fa0
+; CHECKIF-NEXT: xori a0, a0, 1
+; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fcmps_ult:
; RV32I: # %bb.0:
@@ -1130,17 +942,11 @@ define i32 @fcmps_ult(float %a, float %b) nounwind strictfp {
}
define i32 @fcmps_ule(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fcmps_ule:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: flt.s a0, fa1, fa0
-; RV32IF-NEXT: xori a0, a0, 1
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: fcmps_ule:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: flt.s a0, fa1, fa0
-; RV64IF-NEXT: xori a0, a0, 1
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: fcmps_ule:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: flt.s a0, fa1, fa0
+; CHECKIF-NEXT: xori a0, a0, 1
+; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fcmps_ule:
; RV32I: # %bb.0:
@@ -1167,21 +973,13 @@ define i32 @fcmps_ule(float %a, float %b) nounwind strictfp {
}
define i32 @fcmps_une(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fcmps_une:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: fle.s a0, fa1, fa0
-; RV32IF-NEXT: fle.s a1, fa0, fa1
-; RV32IF-NEXT: and a0, a1, a0
-; RV32IF-NEXT: xori a0, a0, 1
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: fcmps_une:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: fle.s a0, fa1, fa0
-; RV64IF-NEXT: fle.s a1, fa0, fa1
-; RV64IF-NEXT: and a0, a1, a0
-; RV64IF-NEXT: xori a0, a0, 1
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: fcmps_une:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: fle.s a0, fa1, fa0
+; CHECKIF-NEXT: fle.s a1, fa0, fa1
+; CHECKIF-NEXT: and a0, a1, a0
+; CHECKIF-NEXT: xori a0, a0, 1
+; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fcmps_une:
; RV32I: # %bb.0:
@@ -1208,21 +1006,13 @@ define i32 @fcmps_une(float %a, float %b) nounwind strictfp {
}
define i32 @fcmps_uno(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fcmps_uno:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: fle.s a0, fa1, fa1
-; RV32IF-NEXT: fle.s a1, fa0, fa0
-; RV32IF-NEXT: and a0, a1, a0
-; RV32IF-NEXT: xori a0, a0, 1
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: fcmps_uno:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: fle.s a0, fa1, fa1
-; RV64IF-NEXT: fle.s a1, fa0, fa0
-; RV64IF-NEXT: and a0, a1, a0
-; RV64IF-NEXT: xori a0, a0, 1
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: fcmps_uno:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: fle.s a0, fa1, fa1
+; CHECKIF-NEXT: fle.s a1, fa0, fa0
+; CHECKIF-NEXT: and a0, a1, a0
+; CHECKIF-NEXT: xori a0, a0, 1
+; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fcmps_uno:
; RV32I: # %bb.0:
diff --git a/llvm/test/CodeGen/RISCV/float-fcmp.ll b/llvm/test/CodeGen/RISCV/float-fcmp.ll
index 663e688d333f..083262d6372c 100644
--- a/llvm/test/CodeGen/RISCV/float-fcmp.ll
+++ b/llvm/test/CodeGen/RISCV/float-fcmp.ll
@@ -1,23 +1,18 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
-; RUN: -target-abi=ilp32f | FileCheck -check-prefix=RV32IF %s
+; RUN: -target-abi=ilp32f | FileCheck -check-prefix=CHECKIF %s
; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
-; RUN: -target-abi=lp64f | FileCheck -check-prefix=RV64IF %s
+; RUN: -target-abi=lp64f | FileCheck -check-prefix=CHECKIF %s
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32I %s
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64I %s
define i32 @fcmp_false(float %a, float %b) nounwind {
-; RV32IF-LABEL: fcmp_false:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: li a0, 0
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: fcmp_false:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: li a0, 0
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: fcmp_false:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: li a0, 0
+; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fcmp_false:
; RV32I: # %bb.0:
@@ -34,15 +29,10 @@ define i32 @fcmp_false(float %a, float %b) nounwind {
}
define i32 @fcmp_oeq(float %a, float %b) nounwind {
-; RV32IF-LABEL: fcmp_oeq:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: feq.s a0, fa0, fa1
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: fcmp_oeq:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: feq.s a0, fa0, fa1
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: fcmp_oeq:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: feq.s a0, fa0, fa1
+; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fcmp_oeq:
; RV32I: # %bb.0:
@@ -69,15 +59,10 @@ define i32 @fcmp_oeq(float %a, float %b) nounwind {
}
define i32 @fcmp_ogt(float %a, float %b) nounwind {
-; RV32IF-LABEL: fcmp_ogt:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: flt.s a0, fa1, fa0
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: fcmp_ogt:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: flt.s a0, fa1, fa0
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: fcmp_ogt:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: flt.s a0, fa1, fa0
+; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fcmp_ogt:
; RV32I: # %bb.0:
@@ -104,15 +89,10 @@ define i32 @fcmp_ogt(float %a, float %b) nounwind {
}
define i32 @fcmp_oge(float %a, float %b) nounwind {
-; RV32IF-LABEL: fcmp_oge:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: fle.s a0, fa1, fa0
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: fcmp_oge:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: fle.s a0, fa1, fa0
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: fcmp_oge:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: fle.s a0, fa1, fa0
+; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fcmp_oge:
; RV32I: # %bb.0:
@@ -141,15 +121,10 @@ define i32 @fcmp_oge(float %a, float %b) nounwind {
}
define i32 @fcmp_olt(float %a, float %b) nounwind {
-; RV32IF-LABEL: fcmp_olt:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: flt.s a0, fa0, fa1
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: fcmp_olt:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: flt.s a0, fa0, fa1
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: fcmp_olt:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: flt.s a0, fa0, fa1
+; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fcmp_olt:
; RV32I: # %bb.0:
@@ -176,15 +151,10 @@ define i32 @fcmp_olt(float %a, float %b) nounwind {
}
define i32 @fcmp_ole(float %a, float %b) nounwind {
-; RV32IF-LABEL: fcmp_ole:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: fle.s a0, fa0, fa1
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: fcmp_ole:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: fle.s a0, fa0, fa1
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: fcmp_ole:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: fle.s a0, fa0, fa1
+; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fcmp_ole:
; RV32I: # %bb.0:
@@ -211,19 +181,12 @@ define i32 @fcmp_ole(float %a, float %b) nounwind {
}
define i32 @fcmp_one(float %a, float %b) nounwind {
-; RV32IF-LABEL: fcmp_one:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: flt.s a0, fa0, fa1
-; RV32IF-NEXT: flt.s a1, fa1, fa0
-; RV32IF-NEXT: or a0, a1, a0
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: fcmp_one:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: flt.s a0, fa0, fa1
-; RV64IF-NEXT: flt.s a1, fa1, fa0
-; RV64IF-NEXT: or a0, a1, a0
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: fcmp_one:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: flt.s a0, fa0, fa1
+; CHECKIF-NEXT: flt.s a1, fa1, fa0
+; CHECKIF-NEXT: or a0, a1, a0
+; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fcmp_one:
; RV32I: # %bb.0:
@@ -276,19 +239,12 @@ define i32 @fcmp_one(float %a, float %b) nounwind {
}
define i32 @fcmp_ord(float %a, float %b) nounwind {
-; RV32IF-LABEL: fcmp_ord:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: feq.s a0, fa1, fa1
-; RV32IF-NEXT: feq.s a1, fa0, fa0
-; RV32IF-NEXT: and a0, a1, a0
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: fcmp_ord:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: feq.s a0, fa1, fa1
-; RV64IF-NEXT: feq.s a1, fa0, fa0
-; RV64IF-NEXT: and a0, a1, a0
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: fcmp_ord:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: feq.s a0, fa1, fa1
+; CHECKIF-NEXT: feq.s a1, fa0, fa0
+; CHECKIF-NEXT: and a0, a1, a0
+; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fcmp_ord:
; RV32I: # %bb.0:
@@ -315,21 +271,13 @@ define i32 @fcmp_ord(float %a, float %b) nounwind {
}
define i32 @fcmp_ueq(float %a, float %b) nounwind {
-; RV32IF-LABEL: fcmp_ueq:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: flt.s a0, fa0, fa1
-; RV32IF-NEXT: flt.s a1, fa1, fa0
-; RV32IF-NEXT: or a0, a1, a0
-; RV32IF-NEXT: xori a0, a0, 1
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: fcmp_ueq:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: flt.s a0, fa0, fa1
-; RV64IF-NEXT: flt.s a1, fa1, fa0
-; RV64IF-NEXT: or a0, a1, a0
-; RV64IF-NEXT: xori a0, a0, 1
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: fcmp_ueq:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: flt.s a0, fa0, fa1
+; CHECKIF-NEXT: flt.s a1, fa1, fa0
+; CHECKIF-NEXT: or a0, a1, a0
+; CHECKIF-NEXT: xori a0, a0, 1
+; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fcmp_ueq:
; RV32I: # %bb.0:
@@ -382,17 +330,11 @@ define i32 @fcmp_ueq(float %a, float %b) nounwind {
}
define i32 @fcmp_ugt(float %a, float %b) nounwind {
-; RV32IF-LABEL: fcmp_ugt:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: fle.s a0, fa0, fa1
-; RV32IF-NEXT: xori a0, a0, 1
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: fcmp_ugt:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: fle.s a0, fa0, fa1
-; RV64IF-NEXT: xori a0, a0, 1
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: fcmp_ugt:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: fle.s a0, fa0, fa1
+; CHECKIF-NEXT: xori a0, a0, 1
+; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fcmp_ugt:
; RV32I: # %bb.0:
@@ -419,17 +361,11 @@ define i32 @fcmp_ugt(float %a, float %b) nounwind {
}
define i32 @fcmp_uge(float %a, float %b) nounwind {
-; RV32IF-LABEL: fcmp_uge:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: flt.s a0, fa0, fa1
-; RV32IF-NEXT: xori a0, a0, 1
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: fcmp_uge:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: flt.s a0, fa0, fa1
-; RV64IF-NEXT: xori a0, a0, 1
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: fcmp_uge:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: flt.s a0, fa0, fa1
+; CHECKIF-NEXT: xori a0, a0, 1
+; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fcmp_uge:
; RV32I: # %bb.0:
@@ -458,17 +394,11 @@ define i32 @fcmp_uge(float %a, float %b) nounwind {
}
define i32 @fcmp_ult(float %a, float %b) nounwind {
-; RV32IF-LABEL: fcmp_ult:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: fle.s a0, fa1, fa0
-; RV32IF-NEXT: xori a0, a0, 1
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: fcmp_ult:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: fle.s a0, fa1, fa0
-; RV64IF-NEXT: xori a0, a0, 1
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: fcmp_ult:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: fle.s a0, fa1, fa0
+; CHECKIF-NEXT: xori a0, a0, 1
+; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fcmp_ult:
; RV32I: # %bb.0:
@@ -495,17 +425,11 @@ define i32 @fcmp_ult(float %a, float %b) nounwind {
}
define i32 @fcmp_ule(float %a, float %b) nounwind {
-; RV32IF-LABEL: fcmp_ule:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: flt.s a0, fa1, fa0
-; RV32IF-NEXT: xori a0, a0, 1
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: fcmp_ule:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: flt.s a0, fa1, fa0
-; RV64IF-NEXT: xori a0, a0, 1
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: fcmp_ule:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: flt.s a0, fa1, fa0
+; CHECKIF-NEXT: xori a0, a0, 1
+; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fcmp_ule:
; RV32I: # %bb.0:
@@ -532,17 +456,11 @@ define i32 @fcmp_ule(float %a, float %b) nounwind {
}
define i32 @fcmp_une(float %a, float %b) nounwind {
-; RV32IF-LABEL: fcmp_une:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: feq.s a0, fa0, fa1
-; RV32IF-NEXT: xori a0, a0, 1
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: fcmp_une:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: feq.s a0, fa0, fa1
-; RV64IF-NEXT: xori a0, a0, 1
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: fcmp_une:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: feq.s a0, fa0, fa1
+; CHECKIF-NEXT: xori a0, a0, 1
+; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fcmp_une:
; RV32I: # %bb.0:
@@ -569,21 +487,13 @@ define i32 @fcmp_une(float %a, float %b) nounwind {
}
define i32 @fcmp_uno(float %a, float %b) nounwind {
-; RV32IF-LABEL: fcmp_uno:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: feq.s a0, fa1, fa1
-; RV32IF-NEXT: feq.s a1, fa0, fa0
-; RV32IF-NEXT: and a0, a1, a0
-; RV32IF-NEXT: xori a0, a0, 1
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: fcmp_uno:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: feq.s a0, fa1, fa1
-; RV64IF-NEXT: feq.s a1, fa0, fa0
-; RV64IF-NEXT: and a0, a1, a0
-; RV64IF-NEXT: xori a0, a0, 1
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: fcmp_uno:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: feq.s a0, fa1, fa1
+; CHECKIF-NEXT: feq.s a1, fa0, fa0
+; CHECKIF-NEXT: and a0, a1, a0
+; CHECKIF-NEXT: xori a0, a0, 1
+; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fcmp_uno:
; RV32I: # %bb.0:
@@ -610,15 +520,10 @@ define i32 @fcmp_uno(float %a, float %b) nounwind {
}
define i32 @fcmp_true(float %a, float %b) nounwind {
-; RV32IF-LABEL: fcmp_true:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: li a0, 1
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: fcmp_true:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: li a0, 1
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: fcmp_true:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: li a0, 1
+; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fcmp_true:
; RV32I: # %bb.0:
diff --git a/llvm/test/CodeGen/RISCV/float-imm.ll b/llvm/test/CodeGen/RISCV/float-imm.ll
index 912ec5748393..b4735e8ae81f 100644
--- a/llvm/test/CodeGen/RISCV/float-imm.ll
+++ b/llvm/test/CodeGen/RISCV/float-imm.ll
@@ -1,39 +1,26 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
-; RUN: -target-abi=ilp32f | FileCheck -check-prefix=RV32IF %s
+; RUN: -target-abi=ilp32f | FileCheck %s
; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
-; RUN: -target-abi=lp64f | FileCheck -check-prefix=RV64IF %s
+; RUN: -target-abi=lp64f | FileCheck %s
; TODO: constant pool shouldn't be necessary for RV64IF.
define float @float_imm() nounwind {
-; RV32IF-LABEL: float_imm:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: lui a0, %hi(.LCPI0_0)
-; RV32IF-NEXT: flw fa0, %lo(.LCPI0_0)(a0)
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: float_imm:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: lui a0, %hi(.LCPI0_0)
-; RV64IF-NEXT: flw fa0, %lo(.LCPI0_0)(a0)
-; RV64IF-NEXT: ret
+; CHECK-LABEL: float_imm:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a0, %hi(.LCPI0_0)
+; CHECK-NEXT: flw fa0, %lo(.LCPI0_0)(a0)
+; CHECK-NEXT: ret
ret float 3.14159274101257324218750
}
define float @float_imm_op(float %a) nounwind {
-; RV32IF-LABEL: float_imm_op:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: lui a0, %hi(.LCPI1_0)
-; RV32IF-NEXT: flw ft0, %lo(.LCPI1_0)(a0)
-; RV32IF-NEXT: fadd.s fa0, fa0, ft0
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: float_imm_op:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: lui a0, %hi(.LCPI1_0)
-; RV64IF-NEXT: flw ft0, %lo(.LCPI1_0)(a0)
-; RV64IF-NEXT: fadd.s fa0, fa0, ft0
-; RV64IF-NEXT: ret
+; CHECK-LABEL: float_imm_op:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a0, %hi(.LCPI1_0)
+; CHECK-NEXT: flw ft0, %lo(.LCPI1_0)(a0)
+; CHECK-NEXT: fadd.s fa0, fa0, ft0
+; CHECK-NEXT: ret
%1 = fadd float %a, 1.0
ret float %1
}
diff --git a/llvm/test/CodeGen/RISCV/float-intrinsics-strict.ll b/llvm/test/CodeGen/RISCV/float-intrinsics-strict.ll
index eca9a931f297..736aa8c10955 100644
--- a/llvm/test/CodeGen/RISCV/float-intrinsics-strict.ll
+++ b/llvm/test/CodeGen/RISCV/float-intrinsics-strict.ll
@@ -1,10 +1,10 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+f \
; RUN: -verify-machineinstrs -disable-strictnode-mutation -target-abi=ilp32f \
-; RUN: | FileCheck -check-prefix=RV32IF %s
+; RUN: | FileCheck -check-prefixes=CHECKIF,RV32IF %s
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+f \
; RUN: -verify-machineinstrs -disable-strictnode-mutation -target-abi=lp64f \
-; RUN: | FileCheck -check-prefix=RV64IF %s
+; RUN: | FileCheck -check-prefixes=CHECKIF,RV64IF %s
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 \
; RUN: -verify-machineinstrs -disable-strictnode-mutation \
; RUN: | FileCheck -check-prefix=RV32I %s
@@ -15,15 +15,10 @@
declare float @llvm.experimental.constrained.sqrt.f32(float, metadata, metadata)
define float @sqrt_f32(float %a) nounwind strictfp {
-; RV32IF-LABEL: sqrt_f32:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: fsqrt.s fa0, fa0
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: sqrt_f32:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: fsqrt.s fa0, fa0
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: sqrt_f32:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: fsqrt.s fa0, fa0
+; CHECKIF-NEXT: ret
;
; RV32I-LABEL: sqrt_f32:
; RV32I: # %bb.0:
@@ -512,15 +507,10 @@ define float @log2_f32(float %a) nounwind strictfp {
declare float @llvm.experimental.constrained.fma.f32(float, float, float, metadata, metadata)
define float @fma_f32(float %a, float %b, float %c) nounwind strictfp {
-; RV32IF-LABEL: fma_f32:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: fmadd.s fa0, fa0, fa1, fa2
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: fma_f32:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: fmadd.s fa0, fa0, fa1, fa2
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: fma_f32:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: fmadd.s fa0, fa0, fa1, fa2
+; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fma_f32:
; RV32I: # %bb.0:
@@ -546,15 +536,10 @@ define float @fma_f32(float %a, float %b, float %c) nounwind strictfp {
declare float @llvm.experimental.constrained.fmuladd.f32(float, float, float, metadata, metadata)
define float @fmuladd_f32(float %a, float %b, float %c) nounwind strictfp {
-; RV32IF-LABEL: fmuladd_f32:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: fmadd.s fa0, fa0, fa1, fa2
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: fmuladd_f32:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: fmadd.s fa0, fa0, fa1, fa2
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: fmuladd_f32:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: fmadd.s fa0, fa0, fa1, fa2
+; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fmuladd_f32:
; RV32I: # %bb.0:
diff --git a/llvm/test/CodeGen/RISCV/float-isnan.ll b/llvm/test/CodeGen/RISCV/float-isnan.ll
index c357f4f9a0e1..d3857cdc609e 100644
--- a/llvm/test/CodeGen/RISCV/float-isnan.ll
+++ b/llvm/test/CodeGen/RISCV/float-isnan.ll
@@ -1,35 +1,24 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi ilp32f -verify-machineinstrs \
-; RUN: < %s | FileCheck -check-prefix=RV32IF %s
+; RUN: < %s | FileCheck %s
; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi lp64f -verify-machineinstrs \
-; RUN: < %s | FileCheck -check-prefix=RV64IF %s
+; RUN: < %s | FileCheck %s
define zeroext i1 @float_is_nan(float %a) nounwind {
-; RV32IF-LABEL: float_is_nan:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: feq.s a0, fa0, fa0
-; RV32IF-NEXT: xori a0, a0, 1
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: float_is_nan:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: feq.s a0, fa0, fa0
-; RV64IF-NEXT: xori a0, a0, 1
-; RV64IF-NEXT: ret
+; CHECK-LABEL: float_is_nan:
+; CHECK: # %bb.0:
+; CHECK-NEXT: feq.s a0, fa0, fa0
+; CHECK-NEXT: xori a0, a0, 1
+; CHECK-NEXT: ret
%1 = fcmp uno float %a, 0.000000e+00
ret i1 %1
}
define zeroext i1 @float_not_nan(float %a) nounwind {
-; RV32IF-LABEL: float_not_nan:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: feq.s a0, fa0, fa0
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: float_not_nan:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: feq.s a0, fa0, fa0
-; RV64IF-NEXT: ret
+; CHECK-LABEL: float_not_nan:
+; CHECK: # %bb.0:
+; CHECK-NEXT: feq.s a0, fa0, fa0
+; CHECK-NEXT: ret
%1 = fcmp ord float %a, 0.000000e+00
ret i1 %1
}
diff --git a/llvm/test/CodeGen/RISCV/float-mem.ll b/llvm/test/CodeGen/RISCV/float-mem.ll
index f90272c816af..c8a5f68c357c 100644
--- a/llvm/test/CodeGen/RISCV/float-mem.ll
+++ b/llvm/test/CodeGen/RISCV/float-mem.ll
@@ -1,23 +1,16 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
-; RUN: -target-abi=ilp32f | FileCheck -check-prefix=RV32IF %s
+; RUN: -target-abi=ilp32f | FileCheck -check-prefixes=CHECKIF,RV32IF %s
; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
-; RUN: -target-abi=lp64f | FileCheck -check-prefix=RV64IF %s
+; RUN: -target-abi=lp64f | FileCheck -check-prefixes=CHECKIF,RV64IF %s
define dso_local float @flw(float *%a) nounwind {
-; RV32IF-LABEL: flw:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: flw ft0, 0(a0)
-; RV32IF-NEXT: flw ft1, 12(a0)
-; RV32IF-NEXT: fadd.s fa0, ft0, ft1
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: flw:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: flw ft0, 0(a0)
-; RV64IF-NEXT: flw ft1, 12(a0)
-; RV64IF-NEXT: fadd.s fa0, ft0, ft1
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: flw:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: flw ft0, 0(a0)
+; CHECKIF-NEXT: flw ft1, 12(a0)
+; CHECKIF-NEXT: fadd.s fa0, ft0, ft1
+; CHECKIF-NEXT: ret
%1 = load float, float* %a
%2 = getelementptr float, float* %a, i32 3
%3 = load float, float* %2
@@ -30,19 +23,12 @@ define dso_local float @flw(float *%a) nounwind {
define dso_local void @fsw(float *%a, float %b, float %c) nounwind {
; Use %b and %c in an FP op to ensure floating point registers are used, even
; for the soft float ABI
-; RV32IF-LABEL: fsw:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: fadd.s ft0, fa0, fa1
-; RV32IF-NEXT: fsw ft0, 0(a0)
-; RV32IF-NEXT: fsw ft0, 32(a0)
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: fsw:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: fadd.s ft0, fa0, fa1
-; RV64IF-NEXT: fsw ft0, 0(a0)
-; RV64IF-NEXT: fsw ft0, 32(a0)
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: fsw:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: fadd.s ft0, fa0, fa1
+; CHECKIF-NEXT: fsw ft0, 0(a0)
+; CHECKIF-NEXT: fsw ft0, 32(a0)
+; CHECKIF-NEXT: ret
%1 = fadd float %b, %c
store float %1, float* %a
%2 = getelementptr float, float* %a, i32 8
@@ -56,27 +42,16 @@ define dso_local void @fsw(float *%a, float %b, float %c) nounwind {
define dso_local float @flw_fsw_global(float %a, float %b) nounwind {
; Use %a and %b in an FP op to ensure floating point registers are used, even
; for the soft float ABI
-; RV32IF-LABEL: flw_fsw_global:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: fadd.s fa0, fa0, fa1
-; RV32IF-NEXT: lui a0, %hi(G)
-; RV32IF-NEXT: flw ft0, %lo(G)(a0)
-; RV32IF-NEXT: addi a1, a0, %lo(G)
-; RV32IF-NEXT: fsw fa0, %lo(G)(a0)
-; RV32IF-NEXT: flw ft0, 36(a1)
-; RV32IF-NEXT: fsw fa0, 36(a1)
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: flw_fsw_global:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: fadd.s fa0, fa0, fa1
-; RV64IF-NEXT: lui a0, %hi(G)
-; RV64IF-NEXT: flw ft0, %lo(G)(a0)
-; RV64IF-NEXT: addi a1, a0, %lo(G)
-; RV64IF-NEXT: fsw fa0, %lo(G)(a0)
-; RV64IF-NEXT: flw ft0, 36(a1)
-; RV64IF-NEXT: fsw fa0, 36(a1)
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: flw_fsw_global:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: fadd.s fa0, fa0, fa1
+; CHECKIF-NEXT: lui a0, %hi(G)
+; CHECKIF-NEXT: flw ft0, %lo(G)(a0)
+; CHECKIF-NEXT: addi a1, a0, %lo(G)
+; CHECKIF-NEXT: fsw fa0, %lo(G)(a0)
+; CHECKIF-NEXT: flw ft0, 36(a1)
+; CHECKIF-NEXT: fsw fa0, 36(a1)
+; CHECKIF-NEXT: ret
%1 = fadd float %a, %b
%2 = load volatile float, float* @G
store float %1, float* @G
diff --git a/llvm/test/CodeGen/RISCV/float-round-conv-sat.ll b/llvm/test/CodeGen/RISCV/float-round-conv-sat.ll
index 834b7f72dd66..ff29bc444818 100644
--- a/llvm/test/CodeGen/RISCV/float-round-conv-sat.ll
+++ b/llvm/test/CodeGen/RISCV/float-round-conv-sat.ll
@@ -1,27 +1,18 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
-; RUN: -target-abi=ilp32f | FileCheck -check-prefix=RV32IF %s
+; RUN: -target-abi=ilp32f | FileCheck -check-prefixes=CHECKIF,RV32IF %s
; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
-; RUN: -target-abi=lp64f | FileCheck -check-prefix=RV64IF %s
+; RUN: -target-abi=lp64f | FileCheck -check-prefixes=CHECKIF,RV64IF %s
define signext i32 @test_floor_si32(float %x) {
-; RV32IF-LABEL: test_floor_si32:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: feq.s a0, fa0, fa0
-; RV32IF-NEXT: beqz a0, .LBB0_2
-; RV32IF-NEXT: # %bb.1:
-; RV32IF-NEXT: fcvt.w.s a0, fa0, rdn
-; RV32IF-NEXT: .LBB0_2:
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: test_floor_si32:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: feq.s a0, fa0, fa0
-; RV64IF-NEXT: beqz a0, .LBB0_2
-; RV64IF-NEXT: # %bb.1:
-; RV64IF-NEXT: fcvt.w.s a0, fa0, rdn
-; RV64IF-NEXT: .LBB0_2:
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: test_floor_si32:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: feq.s a0, fa0, fa0
+; CHECKIF-NEXT: beqz a0, .LBB0_2
+; CHECKIF-NEXT: # %bb.1:
+; CHECKIF-NEXT: fcvt.w.s a0, fa0, rdn
+; CHECKIF-NEXT: .LBB0_2:
+; CHECKIF-NEXT: ret
%a = call float @llvm.floor.f32(float %x)
%b = call i32 @llvm.fptosi.sat.i32.f32(float %a)
ret i32 %b
@@ -98,23 +89,14 @@ define i64 @test_floor_si64(float %x) nounwind {
}
define signext i32 @test_floor_ui32(float %x) {
-; RV32IF-LABEL: test_floor_ui32:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: feq.s a0, fa0, fa0
-; RV32IF-NEXT: beqz a0, .LBB2_2
-; RV32IF-NEXT: # %bb.1:
-; RV32IF-NEXT: fcvt.wu.s a0, fa0, rdn
-; RV32IF-NEXT: .LBB2_2:
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: test_floor_ui32:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: feq.s a0, fa0, fa0
-; RV64IF-NEXT: beqz a0, .LBB2_2
-; RV64IF-NEXT: # %bb.1:
-; RV64IF-NEXT: fcvt.wu.s a0, fa0, rdn
-; RV64IF-NEXT: .LBB2_2:
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: test_floor_ui32:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: feq.s a0, fa0, fa0
+; CHECKIF-NEXT: beqz a0, .LBB2_2
+; CHECKIF-NEXT: # %bb.1:
+; CHECKIF-NEXT: fcvt.wu.s a0, fa0, rdn
+; CHECKIF-NEXT: .LBB2_2:
+; CHECKIF-NEXT: ret
%a = call float @llvm.floor.f32(float %x)
%b = call i32 @llvm.fptoui.sat.i32.f32(float %a)
ret i32 %b
@@ -178,23 +160,14 @@ define i64 @test_floor_ui64(float %x) nounwind {
}
define signext i32 @test_ceil_si32(float %x) {
-; RV32IF-LABEL: test_ceil_si32:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: feq.s a0, fa0, fa0
-; RV32IF-NEXT: beqz a0, .LBB4_2
-; RV32IF-NEXT: # %bb.1:
-; RV32IF-NEXT: fcvt.w.s a0, fa0, rup
-; RV32IF-NEXT: .LBB4_2:
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: test_ceil_si32:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: feq.s a0, fa0, fa0
-; RV64IF-NEXT: beqz a0, .LBB4_2
-; RV64IF-NEXT: # %bb.1:
-; RV64IF-NEXT: fcvt.w.s a0, fa0, rup
-; RV64IF-NEXT: .LBB4_2:
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: test_ceil_si32:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: feq.s a0, fa0, fa0
+; CHECKIF-NEXT: beqz a0, .LBB4_2
+; CHECKIF-NEXT: # %bb.1:
+; CHECKIF-NEXT: fcvt.w.s a0, fa0, rup
+; CHECKIF-NEXT: .LBB4_2:
+; CHECKIF-NEXT: ret
%a = call float @llvm.ceil.f32(float %x)
%b = call i32 @llvm.fptosi.sat.i32.f32(float %a)
ret i32 %b
@@ -271,23 +244,14 @@ define i64 @test_ceil_si64(float %x) nounwind {
}
define signext i32 @test_ceil_ui32(float %x) {
-; RV32IF-LABEL: test_ceil_ui32:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: feq.s a0, fa0, fa0
-; RV32IF-NEXT: beqz a0, .LBB6_2
-; RV32IF-NEXT: # %bb.1:
-; RV32IF-NEXT: fcvt.wu.s a0, fa0, rup
-; RV32IF-NEXT: .LBB6_2:
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: test_ceil_ui32:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: feq.s a0, fa0, fa0
-; RV64IF-NEXT: beqz a0, .LBB6_2
-; RV64IF-NEXT: # %bb.1:
-; RV64IF-NEXT: fcvt.wu.s a0, fa0, rup
-; RV64IF-NEXT: .LBB6_2:
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: test_ceil_ui32:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: feq.s a0, fa0, fa0
+; CHECKIF-NEXT: beqz a0, .LBB6_2
+; CHECKIF-NEXT: # %bb.1:
+; CHECKIF-NEXT: fcvt.wu.s a0, fa0, rup
+; CHECKIF-NEXT: .LBB6_2:
+; CHECKIF-NEXT: ret
%a = call float @llvm.ceil.f32(float %x)
%b = call i32 @llvm.fptoui.sat.i32.f32(float %a)
ret i32 %b
@@ -351,23 +315,14 @@ define i64 @test_ceil_ui64(float %x) nounwind {
}
define signext i32 @test_trunc_si32(float %x) {
-; RV32IF-LABEL: test_trunc_si32:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: feq.s a0, fa0, fa0
-; RV32IF-NEXT: beqz a0, .LBB8_2
-; RV32IF-NEXT: # %bb.1:
-; RV32IF-NEXT: fcvt.w.s a0, fa0, rtz
-; RV32IF-NEXT: .LBB8_2:
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: test_trunc_si32:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: feq.s a0, fa0, fa0
-; RV64IF-NEXT: beqz a0, .LBB8_2
-; RV64IF-NEXT: # %bb.1:
-; RV64IF-NEXT: fcvt.w.s a0, fa0, rtz
-; RV64IF-NEXT: .LBB8_2:
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: test_trunc_si32:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: feq.s a0, fa0, fa0
+; CHECKIF-NEXT: beqz a0, .LBB8_2
+; CHECKIF-NEXT: # %bb.1:
+; CHECKIF-NEXT: fcvt.w.s a0, fa0, rtz
+; CHECKIF-NEXT: .LBB8_2:
+; CHECKIF-NEXT: ret
%a = call float @llvm.trunc.f32(float %x)
%b = call i32 @llvm.fptosi.sat.i32.f32(float %a)
ret i32 %b
@@ -444,23 +399,14 @@ define i64 @test_trunc_si64(float %x) nounwind {
}
define signext i32 @test_trunc_ui32(float %x) {
-; RV32IF-LABEL: test_trunc_ui32:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: feq.s a0, fa0, fa0
-; RV32IF-NEXT: beqz a0, .LBB10_2
-; RV32IF-NEXT: # %bb.1:
-; RV32IF-NEXT: fcvt.wu.s a0, fa0, rtz
-; RV32IF-NEXT: .LBB10_2:
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: test_trunc_ui32:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: feq.s a0, fa0, fa0
-; RV64IF-NEXT: beqz a0, .LBB10_2
-; RV64IF-NEXT: # %bb.1:
-; RV64IF-NEXT: fcvt.wu.s a0, fa0, rtz
-; RV64IF-NEXT: .LBB10_2:
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: test_trunc_ui32:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: feq.s a0, fa0, fa0
+; CHECKIF-NEXT: beqz a0, .LBB10_2
+; CHECKIF-NEXT: # %bb.1:
+; CHECKIF-NEXT: fcvt.wu.s a0, fa0, rtz
+; CHECKIF-NEXT: .LBB10_2:
+; CHECKIF-NEXT: ret
%a = call float @llvm.trunc.f32(float %x)
%b = call i32 @llvm.fptoui.sat.i32.f32(float %a)
ret i32 %b
@@ -524,23 +470,14 @@ define i64 @test_trunc_ui64(float %x) nounwind {
}
define signext i32 @test_round_si32(float %x) {
-; RV32IF-LABEL: test_round_si32:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: feq.s a0, fa0, fa0
-; RV32IF-NEXT: beqz a0, .LBB12_2
-; RV32IF-NEXT: # %bb.1:
-; RV32IF-NEXT: fcvt.w.s a0, fa0, rmm
-; RV32IF-NEXT: .LBB12_2:
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: test_round_si32:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: feq.s a0, fa0, fa0
-; RV64IF-NEXT: beqz a0, .LBB12_2
-; RV64IF-NEXT: # %bb.1:
-; RV64IF-NEXT: fcvt.w.s a0, fa0, rmm
-; RV64IF-NEXT: .LBB12_2:
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: test_round_si32:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: feq.s a0, fa0, fa0
+; CHECKIF-NEXT: beqz a0, .LBB12_2
+; CHECKIF-NEXT: # %bb.1:
+; CHECKIF-NEXT: fcvt.w.s a0, fa0, rmm
+; CHECKIF-NEXT: .LBB12_2:
+; CHECKIF-NEXT: ret
%a = call float @llvm.round.f32(float %x)
%b = call i32 @llvm.fptosi.sat.i32.f32(float %a)
ret i32 %b
@@ -617,23 +554,14 @@ define i64 @test_round_si64(float %x) nounwind {
}
define signext i32 @test_round_ui32(float %x) {
-; RV32IF-LABEL: test_round_ui32:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: feq.s a0, fa0, fa0
-; RV32IF-NEXT: beqz a0, .LBB14_2
-; RV32IF-NEXT: # %bb.1:
-; RV32IF-NEXT: fcvt.wu.s a0, fa0, rmm
-; RV32IF-NEXT: .LBB14_2:
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: test_round_ui32:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: feq.s a0, fa0, fa0
-; RV64IF-NEXT: beqz a0, .LBB14_2
-; RV64IF-NEXT: # %bb.1:
-; RV64IF-NEXT: fcvt.wu.s a0, fa0, rmm
-; RV64IF-NEXT: .LBB14_2:
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: test_round_ui32:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: feq.s a0, fa0, fa0
+; CHECKIF-NEXT: beqz a0, .LBB14_2
+; CHECKIF-NEXT: # %bb.1:
+; CHECKIF-NEXT: fcvt.wu.s a0, fa0, rmm
+; CHECKIF-NEXT: .LBB14_2:
+; CHECKIF-NEXT: ret
%a = call float @llvm.round.f32(float %x)
%b = call i32 @llvm.fptoui.sat.i32.f32(float %a)
ret i32 %b
@@ -697,23 +625,14 @@ define i64 @test_round_ui64(float %x) nounwind {
}
define signext i32 @test_roundeven_si32(float %x) {
-; RV32IF-LABEL: test_roundeven_si32:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: feq.s a0, fa0, fa0
-; RV32IF-NEXT: beqz a0, .LBB16_2
-; RV32IF-NEXT: # %bb.1:
-; RV32IF-NEXT: fcvt.w.s a0, fa0, rne
-; RV32IF-NEXT: .LBB16_2:
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: test_roundeven_si32:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: feq.s a0, fa0, fa0
-; RV64IF-NEXT: beqz a0, .LBB16_2
-; RV64IF-NEXT: # %bb.1:
-; RV64IF-NEXT: fcvt.w.s a0, fa0, rne
-; RV64IF-NEXT: .LBB16_2:
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: test_roundeven_si32:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: feq.s a0, fa0, fa0
+; CHECKIF-NEXT: beqz a0, .LBB16_2
+; CHECKIF-NEXT: # %bb.1:
+; CHECKIF-NEXT: fcvt.w.s a0, fa0, rne
+; CHECKIF-NEXT: .LBB16_2:
+; CHECKIF-NEXT: ret
%a = call float @llvm.roundeven.f32(float %x)
%b = call i32 @llvm.fptosi.sat.i32.f32(float %a)
ret i32 %b
@@ -790,23 +709,14 @@ define i64 @test_roundeven_si64(float %x) nounwind {
}
define signext i32 @test_roundeven_ui32(float %x) {
-; RV32IF-LABEL: test_roundeven_ui32:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: feq.s a0, fa0, fa0
-; RV32IF-NEXT: beqz a0, .LBB18_2
-; RV32IF-NEXT: # %bb.1:
-; RV32IF-NEXT: fcvt.wu.s a0, fa0, rne
-; RV32IF-NEXT: .LBB18_2:
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: test_roundeven_ui32:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: feq.s a0, fa0, fa0
-; RV64IF-NEXT: beqz a0, .LBB18_2
-; RV64IF-NEXT: # %bb.1:
-; RV64IF-NEXT: fcvt.wu.s a0, fa0, rne
-; RV64IF-NEXT: .LBB18_2:
-; RV64IF-NEXT: ret
+; CHECKIF-LABEL: test_roundeven_ui32:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: feq.s a0, fa0, fa0
+; CHECKIF-NEXT: beqz a0, .LBB18_2
+; CHECKIF-NEXT: # %bb.1:
+; CHECKIF-NEXT: fcvt.wu.s a0, fa0, rne
+; CHECKIF-NEXT: .LBB18_2:
+; CHECKIF-NEXT: ret
%a = call float @llvm.roundeven.f32(float %x)
%b = call i32 @llvm.fptoui.sat.i32.f32(float %a)
ret i32 %b
diff --git a/llvm/test/CodeGen/RISCV/float-select-fcmp.ll b/llvm/test/CodeGen/RISCV/float-select-fcmp.ll
index b3c253341198..1188201d91a9 100644
--- a/llvm/test/CodeGen/RISCV/float-select-fcmp.ll
+++ b/llvm/test/CodeGen/RISCV/float-select-fcmp.ll
@@ -1,370 +1,227 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
-; RUN: -target-abi=ilp32f | FileCheck -check-prefix=RV32IF %s
+; RUN: -target-abi=ilp32f | FileCheck %s
; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
-; RUN: -target-abi=lp64f | FileCheck -check-prefix=RV64IF %s
+; RUN: -target-abi=lp64f | FileCheck %s
define float @select_fcmp_false(float %a, float %b) nounwind {
-; RV32IF-LABEL: select_fcmp_false:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: fmv.s fa0, fa1
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: select_fcmp_false:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: fmv.s fa0, fa1
-; RV64IF-NEXT: ret
+; CHECK-LABEL: select_fcmp_false:
+; CHECK: # %bb.0:
+; CHECK-NEXT: fmv.s fa0, fa1
+; CHECK-NEXT: ret
%1 = fcmp false float %a, %b
%2 = select i1 %1, float %a, float %b
ret float %2
}
define float @select_fcmp_oeq(float %a, float %b) nounwind {
-; RV32IF-LABEL: select_fcmp_oeq:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: feq.s a0, fa0, fa1
-; RV32IF-NEXT: bnez a0, .LBB1_2
-; RV32IF-NEXT: # %bb.1:
-; RV32IF-NEXT: fmv.s fa0, fa1
-; RV32IF-NEXT: .LBB1_2:
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: select_fcmp_oeq:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: feq.s a0, fa0, fa1
-; RV64IF-NEXT: bnez a0, .LBB1_2
-; RV64IF-NEXT: # %bb.1:
-; RV64IF-NEXT: fmv.s fa0, fa1
-; RV64IF-NEXT: .LBB1_2:
-; RV64IF-NEXT: ret
+; CHECK-LABEL: select_fcmp_oeq:
+; CHECK: # %bb.0:
+; CHECK-NEXT: feq.s a0, fa0, fa1
+; CHECK-NEXT: bnez a0, .LBB1_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: fmv.s fa0, fa1
+; CHECK-NEXT: .LBB1_2:
+; CHECK-NEXT: ret
%1 = fcmp oeq float %a, %b
%2 = select i1 %1, float %a, float %b
ret float %2
}
define float @select_fcmp_ogt(float %a, float %b) nounwind {
-; RV32IF-LABEL: select_fcmp_ogt:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: flt.s a0, fa1, fa0
-; RV32IF-NEXT: bnez a0, .LBB2_2
-; RV32IF-NEXT: # %bb.1:
-; RV32IF-NEXT: fmv.s fa0, fa1
-; RV32IF-NEXT: .LBB2_2:
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: select_fcmp_ogt:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: flt.s a0, fa1, fa0
-; RV64IF-NEXT: bnez a0, .LBB2_2
-; RV64IF-NEXT: # %bb.1:
-; RV64IF-NEXT: fmv.s fa0, fa1
-; RV64IF-NEXT: .LBB2_2:
-; RV64IF-NEXT: ret
+; CHECK-LABEL: select_fcmp_ogt:
+; CHECK: # %bb.0:
+; CHECK-NEXT: flt.s a0, fa1, fa0
+; CHECK-NEXT: bnez a0, .LBB2_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: fmv.s fa0, fa1
+; CHECK-NEXT: .LBB2_2:
+; CHECK-NEXT: ret
%1 = fcmp ogt float %a, %b
%2 = select i1 %1, float %a, float %b
ret float %2
}
define float @select_fcmp_oge(float %a, float %b) nounwind {
-; RV32IF-LABEL: select_fcmp_oge:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: fle.s a0, fa1, fa0
-; RV32IF-NEXT: bnez a0, .LBB3_2
-; RV32IF-NEXT: # %bb.1:
-; RV32IF-NEXT: fmv.s fa0, fa1
-; RV32IF-NEXT: .LBB3_2:
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: select_fcmp_oge:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: fle.s a0, fa1, fa0
-; RV64IF-NEXT: bnez a0, .LBB3_2
-; RV64IF-NEXT: # %bb.1:
-; RV64IF-NEXT: fmv.s fa0, fa1
-; RV64IF-NEXT: .LBB3_2:
-; RV64IF-NEXT: ret
+; CHECK-LABEL: select_fcmp_oge:
+; CHECK: # %bb.0:
+; CHECK-NEXT: fle.s a0, fa1, fa0
+; CHECK-NEXT: bnez a0, .LBB3_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: fmv.s fa0, fa1
+; CHECK-NEXT: .LBB3_2:
+; CHECK-NEXT: ret
%1 = fcmp oge float %a, %b
%2 = select i1 %1, float %a, float %b
ret float %2
}
define float @select_fcmp_olt(float %a, float %b) nounwind {
-; RV32IF-LABEL: select_fcmp_olt:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: flt.s a0, fa0, fa1
-; RV32IF-NEXT: bnez a0, .LBB4_2
-; RV32IF-NEXT: # %bb.1:
-; RV32IF-NEXT: fmv.s fa0, fa1
-; RV32IF-NEXT: .LBB4_2:
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: select_fcmp_olt:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: flt.s a0, fa0, fa1
-; RV64IF-NEXT: bnez a0, .LBB4_2
-; RV64IF-NEXT: # %bb.1:
-; RV64IF-NEXT: fmv.s fa0, fa1
-; RV64IF-NEXT: .LBB4_2:
-; RV64IF-NEXT: ret
+; CHECK-LABEL: select_fcmp_olt:
+; CHECK: # %bb.0:
+; CHECK-NEXT: flt.s a0, fa0, fa1
+; CHECK-NEXT: bnez a0, .LBB4_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: fmv.s fa0, fa1
+; CHECK-NEXT: .LBB4_2:
+; CHECK-NEXT: ret
%1 = fcmp olt float %a, %b
%2 = select i1 %1, float %a, float %b
ret float %2
}
define float @select_fcmp_ole(float %a, float %b) nounwind {
-; RV32IF-LABEL: select_fcmp_ole:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: fle.s a0, fa0, fa1
-; RV32IF-NEXT: bnez a0, .LBB5_2
-; RV32IF-NEXT: # %bb.1:
-; RV32IF-NEXT: fmv.s fa0, fa1
-; RV32IF-NEXT: .LBB5_2:
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: select_fcmp_ole:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: fle.s a0, fa0, fa1
-; RV64IF-NEXT: bnez a0, .LBB5_2
-; RV64IF-NEXT: # %bb.1:
-; RV64IF-NEXT: fmv.s fa0, fa1
-; RV64IF-NEXT: .LBB5_2:
-; RV64IF-NEXT: ret
+; CHECK-LABEL: select_fcmp_ole:
+; CHECK: # %bb.0:
+; CHECK-NEXT: fle.s a0, fa0, fa1
+; CHECK-NEXT: bnez a0, .LBB5_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: fmv.s fa0, fa1
+; CHECK-NEXT: .LBB5_2:
+; CHECK-NEXT: ret
%1 = fcmp ole float %a, %b
%2 = select i1 %1, float %a, float %b
ret float %2
}
define float @select_fcmp_one(float %a, float %b) nounwind {
-; RV32IF-LABEL: select_fcmp_one:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: flt.s a0, fa0, fa1
-; RV32IF-NEXT: flt.s a1, fa1, fa0
-; RV32IF-NEXT: or a0, a1, a0
-; RV32IF-NEXT: bnez a0, .LBB6_2
-; RV32IF-NEXT: # %bb.1:
-; RV32IF-NEXT: fmv.s fa0, fa1
-; RV32IF-NEXT: .LBB6_2:
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: select_fcmp_one:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: flt.s a0, fa0, fa1
-; RV64IF-NEXT: flt.s a1, fa1, fa0
-; RV64IF-NEXT: or a0, a1, a0
-; RV64IF-NEXT: bnez a0, .LBB6_2
-; RV64IF-NEXT: # %bb.1:
-; RV64IF-NEXT: fmv.s fa0, fa1
-; RV64IF-NEXT: .LBB6_2:
-; RV64IF-NEXT: ret
+; CHECK-LABEL: select_fcmp_one:
+; CHECK: # %bb.0:
+; CHECK-NEXT: flt.s a0, fa0, fa1
+; CHECK-NEXT: flt.s a1, fa1, fa0
+; CHECK-NEXT: or a0, a1, a0
+; CHECK-NEXT: bnez a0, .LBB6_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: fmv.s fa0, fa1
+; CHECK-NEXT: .LBB6_2:
+; CHECK-NEXT: ret
%1 = fcmp one float %a, %b
%2 = select i1 %1, float %a, float %b
ret float %2
}
define float @select_fcmp_ord(float %a, float %b) nounwind {
-; RV32IF-LABEL: select_fcmp_ord:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: feq.s a0, fa1, fa1
-; RV32IF-NEXT: feq.s a1, fa0, fa0
-; RV32IF-NEXT: and a0, a1, a0
-; RV32IF-NEXT: bnez a0, .LBB7_2
-; RV32IF-NEXT: # %bb.1:
-; RV32IF-NEXT: fmv.s fa0, fa1
-; RV32IF-NEXT: .LBB7_2:
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: select_fcmp_ord:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: feq.s a0, fa1, fa1
-; RV64IF-NEXT: feq.s a1, fa0, fa0
-; RV64IF-NEXT: and a0, a1, a0
-; RV64IF-NEXT: bnez a0, .LBB7_2
-; RV64IF-NEXT: # %bb.1:
-; RV64IF-NEXT: fmv.s fa0, fa1
-; RV64IF-NEXT: .LBB7_2:
-; RV64IF-NEXT: ret
+; CHECK-LABEL: select_fcmp_ord:
+; CHECK: # %bb.0:
+; CHECK-NEXT: feq.s a0, fa1, fa1
+; CHECK-NEXT: feq.s a1, fa0, fa0
+; CHECK-NEXT: and a0, a1, a0
+; CHECK-NEXT: bnez a0, .LBB7_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: fmv.s fa0, fa1
+; CHECK-NEXT: .LBB7_2:
+; CHECK-NEXT: ret
%1 = fcmp ord float %a, %b
%2 = select i1 %1, float %a, float %b
ret float %2
}
define float @select_fcmp_ueq(float %a, float %b) nounwind {
-; RV32IF-LABEL: select_fcmp_ueq:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: flt.s a0, fa0, fa1
-; RV32IF-NEXT: flt.s a1, fa1, fa0
-; RV32IF-NEXT: or a0, a1, a0
-; RV32IF-NEXT: beqz a0, .LBB8_2
-; RV32IF-NEXT: # %bb.1:
-; RV32IF-NEXT: fmv.s fa0, fa1
-; RV32IF-NEXT: .LBB8_2:
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: select_fcmp_ueq:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: flt.s a0, fa0, fa1
-; RV64IF-NEXT: flt.s a1, fa1, fa0
-; RV64IF-NEXT: or a0, a1, a0
-; RV64IF-NEXT: beqz a0, .LBB8_2
-; RV64IF-NEXT: # %bb.1:
-; RV64IF-NEXT: fmv.s fa0, fa1
-; RV64IF-NEXT: .LBB8_2:
-; RV64IF-NEXT: ret
+; CHECK-LABEL: select_fcmp_ueq:
+; CHECK: # %bb.0:
+; CHECK-NEXT: flt.s a0, fa0, fa1
+; CHECK-NEXT: flt.s a1, fa1, fa0
+; CHECK-NEXT: or a0, a1, a0
+; CHECK-NEXT: beqz a0, .LBB8_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: fmv.s fa0, fa1
+; CHECK-NEXT: .LBB8_2:
+; CHECK-NEXT: ret
%1 = fcmp ueq float %a, %b
%2 = select i1 %1, float %a, float %b
ret float %2
}
define float @select_fcmp_ugt(float %a, float %b) nounwind {
-; RV32IF-LABEL: select_fcmp_ugt:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: fle.s a0, fa0, fa1
-; RV32IF-NEXT: beqz a0, .LBB9_2
-; RV32IF-NEXT: # %bb.1:
-; RV32IF-NEXT: fmv.s fa0, fa1
-; RV32IF-NEXT: .LBB9_2:
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: select_fcmp_ugt:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: fle.s a0, fa0, fa1
-; RV64IF-NEXT: beqz a0, .LBB9_2
-; RV64IF-NEXT: # %bb.1:
-; RV64IF-NEXT: fmv.s fa0, fa1
-; RV64IF-NEXT: .LBB9_2:
-; RV64IF-NEXT: ret
+; CHECK-LABEL: select_fcmp_ugt:
+; CHECK: # %bb.0:
+; CHECK-NEXT: fle.s a0, fa0, fa1
+; CHECK-NEXT: beqz a0, .LBB9_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: fmv.s fa0, fa1
+; CHECK-NEXT: .LBB9_2:
+; CHECK-NEXT: ret
%1 = fcmp ugt float %a, %b
%2 = select i1 %1, float %a, float %b
ret float %2
}
define float @select_fcmp_uge(float %a, float %b) nounwind {
-; RV32IF-LABEL: select_fcmp_uge:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: flt.s a0, fa0, fa1
-; RV32IF-NEXT: beqz a0, .LBB10_2
-; RV32IF-NEXT: # %bb.1:
-; RV32IF-NEXT: fmv.s fa0, fa1
-; RV32IF-NEXT: .LBB10_2:
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: select_fcmp_uge:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: flt.s a0, fa0, fa1
-; RV64IF-NEXT: beqz a0, .LBB10_2
-; RV64IF-NEXT: # %bb.1:
-; RV64IF-NEXT: fmv.s fa0, fa1
-; RV64IF-NEXT: .LBB10_2:
-; RV64IF-NEXT: ret
+; CHECK-LABEL: select_fcmp_uge:
+; CHECK: # %bb.0:
+; CHECK-NEXT: flt.s a0, fa0, fa1
+; CHECK-NEXT: beqz a0, .LBB10_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: fmv.s fa0, fa1
+; CHECK-NEXT: .LBB10_2:
+; CHECK-NEXT: ret
%1 = fcmp uge float %a, %b
%2 = select i1 %1, float %a, float %b
ret float %2
}
define float @select_fcmp_ult(float %a, float %b) nounwind {
-; RV32IF-LABEL: select_fcmp_ult:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: fle.s a0, fa1, fa0
-; RV32IF-NEXT: beqz a0, .LBB11_2
-; RV32IF-NEXT: # %bb.1:
-; RV32IF-NEXT: fmv.s fa0, fa1
-; RV32IF-NEXT: .LBB11_2:
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: select_fcmp_ult:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: fle.s a0, fa1, fa0
-; RV64IF-NEXT: beqz a0, .LBB11_2
-; RV64IF-NEXT: # %bb.1:
-; RV64IF-NEXT: fmv.s fa0, fa1
-; RV64IF-NEXT: .LBB11_2:
-; RV64IF-NEXT: ret
+; CHECK-LABEL: select_fcmp_ult:
+; CHECK: # %bb.0:
+; CHECK-NEXT: fle.s a0, fa1, fa0
+; CHECK-NEXT: beqz a0, .LBB11_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: fmv.s fa0, fa1
+; CHECK-NEXT: .LBB11_2:
+; CHECK-NEXT: ret
%1 = fcmp ult float %a, %b
%2 = select i1 %1, float %a, float %b
ret float %2
}
define float @select_fcmp_ule(float %a, float %b) nounwind {
-; RV32IF-LABEL: select_fcmp_ule:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: flt.s a0, fa1, fa0
-; RV32IF-NEXT: beqz a0, .LBB12_2
-; RV32IF-NEXT: # %bb.1:
-; RV32IF-NEXT: fmv.s fa0, fa1
-; RV32IF-NEXT: .LBB12_2:
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: select_fcmp_ule:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: flt.s a0, fa1, fa0
-; RV64IF-NEXT: beqz a0, .LBB12_2
-; RV64IF-NEXT: # %bb.1:
-; RV64IF-NEXT: fmv.s fa0, fa1
-; RV64IF-NEXT: .LBB12_2:
-; RV64IF-NEXT: ret
+; CHECK-LABEL: select_fcmp_ule:
+; CHECK: # %bb.0:
+; CHECK-NEXT: flt.s a0, fa1, fa0
+; CHECK-NEXT: beqz a0, .LBB12_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: fmv.s fa0, fa1
+; CHECK-NEXT: .LBB12_2:
+; CHECK-NEXT: ret
%1 = fcmp ule float %a, %b
%2 = select i1 %1, float %a, float %b
ret float %2
}
define float @select_fcmp_une(float %a, float %b) nounwind {
-; RV32IF-LABEL: select_fcmp_une:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: feq.s a0, fa0, fa1
-; RV32IF-NEXT: beqz a0, .LBB13_2
-; RV32IF-NEXT: # %bb.1:
-; RV32IF-NEXT: fmv.s fa0, fa1
-; RV32IF-NEXT: .LBB13_2:
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: select_fcmp_une:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: feq.s a0, fa0, fa1
-; RV64IF-NEXT: beqz a0, .LBB13_2
-; RV64IF-NEXT: # %bb.1:
-; RV64IF-NEXT: fmv.s fa0, fa1
-; RV64IF-NEXT: .LBB13_2:
-; RV64IF-NEXT: ret
+; CHECK-LABEL: select_fcmp_une:
+; CHECK: # %bb.0:
+; CHECK-NEXT: feq.s a0, fa0, fa1
+; CHECK-NEXT: beqz a0, .LBB13_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: fmv.s fa0, fa1
+; CHECK-NEXT: .LBB13_2:
+; CHECK-NEXT: ret
%1 = fcmp une float %a, %b
%2 = select i1 %1, float %a, float %b
ret float %2
}
define float @select_fcmp_uno(float %a, float %b) nounwind {
-; RV32IF-LABEL: select_fcmp_uno:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: feq.s a0, fa1, fa1
-; RV32IF-NEXT: feq.s a1, fa0, fa0
-; RV32IF-NEXT: and a0, a1, a0
-; RV32IF-NEXT: beqz a0, .LBB14_2
-; RV32IF-NEXT: # %bb.1:
-; RV32IF-NEXT: fmv.s fa0, fa1
-; RV32IF-NEXT: .LBB14_2:
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: select_fcmp_uno:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: feq.s a0, fa1, fa1
-; RV64IF-NEXT: feq.s a1, fa0, fa0
-; RV64IF-NEXT: and a0, a1, a0
-; RV64IF-NEXT: beqz a0, .LBB14_2
-; RV64IF-NEXT: # %bb.1:
-; RV64IF-NEXT: fmv.s fa0, fa1
-; RV64IF-NEXT: .LBB14_2:
-; RV64IF-NEXT: ret
+; CHECK-LABEL: select_fcmp_uno:
+; CHECK: # %bb.0:
+; CHECK-NEXT: feq.s a0, fa1, fa1
+; CHECK-NEXT: feq.s a1, fa0, fa0
+; CHECK-NEXT: and a0, a1, a0
+; CHECK-NEXT: beqz a0, .LBB14_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: fmv.s fa0, fa1
+; CHECK-NEXT: .LBB14_2:
+; CHECK-NEXT: ret
%1 = fcmp uno float %a, %b
%2 = select i1 %1, float %a, float %b
ret float %2
}
define float @select_fcmp_true(float %a, float %b) nounwind {
-; RV32IF-LABEL: select_fcmp_true:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: select_fcmp_true:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: ret
+; CHECK-LABEL: select_fcmp_true:
+; CHECK: # %bb.0:
+; CHECK-NEXT: ret
%1 = fcmp true float %a, %b
%2 = select i1 %1, float %a, float %b
ret float %2
@@ -372,23 +229,14 @@ define float @select_fcmp_true(float %a, float %b) nounwind {
; Ensure that ISel succeeds for a select+fcmp that has an i32 result type.
define i32 @i32_select_fcmp_oeq(float %a, float %b, i32 %c, i32 %d) nounwind {
-; RV32IF-LABEL: i32_select_fcmp_oeq:
-; RV32IF: # %bb.0:
-; RV32IF-NEXT: feq.s a2, fa0, fa1
-; RV32IF-NEXT: bnez a2, .LBB16_2
-; RV32IF-NEXT: # %bb.1:
-; RV32IF-NEXT: mv a0, a1
-; RV32IF-NEXT: .LBB16_2:
-; RV32IF-NEXT: ret
-;
-; RV64IF-LABEL: i32_select_fcmp_oeq:
-; RV64IF: # %bb.0:
-; RV64IF-NEXT: feq.s a2, fa0, fa1
-; RV64IF-NEXT: bnez a2, .LBB16_2
-; RV64IF-NEXT: # %bb.1:
-; RV64IF-NEXT: mv a0, a1
-; RV64IF-NEXT: .LBB16_2:
-; RV64IF-NEXT: ret
+; CHECK-LABEL: i32_select_fcmp_oeq:
+; CHECK: # %bb.0:
+; CHECK-NEXT: feq.s a2, fa0, fa1
+; CHECK-NEXT: bnez a2, .LBB16_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: mv a0, a1
+; CHECK-NEXT: .LBB16_2:
+; CHECK-NEXT: ret
%1 = fcmp oeq float %a, %b
%2 = select i1 %1, i32 %c, i32 %d
ret i32 %2
diff --git a/llvm/test/CodeGen/RISCV/half-arith-strict.ll b/llvm/test/CodeGen/RISCV/half-arith-strict.ll
index ff8c1034673c..83b3629d5d61 100644
--- a/llvm/test/CodeGen/RISCV/half-arith-strict.ll
+++ b/llvm/test/CodeGen/RISCV/half-arith-strict.ll
@@ -1,84 +1,57 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs \
-; RUN: -disable-strictnode-mutation -target-abi ilp32f < %s \
-; RUN: | FileCheck -check-prefix=RV32IZFH %s
+; RUN: -disable-strictnode-mutation -target-abi ilp32f < %s | FileCheck %s
; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs \
-; RUN: -disable-strictnode-mutation -target-abi lp64f < %s \
-; RUN: | FileCheck -check-prefix=RV64IZFH %s
+; RUN: -disable-strictnode-mutation -target-abi lp64f < %s | FileCheck %s
; FIXME: We can't test without Zfh because soft promote legalization isn't
; implemented in SelectionDAG for STRICT nodes.
define half @fadd_h(half %a, half %b) nounwind strictfp {
-; RV32IZFH-LABEL: fadd_h:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: fadd.h fa0, fa0, fa1
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: fadd_h:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fadd.h fa0, fa0, fa1
-; RV64IZFH-NEXT: ret
+; CHECK-LABEL: fadd_h:
+; CHECK: # %bb.0:
+; CHECK-NEXT: fadd.h fa0, fa0, fa1
+; CHECK-NEXT: ret
%1 = call half @llvm.experimental.constrained.fadd.f16(half %a, half %b, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
ret half %1
}
declare half @llvm.experimental.constrained.fadd.f16(half, half, metadata, metadata)
define half @fsub_h(half %a, half %b) nounwind strictfp {
-; RV32IZFH-LABEL: fsub_h:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: fsub.h fa0, fa0, fa1
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: fsub_h:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fsub.h fa0, fa0, fa1
-; RV64IZFH-NEXT: ret
+; CHECK-LABEL: fsub_h:
+; CHECK: # %bb.0:
+; CHECK-NEXT: fsub.h fa0, fa0, fa1
+; CHECK-NEXT: ret
%1 = call half @llvm.experimental.constrained.fsub.f16(half %a, half %b, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
ret half %1
}
declare half @llvm.experimental.constrained.fsub.f16(half, half, metadata, metadata)
define half @fmul_h(half %a, half %b) nounwind strictfp {
-; RV32IZFH-LABEL: fmul_h:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: fmul.h fa0, fa0, fa1
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: fmul_h:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fmul.h fa0, fa0, fa1
-; RV64IZFH-NEXT: ret
+; CHECK-LABEL: fmul_h:
+; CHECK: # %bb.0:
+; CHECK-NEXT: fmul.h fa0, fa0, fa1
+; CHECK-NEXT: ret
%1 = call half @llvm.experimental.constrained.fmul.f16(half %a, half %b, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
ret half %1
}
declare half @llvm.experimental.constrained.fmul.f16(half, half, metadata, metadata)
define half @fdiv_h(half %a, half %b) nounwind strictfp {
-; RV32IZFH-LABEL: fdiv_h:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: fdiv.h fa0, fa0, fa1
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: fdiv_h:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fdiv.h fa0, fa0, fa1
-; RV64IZFH-NEXT: ret
+; CHECK-LABEL: fdiv_h:
+; CHECK: # %bb.0:
+; CHECK-NEXT: fdiv.h fa0, fa0, fa1
+; CHECK-NEXT: ret
%1 = call half @llvm.experimental.constrained.fdiv.f16(half %a, half %b, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
ret half %1
}
declare half @llvm.experimental.constrained.fdiv.f16(half, half, metadata, metadata)
define half @fsqrt_h(half %a) nounwind strictfp {
-; RV32IZFH-LABEL: fsqrt_h:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: fsqrt.h fa0, fa0
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: fsqrt_h:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fsqrt.h fa0, fa0
-; RV64IZFH-NEXT: ret
+; CHECK-LABEL: fsqrt_h:
+; CHECK: # %bb.0:
+; CHECK-NEXT: fsqrt.h fa0, fa0
+; CHECK-NEXT: ret
%1 = call half @llvm.experimental.constrained.sqrt.f16(half %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
ret half %1
}
@@ -99,34 +72,22 @@ declare half @llvm.experimental.constrained.sqrt.f16(half, metadata, metadata)
;declare half @llvm.experimental.constrained.maxnum.f16(half, half, metadata) strictfp
define half @fmadd_h(half %a, half %b, half %c) nounwind strictfp {
-; RV32IZFH-LABEL: fmadd_h:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: fmadd.h fa0, fa0, fa1, fa2
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: fmadd_h:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fmadd.h fa0, fa0, fa1, fa2
-; RV64IZFH-NEXT: ret
+; CHECK-LABEL: fmadd_h:
+; CHECK: # %bb.0:
+; CHECK-NEXT: fmadd.h fa0, fa0, fa1, fa2
+; CHECK-NEXT: ret
%1 = call half @llvm.experimental.constrained.fma.f16(half %a, half %b, half %c, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
ret half %1
}
declare half @llvm.experimental.constrained.fma.f16(half, half, half, metadata, metadata) strictfp
define half @fmsub_h(half %a, half %b, half %c) nounwind strictfp {
-; RV32IZFH-LABEL: fmsub_h:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: fmv.h.x ft0, zero
-; RV32IZFH-NEXT: fadd.h ft0, fa2, ft0
-; RV32IZFH-NEXT: fmsub.h fa0, fa0, fa1, ft0
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: fmsub_h:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fmv.h.x ft0, zero
-; RV64IZFH-NEXT: fadd.h ft0, fa2, ft0
-; RV64IZFH-NEXT: fmsub.h fa0, fa0, fa1, ft0
-; RV64IZFH-NEXT: ret
+; CHECK-LABEL: fmsub_h:
+; CHECK: # %bb.0:
+; CHECK-NEXT: fmv.h.x ft0, zero
+; CHECK-NEXT: fadd.h ft0, fa2, ft0
+; CHECK-NEXT: fmsub.h fa0, fa0, fa1, ft0
+; CHECK-NEXT: ret
%c_ = fadd half 0.0, %c ; avoid negation using xor
%negc = fneg half %c_
%1 = call half @llvm.experimental.constrained.fma.f16(half %a, half %b, half %negc, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
@@ -134,21 +95,13 @@ define half @fmsub_h(half %a, half %b, half %c) nounwind strictfp {
}
define half @fnmadd_h(half %a, half %b, half %c) nounwind strictfp {
-; RV32IZFH-LABEL: fnmadd_h:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: fmv.h.x ft0, zero
-; RV32IZFH-NEXT: fadd.h ft1, fa0, ft0
-; RV32IZFH-NEXT: fadd.h ft0, fa2, ft0
-; RV32IZFH-NEXT: fnmadd.h fa0, ft1, fa1, ft0
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: fnmadd_h:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fmv.h.x ft0, zero
-; RV64IZFH-NEXT: fadd.h ft1, fa0, ft0
-; RV64IZFH-NEXT: fadd.h ft0, fa2, ft0
-; RV64IZFH-NEXT: fnmadd.h fa0, ft1, fa1, ft0
-; RV64IZFH-NEXT: ret
+; CHECK-LABEL: fnmadd_h:
+; CHECK: # %bb.0:
+; CHECK-NEXT: fmv.h.x ft0, zero
+; CHECK-NEXT: fadd.h ft1, fa0, ft0
+; CHECK-NEXT: fadd.h ft0, fa2, ft0
+; CHECK-NEXT: fnmadd.h fa0, ft1, fa1, ft0
+; CHECK-NEXT: ret
%a_ = fadd half 0.0, %a
%c_ = fadd half 0.0, %c
%nega = fneg half %a_
@@ -158,21 +111,13 @@ define half @fnmadd_h(half %a, half %b, half %c) nounwind strictfp {
}
define half @fnmadd_h_2(half %a, half %b, half %c) nounwind strictfp {
-; RV32IZFH-LABEL: fnmadd_h_2:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: fmv.h.x ft0, zero
-; RV32IZFH-NEXT: fadd.h ft1, fa1, ft0
-; RV32IZFH-NEXT: fadd.h ft0, fa2, ft0
-; RV32IZFH-NEXT: fnmadd.h fa0, ft1, fa0, ft0
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: fnmadd_h_2:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fmv.h.x ft0, zero
-; RV64IZFH-NEXT: fadd.h ft1, fa1, ft0
-; RV64IZFH-NEXT: fadd.h ft0, fa2, ft0
-; RV64IZFH-NEXT: fnmadd.h fa0, ft1, fa0, ft0
-; RV64IZFH-NEXT: ret
+; CHECK-LABEL: fnmadd_h_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: fmv.h.x ft0, zero
+; CHECK-NEXT: fadd.h ft1, fa1, ft0
+; CHECK-NEXT: fadd.h ft0, fa2, ft0
+; CHECK-NEXT: fnmadd.h fa0, ft1, fa0, ft0
+; CHECK-NEXT: ret
%b_ = fadd half 0.0, %b
%c_ = fadd half 0.0, %c
%negb = fneg half %b_
@@ -182,19 +127,12 @@ define half @fnmadd_h_2(half %a, half %b, half %c) nounwind strictfp {
}
define half @fnmsub_h(half %a, half %b, half %c) nounwind strictfp {
-; RV32IZFH-LABEL: fnmsub_h:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: fmv.h.x ft0, zero
-; RV32IZFH-NEXT: fadd.h ft0, fa0, ft0
-; RV32IZFH-NEXT: fnmsub.h fa0, ft0, fa1, fa2
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: fnmsub_h:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fmv.h.x ft0, zero
-; RV64IZFH-NEXT: fadd.h ft0, fa0, ft0
-; RV64IZFH-NEXT: fnmsub.h fa0, ft0, fa1, fa2
-; RV64IZFH-NEXT: ret
+; CHECK-LABEL: fnmsub_h:
+; CHECK: # %bb.0:
+; CHECK-NEXT: fmv.h.x ft0, zero
+; CHECK-NEXT: fadd.h ft0, fa0, ft0
+; CHECK-NEXT: fnmsub.h fa0, ft0, fa1, fa2
+; CHECK-NEXT: ret
%a_ = fadd half 0.0, %a
%nega = fneg half %a_
%1 = call half @llvm.experimental.constrained.fma.f16(half %nega, half %b, half %c, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
@@ -202,19 +140,12 @@ define half @fnmsub_h(half %a, half %b, half %c) nounwind strictfp {
}
define half @fnmsub_h_2(half %a, half %b, half %c) nounwind strictfp {
-; RV32IZFH-LABEL: fnmsub_h_2:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: fmv.h.x ft0, zero
-; RV32IZFH-NEXT: fadd.h ft0, fa1, ft0
-; RV32IZFH-NEXT: fnmsub.h fa0, ft0, fa0, fa2
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: fnmsub_h_2:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fmv.h.x ft0, zero
-; RV64IZFH-NEXT: fadd.h ft0, fa1, ft0
-; RV64IZFH-NEXT: fnmsub.h fa0, ft0, fa0, fa2
-; RV64IZFH-NEXT: ret
+; CHECK-LABEL: fnmsub_h_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: fmv.h.x ft0, zero
+; CHECK-NEXT: fadd.h ft0, fa1, ft0
+; CHECK-NEXT: fnmsub.h fa0, ft0, fa0, fa2
+; CHECK-NEXT: ret
%b_ = fadd half 0.0, %b
%negb = fneg half %b_
%1 = call half @llvm.experimental.constrained.fma.f16(half %a, half %negb, half %c, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
diff --git a/llvm/test/CodeGen/RISCV/half-arith.ll b/llvm/test/CodeGen/RISCV/half-arith.ll
index d343aa23e0a0..b221e075aac9 100644
--- a/llvm/test/CodeGen/RISCV/half-arith.ll
+++ b/llvm/test/CodeGen/RISCV/half-arith.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs \
-; RUN: -target-abi ilp32f < %s | FileCheck -check-prefix=RV32IZFH %s
+; RUN: -target-abi ilp32f < %s | FileCheck -check-prefix=CHECKIZFH %s
; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs \
-; RUN: -target-abi lp64f < %s | FileCheck -check-prefix=RV64IZFH %s
+; RUN: -target-abi lp64f < %s | FileCheck -check-prefix=CHECKIZFH %s
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32I %s
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
@@ -14,15 +14,10 @@
; instructions that don't directly match a RISC-V instruction.
define half @fadd_s(half %a, half %b) nounwind {
-; RV32IZFH-LABEL: fadd_s:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: fadd.h fa0, fa0, fa1
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: fadd_s:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fadd.h fa0, fa0, fa1
-; RV64IZFH-NEXT: ret
+;CHECKIZFH-LABEL: fadd_s:
+;CHECKIZFH: # %bb.0:
+;CHECKIZFH-NEXT: fadd.h fa0, fa0, fa1
+;CHECKIZFH-NEXT: ret
;
; RV32I-LABEL: fadd_s:
; RV32I: # %bb.0:
@@ -80,15 +75,10 @@ define half @fadd_s(half %a, half %b) nounwind {
}
define half @fsub_s(half %a, half %b) nounwind {
-; RV32IZFH-LABEL: fsub_s:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: fsub.h fa0, fa0, fa1
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: fsub_s:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fsub.h fa0, fa0, fa1
-; RV64IZFH-NEXT: ret
+;CHECKIZFH-LABEL: fsub_s:
+;CHECKIZFH: # %bb.0:
+;CHECKIZFH-NEXT: fsub.h fa0, fa0, fa1
+;CHECKIZFH-NEXT: ret
;
; RV32I-LABEL: fsub_s:
; RV32I: # %bb.0:
@@ -146,15 +136,10 @@ define half @fsub_s(half %a, half %b) nounwind {
}
define half @fmul_s(half %a, half %b) nounwind {
-; RV32IZFH-LABEL: fmul_s:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: fmul.h fa0, fa0, fa1
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: fmul_s:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fmul.h fa0, fa0, fa1
-; RV64IZFH-NEXT: ret
+;CHECKIZFH-LABEL: fmul_s:
+;CHECKIZFH: # %bb.0:
+;CHECKIZFH-NEXT: fmul.h fa0, fa0, fa1
+;CHECKIZFH-NEXT: ret
;
; RV32I-LABEL: fmul_s:
; RV32I: # %bb.0:
@@ -212,15 +197,10 @@ define half @fmul_s(half %a, half %b) nounwind {
}
define half @fdiv_s(half %a, half %b) nounwind {
-; RV32IZFH-LABEL: fdiv_s:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: fdiv.h fa0, fa0, fa1
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: fdiv_s:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fdiv.h fa0, fa0, fa1
-; RV64IZFH-NEXT: ret
+;CHECKIZFH-LABEL: fdiv_s:
+;CHECKIZFH: # %bb.0:
+;CHECKIZFH-NEXT: fdiv.h fa0, fa0, fa1
+;CHECKIZFH-NEXT: ret
;
; RV32I-LABEL: fdiv_s:
; RV32I: # %bb.0:
@@ -280,15 +260,10 @@ define half @fdiv_s(half %a, half %b) nounwind {
declare half @llvm.sqrt.f16(half)
define half @fsqrt_s(half %a) nounwind {
-; RV32IZFH-LABEL: fsqrt_s:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: fsqrt.h fa0, fa0
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: fsqrt_s:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fsqrt.h fa0, fa0
-; RV64IZFH-NEXT: ret
+;CHECKIZFH-LABEL: fsqrt_s:
+;CHECKIZFH: # %bb.0:
+;CHECKIZFH-NEXT: fsqrt.h fa0, fa0
+;CHECKIZFH-NEXT: ret
;
; RV32I-LABEL: fsqrt_s:
; RV32I: # %bb.0:
@@ -322,15 +297,10 @@ define half @fsqrt_s(half %a) nounwind {
declare half @llvm.copysign.f16(half, half)
define half @fsgnj_s(half %a, half %b) nounwind {
-; RV32IZFH-LABEL: fsgnj_s:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: fsgnj.h fa0, fa0, fa1
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: fsgnj_s:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fsgnj.h fa0, fa0, fa1
-; RV64IZFH-NEXT: ret
+;CHECKIZFH-LABEL: fsgnj_s:
+;CHECKIZFH: # %bb.0:
+;CHECKIZFH-NEXT: fsgnj.h fa0, fa0, fa1
+;CHECKIZFH-NEXT: ret
;
; RV32I-LABEL: fsgnj_s:
; RV32I: # %bb.0:
@@ -356,19 +326,12 @@ define half @fsgnj_s(half %a, half %b) nounwind {
; This function performs extra work to ensure that
; DAGCombiner::visitBITCAST doesn't replace the fneg with an xor.
define i32 @fneg_s(half %a, half %b) nounwind {
-; RV32IZFH-LABEL: fneg_s:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: fadd.h ft0, fa0, fa0
-; RV32IZFH-NEXT: fneg.h ft1, ft0
-; RV32IZFH-NEXT: feq.h a0, ft0, ft1
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: fneg_s:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fadd.h ft0, fa0, fa0
-; RV64IZFH-NEXT: fneg.h ft1, ft0
-; RV64IZFH-NEXT: feq.h a0, ft0, ft1
-; RV64IZFH-NEXT: ret
+;CHECKIZFH-LABEL: fneg_s:
+;CHECKIZFH: # %bb.0:
+;CHECKIZFH-NEXT: fadd.h ft0, fa0, fa0
+;CHECKIZFH-NEXT: fneg.h ft1, ft0
+;CHECKIZFH-NEXT: feq.h a0, ft0, ft1
+;CHECKIZFH-NEXT: ret
;
; RV32I-LABEL: fneg_s:
; RV32I: # %bb.0:
@@ -441,17 +404,11 @@ define i32 @fneg_s(half %a, half %b) nounwind {
; This function performs extra work to ensure that
; DAGCombiner::visitBITCAST doesn't replace the fneg with an xor.
define half @fsgnjn_s(half %a, half %b) nounwind {
-; RV32IZFH-LABEL: fsgnjn_s:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: fadd.h ft0, fa0, fa1
-; RV32IZFH-NEXT: fsgnjn.h fa0, fa0, ft0
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: fsgnjn_s:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fadd.h ft0, fa0, fa1
-; RV64IZFH-NEXT: fsgnjn.h fa0, fa0, ft0
-; RV64IZFH-NEXT: ret
+;CHECKIZFH-LABEL: fsgnjn_s:
+;CHECKIZFH: # %bb.0:
+;CHECKIZFH-NEXT: fadd.h ft0, fa0, fa1
+;CHECKIZFH-NEXT: fsgnjn.h fa0, fa0, ft0
+;CHECKIZFH-NEXT: ret
;
; RV32I-LABEL: fsgnjn_s:
; RV32I: # %bb.0:
@@ -541,19 +498,12 @@ declare half @llvm.fabs.f16(half)
; This function performs extra work to ensure that
; DAGCombiner::visitBITCAST doesn't replace the fabs with an and.
define half @fabs_s(half %a, half %b) nounwind {
-; RV32IZFH-LABEL: fabs_s:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: fadd.h ft0, fa0, fa1
-; RV32IZFH-NEXT: fabs.h ft1, ft0
-; RV32IZFH-NEXT: fadd.h fa0, ft1, ft0
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: fabs_s:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fadd.h ft0, fa0, fa1
-; RV64IZFH-NEXT: fabs.h ft1, ft0
-; RV64IZFH-NEXT: fadd.h fa0, ft1, ft0
-; RV64IZFH-NEXT: ret
+;CHECKIZFH-LABEL: fabs_s:
+;CHECKIZFH: # %bb.0:
+;CHECKIZFH-NEXT: fadd.h ft0, fa0, fa1
+;CHECKIZFH-NEXT: fabs.h ft1, ft0
+;CHECKIZFH-NEXT: fadd.h fa0, ft1, ft0
+;CHECKIZFH-NEXT: ret
;
; RV32I-LABEL: fabs_s:
; RV32I: # %bb.0:
@@ -637,15 +587,10 @@ define half @fabs_s(half %a, half %b) nounwind {
declare half @llvm.minnum.f16(half, half)
define half @fmin_s(half %a, half %b) nounwind {
-; RV32IZFH-LABEL: fmin_s:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: fmin.h fa0, fa0, fa1
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: fmin_s:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fmin.h fa0, fa0, fa1
-; RV64IZFH-NEXT: ret
+;CHECKIZFH-LABEL: fmin_s:
+;CHECKIZFH: # %bb.0:
+;CHECKIZFH-NEXT: fmin.h fa0, fa0, fa1
+;CHECKIZFH-NEXT: ret
;
; RV32I-LABEL: fmin_s:
; RV32I: # %bb.0:
@@ -705,15 +650,10 @@ define half @fmin_s(half %a, half %b) nounwind {
declare half @llvm.maxnum.f16(half, half)
define half @fmax_s(half %a, half %b) nounwind {
-; RV32IZFH-LABEL: fmax_s:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: fmax.h fa0, fa0, fa1
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: fmax_s:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fmax.h fa0, fa0, fa1
-; RV64IZFH-NEXT: ret
+;CHECKIZFH-LABEL: fmax_s:
+;CHECKIZFH: # %bb.0:
+;CHECKIZFH-NEXT: fmax.h fa0, fa0, fa1
+;CHECKIZFH-NEXT: ret
;
; RV32I-LABEL: fmax_s:
; RV32I: # %bb.0:
@@ -773,15 +713,10 @@ define half @fmax_s(half %a, half %b) nounwind {
declare half @llvm.fma.f16(half, half, half)
define half @fmadd_s(half %a, half %b, half %c) nounwind {
-; RV32IZFH-LABEL: fmadd_s:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: fmadd.h fa0, fa0, fa1, fa2
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: fmadd_s:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fmadd.h fa0, fa0, fa1, fa2
-; RV64IZFH-NEXT: ret
+;CHECKIZFH-LABEL: fmadd_s:
+;CHECKIZFH: # %bb.0:
+;CHECKIZFH-NEXT: fmadd.h fa0, fa0, fa1, fa2
+;CHECKIZFH-NEXT: ret
;
; RV32I-LABEL: fmadd_s:
; RV32I: # %bb.0:
@@ -853,19 +788,12 @@ define half @fmadd_s(half %a, half %b, half %c) nounwind {
}
define half @fmsub_s(half %a, half %b, half %c) nounwind {
-; RV32IZFH-LABEL: fmsub_s:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: fmv.h.x ft0, zero
-; RV32IZFH-NEXT: fadd.h ft0, fa2, ft0
-; RV32IZFH-NEXT: fmsub.h fa0, fa0, fa1, ft0
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: fmsub_s:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fmv.h.x ft0, zero
-; RV64IZFH-NEXT: fadd.h ft0, fa2, ft0
-; RV64IZFH-NEXT: fmsub.h fa0, fa0, fa1, ft0
-; RV64IZFH-NEXT: ret
+;CHECKIZFH-LABEL: fmsub_s:
+;CHECKIZFH: # %bb.0:
+;CHECKIZFH-NEXT: fmv.h.x ft0, zero
+;CHECKIZFH-NEXT: fadd.h ft0, fa2, ft0
+;CHECKIZFH-NEXT: fmsub.h fa0, fa0, fa1, ft0
+;CHECKIZFH-NEXT: ret
;
; RV32I-LABEL: fmsub_s:
; RV32I: # %bb.0:
@@ -961,21 +889,13 @@ define half @fmsub_s(half %a, half %b, half %c) nounwind {
}
define half @fnmadd_s(half %a, half %b, half %c) nounwind {
-; RV32IZFH-LABEL: fnmadd_s:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: fmv.h.x ft0, zero
-; RV32IZFH-NEXT: fadd.h ft1, fa0, ft0
-; RV32IZFH-NEXT: fadd.h ft0, fa2, ft0
-; RV32IZFH-NEXT: fnmadd.h fa0, ft1, fa1, ft0
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: fnmadd_s:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fmv.h.x ft0, zero
-; RV64IZFH-NEXT: fadd.h ft1, fa0, ft0
-; RV64IZFH-NEXT: fadd.h ft0, fa2, ft0
-; RV64IZFH-NEXT: fnmadd.h fa0, ft1, fa1, ft0
-; RV64IZFH-NEXT: ret
+;CHECKIZFH-LABEL: fnmadd_s:
+;CHECKIZFH: # %bb.0:
+;CHECKIZFH-NEXT: fmv.h.x ft0, zero
+;CHECKIZFH-NEXT: fadd.h ft1, fa0, ft0
+;CHECKIZFH-NEXT: fadd.h ft0, fa2, ft0
+;CHECKIZFH-NEXT: fnmadd.h fa0, ft1, fa1, ft0
+;CHECKIZFH-NEXT: ret
;
; RV32I-LABEL: fnmadd_s:
; RV32I: # %bb.0:
@@ -1101,21 +1021,13 @@ define half @fnmadd_s(half %a, half %b, half %c) nounwind {
}
define half @fnmadd_s_2(half %a, half %b, half %c) nounwind {
-; RV32IZFH-LABEL: fnmadd_s_2:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: fmv.h.x ft0, zero
-; RV32IZFH-NEXT: fadd.h ft1, fa1, ft0
-; RV32IZFH-NEXT: fadd.h ft0, fa2, ft0
-; RV32IZFH-NEXT: fnmadd.h fa0, ft1, fa0, ft0
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: fnmadd_s_2:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fmv.h.x ft0, zero
-; RV64IZFH-NEXT: fadd.h ft1, fa1, ft0
-; RV64IZFH-NEXT: fadd.h ft0, fa2, ft0
-; RV64IZFH-NEXT: fnmadd.h fa0, ft1, fa0, ft0
-; RV64IZFH-NEXT: ret
+;CHECKIZFH-LABEL: fnmadd_s_2:
+;CHECKIZFH: # %bb.0:
+;CHECKIZFH-NEXT: fmv.h.x ft0, zero
+;CHECKIZFH-NEXT: fadd.h ft1, fa1, ft0
+;CHECKIZFH-NEXT: fadd.h ft0, fa2, ft0
+;CHECKIZFH-NEXT: fnmadd.h fa0, ft1, fa0, ft0
+;CHECKIZFH-NEXT: ret
;
; RV32I-LABEL: fnmadd_s_2:
; RV32I: # %bb.0:
@@ -1414,19 +1326,12 @@ define half @fnmadd_nsz(half %a, half %b, half %c) nounwind {
}
define half @fnmsub_s(half %a, half %b, half %c) nounwind {
-; RV32IZFH-LABEL: fnmsub_s:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: fmv.h.x ft0, zero
-; RV32IZFH-NEXT: fadd.h ft0, fa0, ft0
-; RV32IZFH-NEXT: fnmsub.h fa0, ft0, fa1, fa2
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: fnmsub_s:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fmv.h.x ft0, zero
-; RV64IZFH-NEXT: fadd.h ft0, fa0, ft0
-; RV64IZFH-NEXT: fnmsub.h fa0, ft0, fa1, fa2
-; RV64IZFH-NEXT: ret
+;CHECKIZFH-LABEL: fnmsub_s:
+;CHECKIZFH: # %bb.0:
+;CHECKIZFH-NEXT: fmv.h.x ft0, zero
+;CHECKIZFH-NEXT: fadd.h ft0, fa0, ft0
+;CHECKIZFH-NEXT: fnmsub.h fa0, ft0, fa1, fa2
+;CHECKIZFH-NEXT: ret
;
; RV32I-LABEL: fnmsub_s:
; RV32I: # %bb.0:
@@ -1520,19 +1425,12 @@ define half @fnmsub_s(half %a, half %b, half %c) nounwind {
}
define half @fnmsub_s_2(half %a, half %b, half %c) nounwind {
-; RV32IZFH-LABEL: fnmsub_s_2:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: fmv.h.x ft0, zero
-; RV32IZFH-NEXT: fadd.h ft0, fa1, ft0
-; RV32IZFH-NEXT: fnmsub.h fa0, ft0, fa0, fa2
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: fnmsub_s_2:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fmv.h.x ft0, zero
-; RV64IZFH-NEXT: fadd.h ft0, fa1, ft0
-; RV64IZFH-NEXT: fnmsub.h fa0, ft0, fa0, fa2
-; RV64IZFH-NEXT: ret
+;CHECKIZFH-LABEL: fnmsub_s_2:
+;CHECKIZFH: # %bb.0:
+;CHECKIZFH-NEXT: fmv.h.x ft0, zero
+;CHECKIZFH-NEXT: fadd.h ft0, fa1, ft0
+;CHECKIZFH-NEXT: fnmsub.h fa0, ft0, fa0, fa2
+;CHECKIZFH-NEXT: ret
;
; RV32I-LABEL: fnmsub_s_2:
; RV32I: # %bb.0:
@@ -1628,15 +1526,10 @@ define half @fnmsub_s_2(half %a, half %b, half %c) nounwind {
}
define half @fmadd_s_contract(half %a, half %b, half %c) nounwind {
-; RV32IZFH-LABEL: fmadd_s_contract:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: fmadd.h fa0, fa0, fa1, fa2
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: fmadd_s_contract:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fmadd.h fa0, fa0, fa1, fa2
-; RV64IZFH-NEXT: ret
+;CHECKIZFH-LABEL: fmadd_s_contract:
+;CHECKIZFH: # %bb.0:
+;CHECKIZFH-NEXT: fmadd.h fa0, fa0, fa1, fa2
+;CHECKIZFH-NEXT: ret
;
; RV32I-LABEL: fmadd_s_contract:
; RV32I: # %bb.0:
@@ -1719,19 +1612,12 @@ define half @fmadd_s_contract(half %a, half %b, half %c) nounwind {
}
define half @fmsub_s_contract(half %a, half %b, half %c) nounwind {
-; RV32IZFH-LABEL: fmsub_s_contract:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: fmv.h.x ft0, zero
-; RV32IZFH-NEXT: fadd.h ft0, fa2, ft0
-; RV32IZFH-NEXT: fmsub.h fa0, fa0, fa1, ft0
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: fmsub_s_contract:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fmv.h.x ft0, zero
-; RV64IZFH-NEXT: fadd.h ft0, fa2, ft0
-; RV64IZFH-NEXT: fmsub.h fa0, fa0, fa1, ft0
-; RV64IZFH-NEXT: ret
+;CHECKIZFH-LABEL: fmsub_s_contract:
+;CHECKIZFH: # %bb.0:
+;CHECKIZFH-NEXT: fmv.h.x ft0, zero
+;CHECKIZFH-NEXT: fadd.h ft0, fa2, ft0
+;CHECKIZFH-NEXT: fmsub.h fa0, fa0, fa1, ft0
+;CHECKIZFH-NEXT: ret
;
; RV32I-LABEL: fmsub_s_contract:
; RV32I: # %bb.0:
@@ -1827,23 +1713,14 @@ define half @fmsub_s_contract(half %a, half %b, half %c) nounwind {
}
define half @fnmadd_s_contract(half %a, half %b, half %c) nounwind {
-; RV32IZFH-LABEL: fnmadd_s_contract:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: fmv.h.x ft0, zero
-; RV32IZFH-NEXT: fadd.h ft1, fa0, ft0
-; RV32IZFH-NEXT: fadd.h ft2, fa1, ft0
-; RV32IZFH-NEXT: fadd.h ft0, fa2, ft0
-; RV32IZFH-NEXT: fnmadd.h fa0, ft1, ft2, ft0
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: fnmadd_s_contract:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fmv.h.x ft0, zero
-; RV64IZFH-NEXT: fadd.h ft1, fa0, ft0
-; RV64IZFH-NEXT: fadd.h ft2, fa1, ft0
-; RV64IZFH-NEXT: fadd.h ft0, fa2, ft0
-; RV64IZFH-NEXT: fnmadd.h fa0, ft1, ft2, ft0
-; RV64IZFH-NEXT: ret
+;CHECKIZFH-LABEL: fnmadd_s_contract:
+;CHECKIZFH: # %bb.0:
+;CHECKIZFH-NEXT: fmv.h.x ft0, zero
+;CHECKIZFH-NEXT: fadd.h ft1, fa0, ft0
+;CHECKIZFH-NEXT: fadd.h ft2, fa1, ft0
+;CHECKIZFH-NEXT: fadd.h ft0, fa2, ft0
+;CHECKIZFH-NEXT: fnmadd.h fa0, ft1, ft2, ft0
+;CHECKIZFH-NEXT: ret
;
; RV32I-LABEL: fnmadd_s_contract:
; RV32I: # %bb.0:
@@ -1976,21 +1853,13 @@ define half @fnmadd_s_contract(half %a, half %b, half %c) nounwind {
}
define half @fnmsub_s_contract(half %a, half %b, half %c) nounwind {
-; RV32IZFH-LABEL: fnmsub_s_contract:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: fmv.h.x ft0, zero
-; RV32IZFH-NEXT: fadd.h ft1, fa0, ft0
-; RV32IZFH-NEXT: fadd.h ft0, fa1, ft0
-; RV32IZFH-NEXT: fnmsub.h fa0, ft1, ft0, fa2
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: fnmsub_s_contract:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fmv.h.x ft0, zero
-; RV64IZFH-NEXT: fadd.h ft1, fa0, ft0
-; RV64IZFH-NEXT: fadd.h ft0, fa1, ft0
-; RV64IZFH-NEXT: fnmsub.h fa0, ft1, ft0, fa2
-; RV64IZFH-NEXT: ret
+;CHECKIZFH-LABEL: fnmsub_s_contract:
+;CHECKIZFH: # %bb.0:
+;CHECKIZFH-NEXT: fmv.h.x ft0, zero
+;CHECKIZFH-NEXT: fadd.h ft1, fa0, ft0
+;CHECKIZFH-NEXT: fadd.h ft0, fa1, ft0
+;CHECKIZFH-NEXT: fnmsub.h fa0, ft1, ft0, fa2
+;CHECKIZFH-NEXT: ret
;
; RV32I-LABEL: fnmsub_s_contract:
; RV32I: # %bb.0:
diff --git a/llvm/test/CodeGen/RISCV/half-convert-strict.ll b/llvm/test/CodeGen/RISCV/half-convert-strict.ll
index b12422cfbd53..d87106b08ddb 100644
--- a/llvm/test/CodeGen/RISCV/half-convert-strict.ll
+++ b/llvm/test/CodeGen/RISCV/half-convert-strict.ll
@@ -1,10 +1,10 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs \
; RUN: -target-abi ilp32f -disable-strictnode-mutation < %s \
-; RUN: | FileCheck -check-prefix=RV32IZFH %s
+; RUN: | FileCheck -check-prefixes=CHECKIZFH,RV32IZFH %s
; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs \
; RUN: -target-abi lp64f -disable-strictnode-mutation < %s \
-; RUN: | FileCheck -check-prefix=RV64IZFH %s
+; RUN: | FileCheck -check-prefixes=CHECKIZFH,RV64IZFH %s
; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh -verify-machineinstrs \
; RUN: -target-abi ilp32d -disable-strictnode-mutation < %s \
; RUN: | FileCheck -check-prefix=RV32IDZFH %s
@@ -67,15 +67,10 @@ define i16 @fcvt_ui_h(half %a) nounwind strictfp {
declare i16 @llvm.experimental.constrained.fptoui.i16.f16(half, metadata)
define i32 @fcvt_w_h(half %a) nounwind strictfp {
-; RV32IZFH-LABEL: fcvt_w_h:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rtz
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: fcvt_w_h:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fcvt.w.h a0, fa0, rtz
-; RV64IZFH-NEXT: ret
+; CHECKIZFH-LABEL: fcvt_w_h:
+; CHECKIZFH: # %bb.0:
+; CHECKIZFH-NEXT: fcvt.w.h a0, fa0, rtz
+; CHECKIZFH-NEXT: ret
;
; RV32IDZFH-LABEL: fcvt_w_h:
; RV32IDZFH: # %bb.0:
@@ -92,15 +87,10 @@ define i32 @fcvt_w_h(half %a) nounwind strictfp {
declare i32 @llvm.experimental.constrained.fptosi.i32.f16(half, metadata)
define i32 @fcvt_wu_h(half %a) nounwind strictfp {
-; RV32IZFH-LABEL: fcvt_wu_h:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: fcvt.wu.h a0, fa0, rtz
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: fcvt_wu_h:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fcvt.wu.h a0, fa0, rtz
-; RV64IZFH-NEXT: ret
+; CHECKIZFH-LABEL: fcvt_wu_h:
+; CHECKIZFH: # %bb.0:
+; CHECKIZFH-NEXT: fcvt.wu.h a0, fa0, rtz
+; CHECKIZFH-NEXT: ret
;
; RV32IDZFH-LABEL: fcvt_wu_h:
; RV32IDZFH: # %bb.0:
@@ -120,25 +110,15 @@ declare i32 @llvm.experimental.constrained.fptoui.i32.f16(half, metadata)
; inserted on RV64.
; FIXME: We should not have an fcvt.wu.h and an fcvt.lu.h.
define i32 @fcvt_wu_h_multiple_use(half %x, i32* %y) {
-; RV32IZFH-LABEL: fcvt_wu_h_multiple_use:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: fcvt.wu.h a1, fa0, rtz
-; RV32IZFH-NEXT: li a0, 1
-; RV32IZFH-NEXT: beqz a1, .LBB4_2
-; RV32IZFH-NEXT: # %bb.1:
-; RV32IZFH-NEXT: mv a0, a1
-; RV32IZFH-NEXT: .LBB4_2:
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: fcvt_wu_h_multiple_use:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fcvt.wu.h a1, fa0, rtz
-; RV64IZFH-NEXT: li a0, 1
-; RV64IZFH-NEXT: beqz a1, .LBB4_2
-; RV64IZFH-NEXT: # %bb.1:
-; RV64IZFH-NEXT: mv a0, a1
-; RV64IZFH-NEXT: .LBB4_2:
-; RV64IZFH-NEXT: ret
+; CHECKIZFH-LABEL: fcvt_wu_h_multiple_use:
+; CHECKIZFH: # %bb.0:
+; CHECKIZFH-NEXT: fcvt.wu.h a1, fa0, rtz
+; CHECKIZFH-NEXT: li a0, 1
+; CHECKIZFH-NEXT: beqz a1, .LBB4_2
+; CHECKIZFH-NEXT: # %bb.1:
+; CHECKIZFH-NEXT: mv a0, a1
+; CHECKIZFH-NEXT: .LBB4_2:
+; CHECKIZFH-NEXT: ret
;
; RV32IDZFH-LABEL: fcvt_wu_h_multiple_use:
; RV32IDZFH: # %bb.0:
@@ -265,15 +245,10 @@ define half @fcvt_h_si(i16 %a) nounwind strictfp {
declare half @llvm.experimental.constrained.sitofp.f16.i16(i16, metadata, metadata)
define half @fcvt_h_si_signext(i16 signext %a) nounwind strictfp {
-; RV32IZFH-LABEL: fcvt_h_si_signext:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: fcvt.h.w fa0, a0
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: fcvt_h_si_signext:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fcvt.h.w fa0, a0
-; RV64IZFH-NEXT: ret
+; CHECKIZFH-LABEL: fcvt_h_si_signext:
+; CHECKIZFH: # %bb.0:
+; CHECKIZFH-NEXT: fcvt.h.w fa0, a0
+; CHECKIZFH-NEXT: ret
;
; RV32IDZFH-LABEL: fcvt_h_si_signext:
; RV32IDZFH: # %bb.0:
@@ -322,15 +297,10 @@ define half @fcvt_h_ui(i16 %a) nounwind strictfp {
declare half @llvm.experimental.constrained.uitofp.f16.i16(i16, metadata, metadata)
define half @fcvt_h_ui_zeroext(i16 zeroext %a) nounwind strictfp {
-; RV32IZFH-LABEL: fcvt_h_ui_zeroext:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: fcvt.h.wu fa0, a0
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: fcvt_h_ui_zeroext:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fcvt.h.wu fa0, a0
-; RV64IZFH-NEXT: ret
+; CHECKIZFH-LABEL: fcvt_h_ui_zeroext:
+; CHECKIZFH: # %bb.0:
+; CHECKIZFH-NEXT: fcvt.h.wu fa0, a0
+; CHECKIZFH-NEXT: ret
;
; RV32IDZFH-LABEL: fcvt_h_ui_zeroext:
; RV32IDZFH: # %bb.0:
@@ -346,15 +316,10 @@ define half @fcvt_h_ui_zeroext(i16 zeroext %a) nounwind strictfp {
}
define half @fcvt_h_w(i32 %a) nounwind strictfp {
-; RV32IZFH-LABEL: fcvt_h_w:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: fcvt.h.w fa0, a0
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: fcvt_h_w:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fcvt.h.w fa0, a0
-; RV64IZFH-NEXT: ret
+; CHECKIZFH-LABEL: fcvt_h_w:
+; CHECKIZFH: # %bb.0:
+; CHECKIZFH-NEXT: fcvt.h.w fa0, a0
+; CHECKIZFH-NEXT: ret
;
; RV32IDZFH-LABEL: fcvt_h_w:
; RV32IDZFH: # %bb.0:
@@ -371,17 +336,11 @@ define half @fcvt_h_w(i32 %a) nounwind strictfp {
declare half @llvm.experimental.constrained.sitofp.f16.i32(i32, metadata, metadata)
define half @fcvt_h_w_load(i32* %p) nounwind strictfp {
-; RV32IZFH-LABEL: fcvt_h_w_load:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: lw a0, 0(a0)
-; RV32IZFH-NEXT: fcvt.h.w fa0, a0
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: fcvt_h_w_load:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: lw a0, 0(a0)
-; RV64IZFH-NEXT: fcvt.h.w fa0, a0
-; RV64IZFH-NEXT: ret
+; CHECKIZFH-LABEL: fcvt_h_w_load:
+; CHECKIZFH: # %bb.0:
+; CHECKIZFH-NEXT: lw a0, 0(a0)
+; CHECKIZFH-NEXT: fcvt.h.w fa0, a0
+; CHECKIZFH-NEXT: ret
;
; RV32IDZFH-LABEL: fcvt_h_w_load:
; RV32IDZFH: # %bb.0:
@@ -400,15 +359,10 @@ define half @fcvt_h_w_load(i32* %p) nounwind strictfp {
}
define half @fcvt_h_wu(i32 %a) nounwind strictfp {
-; RV32IZFH-LABEL: fcvt_h_wu:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: fcvt.h.wu fa0, a0
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: fcvt_h_wu:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fcvt.h.wu fa0, a0
-; RV64IZFH-NEXT: ret
+; CHECKIZFH-LABEL: fcvt_h_wu:
+; CHECKIZFH: # %bb.0:
+; CHECKIZFH-NEXT: fcvt.h.wu fa0, a0
+; CHECKIZFH-NEXT: ret
;
; RV32IDZFH-LABEL: fcvt_h_wu:
; RV32IDZFH: # %bb.0:
@@ -520,15 +474,10 @@ define half @fcvt_h_lu(i64 %a) nounwind strictfp {
declare half @llvm.experimental.constrained.uitofp.f16.i64(i64, metadata, metadata)
define half @fcvt_h_s(float %a) nounwind strictfp {
-; RV32IZFH-LABEL: fcvt_h_s:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: fcvt.h.s fa0, fa0
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: fcvt_h_s:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fcvt.h.s fa0, fa0
-; RV64IZFH-NEXT: ret
+; CHECKIZFH-LABEL: fcvt_h_s:
+; CHECKIZFH: # %bb.0:
+; CHECKIZFH-NEXT: fcvt.h.s fa0, fa0
+; CHECKIZFH-NEXT: ret
;
; RV32IDZFH-LABEL: fcvt_h_s:
; RV32IDZFH: # %bb.0:
@@ -545,15 +494,10 @@ define half @fcvt_h_s(float %a) nounwind strictfp {
declare half @llvm.experimental.constrained.fptrunc.f16.f32(float, metadata, metadata)
define float @fcvt_s_h(half %a) nounwind strictfp {
-; RV32IZFH-LABEL: fcvt_s_h:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: fcvt_s_h:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fcvt.s.h fa0, fa0
-; RV64IZFH-NEXT: ret
+; CHECKIZFH-LABEL: fcvt_s_h:
+; CHECKIZFH: # %bb.0:
+; CHECKIZFH-NEXT: fcvt.s.h fa0, fa0
+; CHECKIZFH-NEXT: ret
;
; RV32IDZFH-LABEL: fcvt_s_h:
; RV32IDZFH: # %bb.0:
diff --git a/llvm/test/CodeGen/RISCV/half-convert.ll b/llvm/test/CodeGen/RISCV/half-convert.ll
index a862c9733d95..debdc8531011 100644
--- a/llvm/test/CodeGen/RISCV/half-convert.ll
+++ b/llvm/test/CodeGen/RISCV/half-convert.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs \
-; RUN: -target-abi ilp32f < %s | FileCheck -check-prefix=RV32IZFH %s
+; RUN: -target-abi ilp32f < %s | FileCheck -check-prefixes=CHECKIZFH,RV32IZFH %s
; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs \
-; RUN: -target-abi lp64f < %s | FileCheck -check-prefix=RV64IZFH %s
+; RUN: -target-abi lp64f < %s | FileCheck -check-prefixes=CHECKIZFH,RV64IZFH %s
; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh -verify-machineinstrs \
; RUN: -target-abi ilp32d < %s | FileCheck -check-prefix=RV32IDZFH %s
; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh -verify-machineinstrs \
@@ -405,15 +405,10 @@ start:
declare i16 @llvm.fptoui.sat.i16.f16(half)
define i32 @fcvt_w_h(half %a) nounwind {
-; RV32IZFH-LABEL: fcvt_w_h:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rtz
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: fcvt_w_h:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fcvt.w.h a0, fa0, rtz
-; RV64IZFH-NEXT: ret
+; CHECKIZFH-LABEL: fcvt_w_h:
+; CHECKIZFH: # %bb.0:
+; CHECKIZFH-NEXT: fcvt.w.h a0, fa0, rtz
+; CHECKIZFH-NEXT: ret
;
; RV32IDZFH-LABEL: fcvt_w_h:
; RV32IDZFH: # %bb.0:
@@ -453,23 +448,14 @@ define i32 @fcvt_w_h(half %a) nounwind {
}
define i32 @fcvt_w_h_sat(half %a) nounwind {
-; RV32IZFH-LABEL: fcvt_w_h_sat:
-; RV32IZFH: # %bb.0: # %start
-; RV32IZFH-NEXT: feq.h a0, fa0, fa0
-; RV32IZFH-NEXT: beqz a0, .LBB5_2
-; RV32IZFH-NEXT: # %bb.1:
-; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rtz
-; RV32IZFH-NEXT: .LBB5_2: # %start
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: fcvt_w_h_sat:
-; RV64IZFH: # %bb.0: # %start
-; RV64IZFH-NEXT: feq.h a0, fa0, fa0
-; RV64IZFH-NEXT: beqz a0, .LBB5_2
-; RV64IZFH-NEXT: # %bb.1:
-; RV64IZFH-NEXT: fcvt.w.h a0, fa0, rtz
-; RV64IZFH-NEXT: .LBB5_2: # %start
-; RV64IZFH-NEXT: ret
+; CHECKIZFH-LABEL: fcvt_w_h_sat:
+; CHECKIZFH: # %bb.0: # %start
+; CHECKIZFH-NEXT: feq.h a0, fa0, fa0
+; CHECKIZFH-NEXT: beqz a0, .LBB5_2
+; CHECKIZFH-NEXT: # %bb.1:
+; CHECKIZFH-NEXT: fcvt.w.h a0, fa0, rtz
+; CHECKIZFH-NEXT: .LBB5_2: # %start
+; CHECKIZFH-NEXT: ret
;
; RV32IDZFH-LABEL: fcvt_w_h_sat:
; RV32IDZFH: # %bb.0: # %start
@@ -595,15 +581,10 @@ start:
declare i32 @llvm.fptosi.sat.i32.f16(half)
define i32 @fcvt_wu_h(half %a) nounwind {
-; RV32IZFH-LABEL: fcvt_wu_h:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: fcvt.wu.h a0, fa0, rtz
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: fcvt_wu_h:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fcvt.wu.h a0, fa0, rtz
-; RV64IZFH-NEXT: ret
+; CHECKIZFH-LABEL: fcvt_wu_h:
+; CHECKIZFH: # %bb.0:
+; CHECKIZFH-NEXT: fcvt.wu.h a0, fa0, rtz
+; CHECKIZFH-NEXT: ret
;
; RV32IDZFH-LABEL: fcvt_wu_h:
; RV32IDZFH: # %bb.0:
@@ -645,25 +626,15 @@ define i32 @fcvt_wu_h(half %a) nounwind {
; Test where the fptoui has multiple uses, one of which causes a sext to be
; inserted on RV64.
define i32 @fcvt_wu_h_multiple_use(half %x, i32* %y) nounwind {
-; RV32IZFH-LABEL: fcvt_wu_h_multiple_use:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: fcvt.wu.h a1, fa0, rtz
-; RV32IZFH-NEXT: li a0, 1
-; RV32IZFH-NEXT: beqz a1, .LBB7_2
-; RV32IZFH-NEXT: # %bb.1:
-; RV32IZFH-NEXT: mv a0, a1
-; RV32IZFH-NEXT: .LBB7_2:
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: fcvt_wu_h_multiple_use:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fcvt.wu.h a1, fa0, rtz
-; RV64IZFH-NEXT: li a0, 1
-; RV64IZFH-NEXT: beqz a1, .LBB7_2
-; RV64IZFH-NEXT: # %bb.1:
-; RV64IZFH-NEXT: mv a0, a1
-; RV64IZFH-NEXT: .LBB7_2:
-; RV64IZFH-NEXT: ret
+; CHECKIZFH-LABEL: fcvt_wu_h_multiple_use:
+; CHECKIZFH: # %bb.0:
+; CHECKIZFH-NEXT: fcvt.wu.h a1, fa0, rtz
+; CHECKIZFH-NEXT: li a0, 1
+; CHECKIZFH-NEXT: beqz a1, .LBB7_2
+; CHECKIZFH-NEXT: # %bb.1:
+; CHECKIZFH-NEXT: mv a0, a1
+; CHECKIZFH-NEXT: .LBB7_2:
+; CHECKIZFH-NEXT: ret
;
; RV32IDZFH-LABEL: fcvt_wu_h_multiple_use:
; RV32IDZFH: # %bb.0:
@@ -727,23 +698,14 @@ define i32 @fcvt_wu_h_multiple_use(half %x, i32* %y) nounwind {
}
define i32 @fcvt_wu_h_sat(half %a) nounwind {
-; RV32IZFH-LABEL: fcvt_wu_h_sat:
-; RV32IZFH: # %bb.0: # %start
-; RV32IZFH-NEXT: feq.h a0, fa0, fa0
-; RV32IZFH-NEXT: beqz a0, .LBB8_2
-; RV32IZFH-NEXT: # %bb.1:
-; RV32IZFH-NEXT: fcvt.wu.h a0, fa0, rtz
-; RV32IZFH-NEXT: .LBB8_2: # %start
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: fcvt_wu_h_sat:
-; RV64IZFH: # %bb.0: # %start
-; RV64IZFH-NEXT: feq.h a0, fa0, fa0
-; RV64IZFH-NEXT: beqz a0, .LBB8_2
-; RV64IZFH-NEXT: # %bb.1:
-; RV64IZFH-NEXT: fcvt.wu.h a0, fa0, rtz
-; RV64IZFH-NEXT: .LBB8_2: # %start
-; RV64IZFH-NEXT: ret
+; CHECKIZFH-LABEL: fcvt_wu_h_sat:
+; CHECKIZFH: # %bb.0: # %start
+; CHECKIZFH-NEXT: feq.h a0, fa0, fa0
+; CHECKIZFH-NEXT: beqz a0, .LBB8_2
+; CHECKIZFH-NEXT: # %bb.1:
+; CHECKIZFH-NEXT: fcvt.wu.h a0, fa0, rtz
+; CHECKIZFH-NEXT: .LBB8_2: # %start
+; CHECKIZFH-NEXT: ret
;
; RV32IDZFH-LABEL: fcvt_wu_h_sat:
; RV32IDZFH: # %bb.0: # %start
@@ -1493,15 +1455,10 @@ define half @fcvt_h_si(i16 %a) nounwind {
}
define half @fcvt_h_si_signext(i16 signext %a) nounwind {
-; RV32IZFH-LABEL: fcvt_h_si_signext:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: fcvt.h.w fa0, a0
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: fcvt_h_si_signext:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fcvt.h.w fa0, a0
-; RV64IZFH-NEXT: ret
+; CHECKIZFH-LABEL: fcvt_h_si_signext:
+; CHECKIZFH: # %bb.0:
+; CHECKIZFH-NEXT: fcvt.h.w fa0, a0
+; CHECKIZFH-NEXT: ret
;
; RV32IDZFH-LABEL: fcvt_h_si_signext:
; RV32IDZFH: # %bb.0:
@@ -1593,15 +1550,10 @@ define half @fcvt_h_ui(i16 %a) nounwind {
}
define half @fcvt_h_ui_zeroext(i16 zeroext %a) nounwind {
-; RV32IZFH-LABEL: fcvt_h_ui_zeroext:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: fcvt.h.wu fa0, a0
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: fcvt_h_ui_zeroext:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fcvt.h.wu fa0, a0
-; RV64IZFH-NEXT: ret
+; CHECKIZFH-LABEL: fcvt_h_ui_zeroext:
+; CHECKIZFH: # %bb.0:
+; CHECKIZFH-NEXT: fcvt.h.wu fa0, a0
+; CHECKIZFH-NEXT: ret
;
; RV32IDZFH-LABEL: fcvt_h_ui_zeroext:
; RV32IDZFH: # %bb.0:
@@ -1637,15 +1589,10 @@ define half @fcvt_h_ui_zeroext(i16 zeroext %a) nounwind {
}
define half @fcvt_h_w(i32 %a) nounwind {
-; RV32IZFH-LABEL: fcvt_h_w:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: fcvt.h.w fa0, a0
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: fcvt_h_w:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fcvt.h.w fa0, a0
-; RV64IZFH-NEXT: ret
+; CHECKIZFH-LABEL: fcvt_h_w:
+; CHECKIZFH: # %bb.0:
+; CHECKIZFH-NEXT: fcvt.h.w fa0, a0
+; CHECKIZFH-NEXT: ret
;
; RV32IDZFH-LABEL: fcvt_h_w:
; RV32IDZFH: # %bb.0:
@@ -1682,17 +1629,11 @@ define half @fcvt_h_w(i32 %a) nounwind {
}
define half @fcvt_h_w_load(i32* %p) nounwind {
-; RV32IZFH-LABEL: fcvt_h_w_load:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: lw a0, 0(a0)
-; RV32IZFH-NEXT: fcvt.h.w fa0, a0
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: fcvt_h_w_load:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: lw a0, 0(a0)
-; RV64IZFH-NEXT: fcvt.h.w fa0, a0
-; RV64IZFH-NEXT: ret
+; CHECKIZFH-LABEL: fcvt_h_w_load:
+; CHECKIZFH: # %bb.0:
+; CHECKIZFH-NEXT: lw a0, 0(a0)
+; CHECKIZFH-NEXT: fcvt.h.w fa0, a0
+; CHECKIZFH-NEXT: ret
;
; RV32IDZFH-LABEL: fcvt_h_w_load:
; RV32IDZFH: # %bb.0:
@@ -1733,15 +1674,10 @@ define half @fcvt_h_w_load(i32* %p) nounwind {
}
define half @fcvt_h_wu(i32 %a) nounwind {
-; RV32IZFH-LABEL: fcvt_h_wu:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: fcvt.h.wu fa0, a0
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: fcvt_h_wu:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fcvt.h.wu fa0, a0
-; RV64IZFH-NEXT: ret
+; CHECKIZFH-LABEL: fcvt_h_wu:
+; CHECKIZFH: # %bb.0:
+; CHECKIZFH-NEXT: fcvt.h.wu fa0, a0
+; CHECKIZFH-NEXT: ret
;
; RV32IDZFH-LABEL: fcvt_h_wu:
; RV32IDZFH: # %bb.0:
@@ -1933,15 +1869,10 @@ define half @fcvt_h_lu(i64 %a) nounwind {
}
define half @fcvt_h_s(float %a) nounwind {
-; RV32IZFH-LABEL: fcvt_h_s:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: fcvt.h.s fa0, fa0
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: fcvt_h_s:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fcvt.h.s fa0, fa0
-; RV64IZFH-NEXT: ret
+; CHECKIZFH-LABEL: fcvt_h_s:
+; CHECKIZFH: # %bb.0:
+; CHECKIZFH-NEXT: fcvt.h.s fa0, fa0
+; CHECKIZFH-NEXT: ret
;
; RV32IDZFH-LABEL: fcvt_h_s:
; RV32IDZFH: # %bb.0:
@@ -1975,15 +1906,10 @@ define half @fcvt_h_s(float %a) nounwind {
}
define float @fcvt_s_h(half %a) nounwind {
-; RV32IZFH-LABEL: fcvt_s_h:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: fcvt_s_h:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fcvt.s.h fa0, fa0
-; RV64IZFH-NEXT: ret
+; CHECKIZFH-LABEL: fcvt_s_h:
+; CHECKIZFH: # %bb.0:
+; CHECKIZFH-NEXT: fcvt.s.h fa0, fa0
+; CHECKIZFH-NEXT: ret
;
; RV32IDZFH-LABEL: fcvt_s_h:
; RV32IDZFH: # %bb.0:
@@ -2131,15 +2057,10 @@ define double @fcvt_d_h(half %a) nounwind {
}
define half @bitcast_h_i16(i16 %a) nounwind {
-; RV32IZFH-LABEL: bitcast_h_i16:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: fmv.h.x fa0, a0
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: bitcast_h_i16:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fmv.h.x fa0, a0
-; RV64IZFH-NEXT: ret
+; CHECKIZFH-LABEL: bitcast_h_i16:
+; CHECKIZFH: # %bb.0:
+; CHECKIZFH-NEXT: fmv.h.x fa0, a0
+; CHECKIZFH-NEXT: ret
;
; RV32IDZFH-LABEL: bitcast_h_i16:
; RV32IDZFH: # %bb.0:
@@ -2163,15 +2084,10 @@ define half @bitcast_h_i16(i16 %a) nounwind {
}
define i16 @bitcast_i16_h(half %a) nounwind {
-; RV32IZFH-LABEL: bitcast_i16_h:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: fmv.x.h a0, fa0
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: bitcast_i16_h:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fmv.x.h a0, fa0
-; RV64IZFH-NEXT: ret
+; CHECKIZFH-LABEL: bitcast_i16_h:
+; CHECKIZFH: # %bb.0:
+; CHECKIZFH-NEXT: fmv.x.h a0, fa0
+; CHECKIZFH-NEXT: ret
;
; RV32IDZFH-LABEL: bitcast_i16_h:
; RV32IDZFH: # %bb.0:
diff --git a/llvm/test/CodeGen/RISCV/half-fcmp-strict.ll b/llvm/test/CodeGen/RISCV/half-fcmp-strict.ll
index e2a8ac4b49e7..f048a9c67761 100644
--- a/llvm/test/CodeGen/RISCV/half-fcmp-strict.ll
+++ b/llvm/test/CodeGen/RISCV/half-fcmp-strict.ll
@@ -1,21 +1,14 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs \
-; RUN: -target-abi ilp32f -disable-strictnode-mutation < %s \
-; RUN: | FileCheck -check-prefix=RV32IZFH %s
+; RUN: -target-abi ilp32f -disable-strictnode-mutation < %s | FileCheck %s
; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs \
-; RUN: -target-abi lp64f -disable-strictnode-mutation < %s \
-; RUN: | FileCheck -check-prefix=RV64IZFH %s
+; RUN: -target-abi lp64f -disable-strictnode-mutation < %s | FileCheck %s
define i32 @fcmp_oeq(half %a, half %b) nounwind strictfp {
-; RV32IZFH-LABEL: fcmp_oeq:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: feq.h a0, fa0, fa1
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: fcmp_oeq:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: feq.h a0, fa0, fa1
-; RV64IZFH-NEXT: ret
+; CHECK-LABEL: fcmp_oeq:
+; CHECK: # %bb.0:
+; CHECK-NEXT: feq.h a0, fa0, fa1
+; CHECK-NEXT: ret
%1 = call i1 @llvm.experimental.constrained.fcmp.f16(half %a, half %b, metadata !"oeq", metadata !"fpexcept.strict") strictfp
%2 = zext i1 %1 to i32
ret i32 %2
@@ -23,84 +16,52 @@ define i32 @fcmp_oeq(half %a, half %b) nounwind strictfp {
declare i1 @llvm.experimental.constrained.fcmp.f16(half, half, metadata, metadata)
define i32 @fcmp_ogt(half %a, half %b) nounwind strictfp {
-; RV32IZFH-LABEL: fcmp_ogt:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: frflags a1
-; RV32IZFH-NEXT: flt.h a0, fa1, fa0
-; RV32IZFH-NEXT: fsflags a1
-; RV32IZFH-NEXT: feq.h zero, fa1, fa0
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: fcmp_ogt:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: frflags a1
-; RV64IZFH-NEXT: flt.h a0, fa1, fa0
-; RV64IZFH-NEXT: fsflags a1
-; RV64IZFH-NEXT: feq.h zero, fa1, fa0
-; RV64IZFH-NEXT: ret
+; CHECK-LABEL: fcmp_ogt:
+; CHECK: # %bb.0:
+; CHECK-NEXT: frflags a1
+; CHECK-NEXT: flt.h a0, fa1, fa0
+; CHECK-NEXT: fsflags a1
+; CHECK-NEXT: feq.h zero, fa1, fa0
+; CHECK-NEXT: ret
%1 = call i1 @llvm.experimental.constrained.fcmp.f16(half %a, half %b, metadata !"ogt", metadata !"fpexcept.strict") strictfp
%2 = zext i1 %1 to i32
ret i32 %2
}
define i32 @fcmp_oge(half %a, half %b) nounwind strictfp {
-; RV32IZFH-LABEL: fcmp_oge:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: frflags a1
-; RV32IZFH-NEXT: fle.h a0, fa1, fa0
-; RV32IZFH-NEXT: fsflags a1
-; RV32IZFH-NEXT: feq.h zero, fa1, fa0
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: fcmp_oge:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: frflags a1
-; RV64IZFH-NEXT: fle.h a0, fa1, fa0
-; RV64IZFH-NEXT: fsflags a1
-; RV64IZFH-NEXT: feq.h zero, fa1, fa0
-; RV64IZFH-NEXT: ret
+; CHECK-LABEL: fcmp_oge:
+; CHECK: # %bb.0:
+; CHECK-NEXT: frflags a1
+; CHECK-NEXT: fle.h a0, fa1, fa0
+; CHECK-NEXT: fsflags a1
+; CHECK-NEXT: feq.h zero, fa1, fa0
+; CHECK-NEXT: ret
%1 = call i1 @llvm.experimental.constrained.fcmp.f16(half %a, half %b, metadata !"oge", metadata !"fpexcept.strict") strictfp
%2 = zext i1 %1 to i32
ret i32 %2
}
define i32 @fcmp_olt(half %a, half %b) nounwind strictfp {
-; RV32IZFH-LABEL: fcmp_olt:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: frflags a1
-; RV32IZFH-NEXT: flt.h a0, fa0, fa1
-; RV32IZFH-NEXT: fsflags a1
-; RV32IZFH-NEXT: feq.h zero, fa0, fa1
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: fcmp_olt:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: frflags a1
-; RV64IZFH-NEXT: flt.h a0, fa0, fa1
-; RV64IZFH-NEXT: fsflags a1
-; RV64IZFH-NEXT: feq.h zero, fa0, fa1
-; RV64IZFH-NEXT: ret
+; CHECK-LABEL: fcmp_olt:
+; CHECK: # %bb.0:
+; CHECK-NEXT: frflags a1
+; CHECK-NEXT: flt.h a0, fa0, fa1
+; CHECK-NEXT: fsflags a1
+; CHECK-NEXT: feq.h zero, fa0, fa1
+; CHECK-NEXT: ret
%1 = call i1 @llvm.experimental.constrained.fcmp.f16(half %a, half %b, metadata !"olt", metadata !"fpexcept.strict") strictfp
%2 = zext i1 %1 to i32
ret i32 %2
}
define i32 @fcmp_ole(half %a, half %b) nounwind strictfp {
-; RV32IZFH-LABEL: fcmp_ole:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: frflags a1
-; RV32IZFH-NEXT: fle.h a0, fa0, fa1
-; RV32IZFH-NEXT: fsflags a1
-; RV32IZFH-NEXT: feq.h zero, fa0, fa1
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: fcmp_ole:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: frflags a1
-; RV64IZFH-NEXT: fle.h a0, fa0, fa1
-; RV64IZFH-NEXT: fsflags a1
-; RV64IZFH-NEXT: feq.h zero, fa0, fa1
-; RV64IZFH-NEXT: ret
+; CHECK-LABEL: fcmp_ole:
+; CHECK: # %bb.0:
+; CHECK-NEXT: frflags a1
+; CHECK-NEXT: fle.h a0, fa0, fa1
+; CHECK-NEXT: fsflags a1
+; CHECK-NEXT: feq.h zero, fa0, fa1
+; CHECK-NEXT: ret
%1 = call i1 @llvm.experimental.constrained.fcmp.f16(half %a, half %b, metadata !"ole", metadata !"fpexcept.strict") strictfp
%2 = zext i1 %1 to i32
ret i32 %2
@@ -109,50 +70,30 @@ define i32 @fcmp_ole(half %a, half %b) nounwind strictfp {
; FIXME: We only need one frflags before the two flts and one fsflags after the
; two flts.
define i32 @fcmp_one(half %a, half %b) nounwind strictfp {
-; RV32IZFH-LABEL: fcmp_one:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: frflags a0
-; RV32IZFH-NEXT: flt.h a1, fa0, fa1
-; RV32IZFH-NEXT: fsflags a0
-; RV32IZFH-NEXT: feq.h zero, fa0, fa1
-; RV32IZFH-NEXT: frflags a0
-; RV32IZFH-NEXT: flt.h a2, fa1, fa0
-; RV32IZFH-NEXT: fsflags a0
-; RV32IZFH-NEXT: or a0, a2, a1
-; RV32IZFH-NEXT: feq.h zero, fa1, fa0
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: fcmp_one:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: frflags a0
-; RV64IZFH-NEXT: flt.h a1, fa0, fa1
-; RV64IZFH-NEXT: fsflags a0
-; RV64IZFH-NEXT: feq.h zero, fa0, fa1
-; RV64IZFH-NEXT: frflags a0
-; RV64IZFH-NEXT: flt.h a2, fa1, fa0
-; RV64IZFH-NEXT: fsflags a0
-; RV64IZFH-NEXT: or a0, a2, a1
-; RV64IZFH-NEXT: feq.h zero, fa1, fa0
-; RV64IZFH-NEXT: ret
+; CHECK-LABEL: fcmp_one:
+; CHECK: # %bb.0:
+; CHECK-NEXT: frflags a0
+; CHECK-NEXT: flt.h a1, fa0, fa1
+; CHECK-NEXT: fsflags a0
+; CHECK-NEXT: feq.h zero, fa0, fa1
+; CHECK-NEXT: frflags a0
+; CHECK-NEXT: flt.h a2, fa1, fa0
+; CHECK-NEXT: fsflags a0
+; CHECK-NEXT: or a0, a2, a1
+; CHECK-NEXT: feq.h zero, fa1, fa0
+; CHECK-NEXT: ret
%1 = call i1 @llvm.experimental.constrained.fcmp.f16(half %a, half %b, metadata !"one", metadata !"fpexcept.strict") strictfp
%2 = zext i1 %1 to i32
ret i32 %2
}
define i32 @fcmp_ord(half %a, half %b) nounwind strictfp {
-; RV32IZFH-LABEL: fcmp_ord:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: feq.h a0, fa1, fa1
-; RV32IZFH-NEXT: feq.h a1, fa0, fa0
-; RV32IZFH-NEXT: and a0, a1, a0
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: fcmp_ord:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: feq.h a0, fa1, fa1
-; RV64IZFH-NEXT: feq.h a1, fa0, fa0
-; RV64IZFH-NEXT: and a0, a1, a0
-; RV64IZFH-NEXT: ret
+; CHECK-LABEL: fcmp_ord:
+; CHECK: # %bb.0:
+; CHECK-NEXT: feq.h a0, fa1, fa1
+; CHECK-NEXT: feq.h a1, fa0, fa0
+; CHECK-NEXT: and a0, a1, a0
+; CHECK-NEXT: ret
%1 = call i1 @llvm.experimental.constrained.fcmp.f16(half %a, half %b, metadata !"ord", metadata !"fpexcept.strict") strictfp
%2 = zext i1 %1 to i32
ret i32 %2
@@ -161,182 +102,111 @@ define i32 @fcmp_ord(half %a, half %b) nounwind strictfp {
; FIXME: We only need one frflags before the two flts and one fsflags after the
; two flts.
define i32 @fcmp_ueq(half %a, half %b) nounwind strictfp {
-; RV32IZFH-LABEL: fcmp_ueq:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: frflags a0
-; RV32IZFH-NEXT: flt.h a1, fa0, fa1
-; RV32IZFH-NEXT: fsflags a0
-; RV32IZFH-NEXT: feq.h zero, fa0, fa1
-; RV32IZFH-NEXT: frflags a0
-; RV32IZFH-NEXT: flt.h a2, fa1, fa0
-; RV32IZFH-NEXT: fsflags a0
-; RV32IZFH-NEXT: or a0, a2, a1
-; RV32IZFH-NEXT: xori a0, a0, 1
-; RV32IZFH-NEXT: feq.h zero, fa1, fa0
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: fcmp_ueq:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: frflags a0
-; RV64IZFH-NEXT: flt.h a1, fa0, fa1
-; RV64IZFH-NEXT: fsflags a0
-; RV64IZFH-NEXT: feq.h zero, fa0, fa1
-; RV64IZFH-NEXT: frflags a0
-; RV64IZFH-NEXT: flt.h a2, fa1, fa0
-; RV64IZFH-NEXT: fsflags a0
-; RV64IZFH-NEXT: or a0, a2, a1
-; RV64IZFH-NEXT: xori a0, a0, 1
-; RV64IZFH-NEXT: feq.h zero, fa1, fa0
-; RV64IZFH-NEXT: ret
+; CHECK-LABEL: fcmp_ueq:
+; CHECK: # %bb.0:
+; CHECK-NEXT: frflags a0
+; CHECK-NEXT: flt.h a1, fa0, fa1
+; CHECK-NEXT: fsflags a0
+; CHECK-NEXT: feq.h zero, fa0, fa1
+; CHECK-NEXT: frflags a0
+; CHECK-NEXT: flt.h a2, fa1, fa0
+; CHECK-NEXT: fsflags a0
+; CHECK-NEXT: or a0, a2, a1
+; CHECK-NEXT: xori a0, a0, 1
+; CHECK-NEXT: feq.h zero, fa1, fa0
+; CHECK-NEXT: ret
%1 = call i1 @llvm.experimental.constrained.fcmp.f16(half %a, half %b, metadata !"ueq", metadata !"fpexcept.strict") strictfp
%2 = zext i1 %1 to i32
ret i32 %2
}
define i32 @fcmp_ugt(half %a, half %b) nounwind strictfp {
-; RV32IZFH-LABEL: fcmp_ugt:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: frflags a0
-; RV32IZFH-NEXT: fle.h a1, fa0, fa1
-; RV32IZFH-NEXT: fsflags a0
-; RV32IZFH-NEXT: xori a0, a1, 1
-; RV32IZFH-NEXT: feq.h zero, fa0, fa1
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: fcmp_ugt:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: frflags a0
-; RV64IZFH-NEXT: fle.h a1, fa0, fa1
-; RV64IZFH-NEXT: fsflags a0
-; RV64IZFH-NEXT: xori a0, a1, 1
-; RV64IZFH-NEXT: feq.h zero, fa0, fa1
-; RV64IZFH-NEXT: ret
+; CHECK-LABEL: fcmp_ugt:
+; CHECK: # %bb.0:
+; CHECK-NEXT: frflags a0
+; CHECK-NEXT: fle.h a1, fa0, fa1
+; CHECK-NEXT: fsflags a0
+; CHECK-NEXT: xori a0, a1, 1
+; CHECK-NEXT: feq.h zero, fa0, fa1
+; CHECK-NEXT: ret
%1 = call i1 @llvm.experimental.constrained.fcmp.f16(half %a, half %b, metadata !"ugt", metadata !"fpexcept.strict") strictfp
%2 = zext i1 %1 to i32
ret i32 %2
}
define i32 @fcmp_uge(half %a, half %b) nounwind strictfp {
-; RV32IZFH-LABEL: fcmp_uge:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: frflags a0
-; RV32IZFH-NEXT: flt.h a1, fa0, fa1
-; RV32IZFH-NEXT: fsflags a0
-; RV32IZFH-NEXT: xori a0, a1, 1
-; RV32IZFH-NEXT: feq.h zero, fa0, fa1
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: fcmp_uge:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: frflags a0
-; RV64IZFH-NEXT: flt.h a1, fa0, fa1
-; RV64IZFH-NEXT: fsflags a0
-; RV64IZFH-NEXT: xori a0, a1, 1
-; RV64IZFH-NEXT: feq.h zero, fa0, fa1
-; RV64IZFH-NEXT: ret
+; CHECK-LABEL: fcmp_uge:
+; CHECK: # %bb.0:
+; CHECK-NEXT: frflags a0
+; CHECK-NEXT: flt.h a1, fa0, fa1
+; CHECK-NEXT: fsflags a0
+; CHECK-NEXT: xori a0, a1, 1
+; CHECK-NEXT: feq.h zero, fa0, fa1
+; CHECK-NEXT: ret
%1 = call i1 @llvm.experimental.constrained.fcmp.f16(half %a, half %b, metadata !"uge", metadata !"fpexcept.strict") strictfp
%2 = zext i1 %1 to i32
ret i32 %2
}
define i32 @fcmp_ult(half %a, half %b) nounwind strictfp {
-; RV32IZFH-LABEL: fcmp_ult:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: frflags a0
-; RV32IZFH-NEXT: fle.h a1, fa1, fa0
-; RV32IZFH-NEXT: fsflags a0
-; RV32IZFH-NEXT: xori a0, a1, 1
-; RV32IZFH-NEXT: feq.h zero, fa1, fa0
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: fcmp_ult:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: frflags a0
-; RV64IZFH-NEXT: fle.h a1, fa1, fa0
-; RV64IZFH-NEXT: fsflags a0
-; RV64IZFH-NEXT: xori a0, a1, 1
-; RV64IZFH-NEXT: feq.h zero, fa1, fa0
-; RV64IZFH-NEXT: ret
+; CHECK-LABEL: fcmp_ult:
+; CHECK: # %bb.0:
+; CHECK-NEXT: frflags a0
+; CHECK-NEXT: fle.h a1, fa1, fa0
+; CHECK-NEXT: fsflags a0
+; CHECK-NEXT: xori a0, a1, 1
+; CHECK-NEXT: feq.h zero, fa1, fa0
+; CHECK-NEXT: ret
%1 = call i1 @llvm.experimental.constrained.fcmp.f16(half %a, half %b, metadata !"ult", metadata !"fpexcept.strict") strictfp
%2 = zext i1 %1 to i32
ret i32 %2
}
define i32 @fcmp_ule(half %a, half %b) nounwind strictfp {
-; RV32IZFH-LABEL: fcmp_ule:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: frflags a0
-; RV32IZFH-NEXT: flt.h a1, fa1, fa0
-; RV32IZFH-NEXT: fsflags a0
-; RV32IZFH-NEXT: xori a0, a1, 1
-; RV32IZFH-NEXT: feq.h zero, fa1, fa0
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: fcmp_ule:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: frflags a0
-; RV64IZFH-NEXT: flt.h a1, fa1, fa0
-; RV64IZFH-NEXT: fsflags a0
-; RV64IZFH-NEXT: xori a0, a1, 1
-; RV64IZFH-NEXT: feq.h zero, fa1, fa0
-; RV64IZFH-NEXT: ret
+; CHECK-LABEL: fcmp_ule:
+; CHECK: # %bb.0:
+; CHECK-NEXT: frflags a0
+; CHECK-NEXT: flt.h a1, fa1, fa0
+; CHECK-NEXT: fsflags a0
+; CHECK-NEXT: xori a0, a1, 1
+; CHECK-NEXT: feq.h zero, fa1, fa0
+; CHECK-NEXT: ret
%1 = call i1 @llvm.experimental.constrained.fcmp.f16(half %a, half %b, metadata !"ule", metadata !"fpexcept.strict") strictfp
%2 = zext i1 %1 to i32
ret i32 %2
}
define i32 @fcmp_une(half %a, half %b) nounwind strictfp {
-; RV32IZFH-LABEL: fcmp_une:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: feq.h a0, fa0, fa1
-; RV32IZFH-NEXT: xori a0, a0, 1
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: fcmp_une:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: feq.h a0, fa0, fa1
-; RV64IZFH-NEXT: xori a0, a0, 1
-; RV64IZFH-NEXT: ret
+; CHECK-LABEL: fcmp_une:
+; CHECK: # %bb.0:
+; CHECK-NEXT: feq.h a0, fa0, fa1
+; CHECK-NEXT: xori a0, a0, 1
+; CHECK-NEXT: ret
%1 = call i1 @llvm.experimental.constrained.fcmp.f16(half %a, half %b, metadata !"une", metadata !"fpexcept.strict") strictfp
%2 = zext i1 %1 to i32
ret i32 %2
}
define i32 @fcmp_uno(half %a, half %b) nounwind strictfp {
-; RV32IZFH-LABEL: fcmp_uno:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: feq.h a0, fa1, fa1
-; RV32IZFH-NEXT: feq.h a1, fa0, fa0
-; RV32IZFH-NEXT: and a0, a1, a0
-; RV32IZFH-NEXT: xori a0, a0, 1
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: fcmp_uno:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: feq.h a0, fa1, fa1
-; RV64IZFH-NEXT: feq.h a1, fa0, fa0
-; RV64IZFH-NEXT: and a0, a1, a0
-; RV64IZFH-NEXT: xori a0, a0, 1
-; RV64IZFH-NEXT: ret
+; CHECK-LABEL: fcmp_uno:
+; CHECK: # %bb.0:
+; CHECK-NEXT: feq.h a0, fa1, fa1
+; CHECK-NEXT: feq.h a1, fa0, fa0
+; CHECK-NEXT: and a0, a1, a0
+; CHECK-NEXT: xori a0, a0, 1
+; CHECK-NEXT: ret
%1 = call i1 @llvm.experimental.constrained.fcmp.f16(half %a, half %b, metadata !"uno", metadata !"fpexcept.strict") strictfp
%2 = zext i1 %1 to i32
ret i32 %2
}
define i32 @fcmps_oeq(half %a, half %b) nounwind strictfp {
-; RV32IZFH-LABEL: fcmps_oeq:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: fle.h a0, fa1, fa0
-; RV32IZFH-NEXT: fle.h a1, fa0, fa1
-; RV32IZFH-NEXT: and a0, a1, a0
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: fcmps_oeq:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fle.h a0, fa1, fa0
-; RV64IZFH-NEXT: fle.h a1, fa0, fa1
-; RV64IZFH-NEXT: and a0, a1, a0
-; RV64IZFH-NEXT: ret
+; CHECK-LABEL: fcmps_oeq:
+; CHECK: # %bb.0:
+; CHECK-NEXT: fle.h a0, fa1, fa0
+; CHECK-NEXT: fle.h a1, fa0, fa1
+; CHECK-NEXT: and a0, a1, a0
+; CHECK-NEXT: ret
%1 = call i1 @llvm.experimental.constrained.fcmps.f16(half %a, half %b, metadata !"oeq", metadata !"fpexcept.strict") strictfp
%2 = zext i1 %1 to i32
ret i32 %2
@@ -344,229 +214,147 @@ define i32 @fcmps_oeq(half %a, half %b) nounwind strictfp {
declare i1 @llvm.experimental.constrained.fcmps.f16(half, half, metadata, metadata)
define i32 @fcmps_ogt(half %a, half %b) nounwind strictfp {
-; RV32IZFH-LABEL: fcmps_ogt:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: flt.h a0, fa1, fa0
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: fcmps_ogt:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: flt.h a0, fa1, fa0
-; RV64IZFH-NEXT: ret
+; CHECK-LABEL: fcmps_ogt:
+; CHECK: # %bb.0:
+; CHECK-NEXT: flt.h a0, fa1, fa0
+; CHECK-NEXT: ret
%1 = call i1 @llvm.experimental.constrained.fcmps.f16(half %a, half %b, metadata !"ogt", metadata !"fpexcept.strict") strictfp
%2 = zext i1 %1 to i32
ret i32 %2
}
define i32 @fcmps_oge(half %a, half %b) nounwind strictfp {
-; RV32IZFH-LABEL: fcmps_oge:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: fle.h a0, fa1, fa0
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: fcmps_oge:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fle.h a0, fa1, fa0
-; RV64IZFH-NEXT: ret
+; CHECK-LABEL: fcmps_oge:
+; CHECK: # %bb.0:
+; CHECK-NEXT: fle.h a0, fa1, fa0
+; CHECK-NEXT: ret
%1 = call i1 @llvm.experimental.constrained.fcmps.f16(half %a, half %b, metadata !"oge", metadata !"fpexcept.strict") strictfp
%2 = zext i1 %1 to i32
ret i32 %2
}
define i32 @fcmps_olt(half %a, half %b) nounwind strictfp {
-; RV32IZFH-LABEL: fcmps_olt:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: flt.h a0, fa0, fa1
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: fcmps_olt:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: flt.h a0, fa0, fa1
-; RV64IZFH-NEXT: ret
+; CHECK-LABEL: fcmps_olt:
+; CHECK: # %bb.0:
+; CHECK-NEXT: flt.h a0, fa0, fa1
+; CHECK-NEXT: ret
%1 = call i1 @llvm.experimental.constrained.fcmps.f16(half %a, half %b, metadata !"olt", metadata !"fpexcept.strict") strictfp
%2 = zext i1 %1 to i32
ret i32 %2
}
define i32 @fcmps_ole(half %a, half %b) nounwind strictfp {
-; RV32IZFH-LABEL: fcmps_ole:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: fle.h a0, fa0, fa1
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: fcmps_ole:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fle.h a0, fa0, fa1
-; RV64IZFH-NEXT: ret
+; CHECK-LABEL: fcmps_ole:
+; CHECK: # %bb.0:
+; CHECK-NEXT: fle.h a0, fa0, fa1
+; CHECK-NEXT: ret
%1 = call i1 @llvm.experimental.constrained.fcmps.f16(half %a, half %b, metadata !"ole", metadata !"fpexcept.strict") strictfp
%2 = zext i1 %1 to i32
ret i32 %2
}
define i32 @fcmps_one(half %a, half %b) nounwind strictfp {
-; RV32IZFH-LABEL: fcmps_one:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: flt.h a0, fa0, fa1
-; RV32IZFH-NEXT: flt.h a1, fa1, fa0
-; RV32IZFH-NEXT: or a0, a1, a0
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: fcmps_one:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: flt.h a0, fa0, fa1
-; RV64IZFH-NEXT: flt.h a1, fa1, fa0
-; RV64IZFH-NEXT: or a0, a1, a0
-; RV64IZFH-NEXT: ret
+; CHECK-LABEL: fcmps_one:
+; CHECK: # %bb.0:
+; CHECK-NEXT: flt.h a0, fa0, fa1
+; CHECK-NEXT: flt.h a1, fa1, fa0
+; CHECK-NEXT: or a0, a1, a0
+; CHECK-NEXT: ret
%1 = call i1 @llvm.experimental.constrained.fcmps.f16(half %a, half %b, metadata !"one", metadata !"fpexcept.strict") strictfp
%2 = zext i1 %1 to i32
ret i32 %2
}
define i32 @fcmps_ord(half %a, half %b) nounwind strictfp {
-; RV32IZFH-LABEL: fcmps_ord:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: fle.h a0, fa1, fa1
-; RV32IZFH-NEXT: fle.h a1, fa0, fa0
-; RV32IZFH-NEXT: and a0, a1, a0
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: fcmps_ord:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fle.h a0, fa1, fa1
-; RV64IZFH-NEXT: fle.h a1, fa0, fa0
-; RV64IZFH-NEXT: and a0, a1, a0
-; RV64IZFH-NEXT: ret
+; CHECK-LABEL: fcmps_ord:
+; CHECK: # %bb.0:
+; CHECK-NEXT: fle.h a0, fa1, fa1
+; CHECK-NEXT: fle.h a1, fa0, fa0
+; CHECK-NEXT: and a0, a1, a0
+; CHECK-NEXT: ret
%1 = call i1 @llvm.experimental.constrained.fcmps.f16(half %a, half %b, metadata !"ord", metadata !"fpexcept.strict") strictfp
%2 = zext i1 %1 to i32
ret i32 %2
}
define i32 @fcmps_ueq(half %a, half %b) nounwind strictfp {
-; RV32IZFH-LABEL: fcmps_ueq:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: flt.h a0, fa0, fa1
-; RV32IZFH-NEXT: flt.h a1, fa1, fa0
-; RV32IZFH-NEXT: or a0, a1, a0
-; RV32IZFH-NEXT: xori a0, a0, 1
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: fcmps_ueq:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: flt.h a0, fa0, fa1
-; RV64IZFH-NEXT: flt.h a1, fa1, fa0
-; RV64IZFH-NEXT: or a0, a1, a0
-; RV64IZFH-NEXT: xori a0, a0, 1
-; RV64IZFH-NEXT: ret
+; CHECK-LABEL: fcmps_ueq:
+; CHECK: # %bb.0:
+; CHECK-NEXT: flt.h a0, fa0, fa1
+; CHECK-NEXT: flt.h a1, fa1, fa0
+; CHECK-NEXT: or a0, a1, a0
+; CHECK-NEXT: xori a0, a0, 1
+; CHECK-NEXT: ret
%1 = call i1 @llvm.experimental.constrained.fcmps.f16(half %a, half %b, metadata !"ueq", metadata !"fpexcept.strict") strictfp
%2 = zext i1 %1 to i32
ret i32 %2
}
define i32 @fcmps_ugt(half %a, half %b) nounwind strictfp {
-; RV32IZFH-LABEL: fcmps_ugt:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: fle.h a0, fa0, fa1
-; RV32IZFH-NEXT: xori a0, a0, 1
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: fcmps_ugt:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fle.h a0, fa0, fa1
-; RV64IZFH-NEXT: xori a0, a0, 1
-; RV64IZFH-NEXT: ret
+; CHECK-LABEL: fcmps_ugt:
+; CHECK: # %bb.0:
+; CHECK-NEXT: fle.h a0, fa0, fa1
+; CHECK-NEXT: xori a0, a0, 1
+; CHECK-NEXT: ret
%1 = call i1 @llvm.experimental.constrained.fcmps.f16(half %a, half %b, metadata !"ugt", metadata !"fpexcept.strict") strictfp
%2 = zext i1 %1 to i32
ret i32 %2
}
define i32 @fcmps_uge(half %a, half %b) nounwind strictfp {
-; RV32IZFH-LABEL: fcmps_uge:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: flt.h a0, fa0, fa1
-; RV32IZFH-NEXT: xori a0, a0, 1
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: fcmps_uge:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: flt.h a0, fa0, fa1
-; RV64IZFH-NEXT: xori a0, a0, 1
-; RV64IZFH-NEXT: ret
+; CHECK-LABEL: fcmps_uge:
+; CHECK: # %bb.0:
+; CHECK-NEXT: flt.h a0, fa0, fa1
+; CHECK-NEXT: xori a0, a0, 1
+; CHECK-NEXT: ret
%1 = call i1 @llvm.experimental.constrained.fcmps.f16(half %a, half %b, metadata !"uge", metadata !"fpexcept.strict") strictfp
%2 = zext i1 %1 to i32
ret i32 %2
}
define i32 @fcmps_ult(half %a, half %b) nounwind strictfp {
-; RV32IZFH-LABEL: fcmps_ult:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: fle.h a0, fa1, fa0
-; RV32IZFH-NEXT: xori a0, a0, 1
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: fcmps_ult:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fle.h a0, fa1, fa0
-; RV64IZFH-NEXT: xori a0, a0, 1
-; RV64IZFH-NEXT: ret
+; CHECK-LABEL: fcmps_ult:
+; CHECK: # %bb.0:
+; CHECK-NEXT: fle.h a0, fa1, fa0
+; CHECK-NEXT: xori a0, a0, 1
+; CHECK-NEXT: ret
%1 = call i1 @llvm.experimental.constrained.fcmps.f16(half %a, half %b, metadata !"ult", metadata !"fpexcept.strict") strictfp
%2 = zext i1 %1 to i32
ret i32 %2
}
define i32 @fcmps_ule(half %a, half %b) nounwind strictfp {
-; RV32IZFH-LABEL: fcmps_ule:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: flt.h a0, fa1, fa0
-; RV32IZFH-NEXT: xori a0, a0, 1
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: fcmps_ule:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: flt.h a0, fa1, fa0
-; RV64IZFH-NEXT: xori a0, a0, 1
-; RV64IZFH-NEXT: ret
+; CHECK-LABEL: fcmps_ule:
+; CHECK: # %bb.0:
+; CHECK-NEXT: flt.h a0, fa1, fa0
+; CHECK-NEXT: xori a0, a0, 1
+; CHECK-NEXT: ret
%1 = call i1 @llvm.experimental.constrained.fcmps.f16(half %a, half %b, metadata !"ule", metadata !"fpexcept.strict") strictfp
%2 = zext i1 %1 to i32
ret i32 %2
}
define i32 @fcmps_une(half %a, half %b) nounwind strictfp {
-; RV32IZFH-LABEL: fcmps_une:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: fle.h a0, fa1, fa0
-; RV32IZFH-NEXT: fle.h a1, fa0, fa1
-; RV32IZFH-NEXT: and a0, a1, a0
-; RV32IZFH-NEXT: xori a0, a0, 1
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: fcmps_une:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fle.h a0, fa1, fa0
-; RV64IZFH-NEXT: fle.h a1, fa0, fa1
-; RV64IZFH-NEXT: and a0, a1, a0
-; RV64IZFH-NEXT: xori a0, a0, 1
-; RV64IZFH-NEXT: ret
+; CHECK-LABEL: fcmps_une:
+; CHECK: # %bb.0:
+; CHECK-NEXT: fle.h a0, fa1, fa0
+; CHECK-NEXT: fle.h a1, fa0, fa1
+; CHECK-NEXT: and a0, a1, a0
+; CHECK-NEXT: xori a0, a0, 1
+; CHECK-NEXT: ret
%1 = call i1 @llvm.experimental.constrained.fcmps.f16(half %a, half %b, metadata !"une", metadata !"fpexcept.strict") strictfp
%2 = zext i1 %1 to i32
ret i32 %2
}
define i32 @fcmps_uno(half %a, half %b) nounwind strictfp {
-; RV32IZFH-LABEL: fcmps_uno:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: fle.h a0, fa1, fa1
-; RV32IZFH-NEXT: fle.h a1, fa0, fa0
-; RV32IZFH-NEXT: and a0, a1, a0
-; RV32IZFH-NEXT: xori a0, a0, 1
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: fcmps_uno:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fle.h a0, fa1, fa1
-; RV64IZFH-NEXT: fle.h a1, fa0, fa0
-; RV64IZFH-NEXT: and a0, a1, a0
-; RV64IZFH-NEXT: xori a0, a0, 1
-; RV64IZFH-NEXT: ret
+; CHECK-LABEL: fcmps_uno:
+; CHECK: # %bb.0:
+; CHECK-NEXT: fle.h a0, fa1, fa1
+; CHECK-NEXT: fle.h a1, fa0, fa0
+; CHECK-NEXT: and a0, a1, a0
+; CHECK-NEXT: xori a0, a0, 1
+; CHECK-NEXT: ret
%1 = call i1 @llvm.experimental.constrained.fcmps.f16(half %a, half %b, metadata !"uno", metadata !"fpexcept.strict") strictfp
%2 = zext i1 %1 to i32
ret i32 %2
diff --git a/llvm/test/CodeGen/RISCV/half-fcmp.ll b/llvm/test/CodeGen/RISCV/half-fcmp.ll
index 97e34ca6fea5..7c84c9607bb8 100644
--- a/llvm/test/CodeGen/RISCV/half-fcmp.ll
+++ b/llvm/test/CodeGen/RISCV/half-fcmp.ll
@@ -1,23 +1,18 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs \
-; RUN: -target-abi ilp32f < %s | FileCheck -check-prefix=RV32IZFH %s
+; RUN: -target-abi ilp32f < %s | FileCheck -check-prefix=CHECKIZFH %s
; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs \
-; RUN: -target-abi lp64f < %s | FileCheck -check-prefix=RV64IZFH %s
+; RUN: -target-abi lp64f < %s | FileCheck -check-prefix=CHECKIZFH %s
; RUN: llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs \
; RUN: < %s | FileCheck -check-prefix=RV32I %s
; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs \
; RUN: < %s | FileCheck -check-prefix=RV64I %s
define i32 @fcmp_false(half %a, half %b) nounwind {
-; RV32IZFH-LABEL: fcmp_false:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: li a0, 0
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: fcmp_false:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: li a0, 0
-; RV64IZFH-NEXT: ret
+;CHECKIZFH-LABEL: fcmp_false:
+;CHECKIZFH: # %bb.0:
+;CHECKIZFH-NEXT: li a0, 0
+;CHECKIZFH-NEXT: ret
;
; RV32I-LABEL: fcmp_false:
; RV32I: # %bb.0:
@@ -34,15 +29,10 @@ define i32 @fcmp_false(half %a, half %b) nounwind {
}
define i32 @fcmp_oeq(half %a, half %b) nounwind {
-; RV32IZFH-LABEL: fcmp_oeq:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: feq.h a0, fa0, fa1
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: fcmp_oeq:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: feq.h a0, fa0, fa1
-; RV64IZFH-NEXT: ret
+;CHECKIZFH-LABEL: fcmp_oeq:
+;CHECKIZFH: # %bb.0:
+;CHECKIZFH-NEXT: feq.h a0, fa0, fa1
+;CHECKIZFH-NEXT: ret
;
; RV32I-LABEL: fcmp_oeq:
; RV32I: # %bb.0:
@@ -63,15 +53,10 @@ define i32 @fcmp_oeq(half %a, half %b) nounwind {
}
define i32 @fcmp_ogt(half %a, half %b) nounwind {
-; RV32IZFH-LABEL: fcmp_ogt:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: flt.h a0, fa1, fa0
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: fcmp_ogt:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: flt.h a0, fa1, fa0
-; RV64IZFH-NEXT: ret
+;CHECKIZFH-LABEL: fcmp_ogt:
+;CHECKIZFH: # %bb.0:
+;CHECKIZFH-NEXT: flt.h a0, fa1, fa0
+;CHECKIZFH-NEXT: ret
;
; RV32I-LABEL: fcmp_ogt:
; RV32I: # %bb.0:
@@ -92,15 +77,10 @@ define i32 @fcmp_ogt(half %a, half %b) nounwind {
}
define i32 @fcmp_oge(half %a, half %b) nounwind {
-; RV32IZFH-LABEL: fcmp_oge:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: fle.h a0, fa1, fa0
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: fcmp_oge:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fle.h a0, fa1, fa0
-; RV64IZFH-NEXT: ret
+;CHECKIZFH-LABEL: fcmp_oge:
+;CHECKIZFH: # %bb.0:
+;CHECKIZFH-NEXT: fle.h a0, fa1, fa0
+;CHECKIZFH-NEXT: ret
;
; RV32I-LABEL: fcmp_oge:
; RV32I: # %bb.0:
@@ -121,15 +101,10 @@ define i32 @fcmp_oge(half %a, half %b) nounwind {
}
define i32 @fcmp_olt(half %a, half %b) nounwind {
-; RV32IZFH-LABEL: fcmp_olt:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: flt.h a0, fa0, fa1
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: fcmp_olt:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: flt.h a0, fa0, fa1
-; RV64IZFH-NEXT: ret
+;CHECKIZFH-LABEL: fcmp_olt:
+;CHECKIZFH: # %bb.0:
+;CHECKIZFH-NEXT: flt.h a0, fa0, fa1
+;CHECKIZFH-NEXT: ret
;
; RV32I-LABEL: fcmp_olt:
; RV32I: # %bb.0:
@@ -150,15 +125,10 @@ define i32 @fcmp_olt(half %a, half %b) nounwind {
}
define i32 @fcmp_ole(half %a, half %b) nounwind {
-; RV32IZFH-LABEL: fcmp_ole:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: fle.h a0, fa0, fa1
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: fcmp_ole:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fle.h a0, fa0, fa1
-; RV64IZFH-NEXT: ret
+;CHECKIZFH-LABEL: fcmp_ole:
+;CHECKIZFH: # %bb.0:
+;CHECKIZFH-NEXT: fle.h a0, fa0, fa1
+;CHECKIZFH-NEXT: ret
;
; RV32I-LABEL: fcmp_ole:
; RV32I: # %bb.0:
@@ -179,19 +149,12 @@ define i32 @fcmp_ole(half %a, half %b) nounwind {
}
define i32 @fcmp_one(half %a, half %b) nounwind {
-; RV32IZFH-LABEL: fcmp_one:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: flt.h a0, fa0, fa1
-; RV32IZFH-NEXT: flt.h a1, fa1, fa0
-; RV32IZFH-NEXT: or a0, a1, a0
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: fcmp_one:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: flt.h a0, fa0, fa1
-; RV64IZFH-NEXT: flt.h a1, fa1, fa0
-; RV64IZFH-NEXT: or a0, a1, a0
-; RV64IZFH-NEXT: ret
+;CHECKIZFH-LABEL: fcmp_one:
+;CHECKIZFH: # %bb.0:
+;CHECKIZFH-NEXT: flt.h a0, fa0, fa1
+;CHECKIZFH-NEXT: flt.h a1, fa1, fa0
+;CHECKIZFH-NEXT: or a0, a1, a0
+;CHECKIZFH-NEXT: ret
;
; RV32I-LABEL: fcmp_one:
; RV32I: # %bb.0:
@@ -216,19 +179,12 @@ define i32 @fcmp_one(half %a, half %b) nounwind {
}
define i32 @fcmp_ord(half %a, half %b) nounwind {
-; RV32IZFH-LABEL: fcmp_ord:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: feq.h a0, fa1, fa1
-; RV32IZFH-NEXT: feq.h a1, fa0, fa0
-; RV32IZFH-NEXT: and a0, a1, a0
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: fcmp_ord:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: feq.h a0, fa1, fa1
-; RV64IZFH-NEXT: feq.h a1, fa0, fa0
-; RV64IZFH-NEXT: and a0, a1, a0
-; RV64IZFH-NEXT: ret
+;CHECKIZFH-LABEL: fcmp_ord:
+;CHECKIZFH: # %bb.0:
+;CHECKIZFH-NEXT: feq.h a0, fa1, fa1
+;CHECKIZFH-NEXT: feq.h a1, fa0, fa0
+;CHECKIZFH-NEXT: and a0, a1, a0
+;CHECKIZFH-NEXT: ret
;
; RV32I-LABEL: fcmp_ord:
; RV32I: # %bb.0:
@@ -253,21 +209,13 @@ define i32 @fcmp_ord(half %a, half %b) nounwind {
}
define i32 @fcmp_ueq(half %a, half %b) nounwind {
-; RV32IZFH-LABEL: fcmp_ueq:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: flt.h a0, fa0, fa1
-; RV32IZFH-NEXT: flt.h a1, fa1, fa0
-; RV32IZFH-NEXT: or a0, a1, a0
-; RV32IZFH-NEXT: xori a0, a0, 1
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: fcmp_ueq:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: flt.h a0, fa0, fa1
-; RV64IZFH-NEXT: flt.h a1, fa1, fa0
-; RV64IZFH-NEXT: or a0, a1, a0
-; RV64IZFH-NEXT: xori a0, a0, 1
-; RV64IZFH-NEXT: ret
+;CHECKIZFH-LABEL: fcmp_ueq:
+;CHECKIZFH: # %bb.0:
+;CHECKIZFH-NEXT: flt.h a0, fa0, fa1
+;CHECKIZFH-NEXT: flt.h a1, fa1, fa0
+;CHECKIZFH-NEXT: or a0, a1, a0
+;CHECKIZFH-NEXT: xori a0, a0, 1
+;CHECKIZFH-NEXT: ret
;
; RV32I-LABEL: fcmp_ueq:
; RV32I: # %bb.0:
@@ -294,17 +242,11 @@ define i32 @fcmp_ueq(half %a, half %b) nounwind {
}
define i32 @fcmp_ugt(half %a, half %b) nounwind {
-; RV32IZFH-LABEL: fcmp_ugt:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: fle.h a0, fa0, fa1
-; RV32IZFH-NEXT: xori a0, a0, 1
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: fcmp_ugt:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fle.h a0, fa0, fa1
-; RV64IZFH-NEXT: xori a0, a0, 1
-; RV64IZFH-NEXT: ret
+;CHECKIZFH-LABEL: fcmp_ugt:
+;CHECKIZFH: # %bb.0:
+;CHECKIZFH-NEXT: fle.h a0, fa0, fa1
+;CHECKIZFH-NEXT: xori a0, a0, 1
+;CHECKIZFH-NEXT: ret
;
; RV32I-LABEL: fcmp_ugt:
; RV32I: # %bb.0:
@@ -327,17 +269,11 @@ define i32 @fcmp_ugt(half %a, half %b) nounwind {
}
define i32 @fcmp_uge(half %a, half %b) nounwind {
-; RV32IZFH-LABEL: fcmp_uge:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: flt.h a0, fa0, fa1
-; RV32IZFH-NEXT: xori a0, a0, 1
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: fcmp_uge:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: flt.h a0, fa0, fa1
-; RV64IZFH-NEXT: xori a0, a0, 1
-; RV64IZFH-NEXT: ret
+;CHECKIZFH-LABEL: fcmp_uge:
+;CHECKIZFH: # %bb.0:
+;CHECKIZFH-NEXT: flt.h a0, fa0, fa1
+;CHECKIZFH-NEXT: xori a0, a0, 1
+;CHECKIZFH-NEXT: ret
;
; RV32I-LABEL: fcmp_uge:
; RV32I: # %bb.0:
@@ -360,17 +296,11 @@ define i32 @fcmp_uge(half %a, half %b) nounwind {
}
define i32 @fcmp_ult(half %a, half %b) nounwind {
-; RV32IZFH-LABEL: fcmp_ult:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: fle.h a0, fa1, fa0
-; RV32IZFH-NEXT: xori a0, a0, 1
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: fcmp_ult:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fle.h a0, fa1, fa0
-; RV64IZFH-NEXT: xori a0, a0, 1
-; RV64IZFH-NEXT: ret
+;CHECKIZFH-LABEL: fcmp_ult:
+;CHECKIZFH: # %bb.0:
+;CHECKIZFH-NEXT: fle.h a0, fa1, fa0
+;CHECKIZFH-NEXT: xori a0, a0, 1
+;CHECKIZFH-NEXT: ret
;
; RV32I-LABEL: fcmp_ult:
; RV32I: # %bb.0:
@@ -393,17 +323,11 @@ define i32 @fcmp_ult(half %a, half %b) nounwind {
}
define i32 @fcmp_ule(half %a, half %b) nounwind {
-; RV32IZFH-LABEL: fcmp_ule:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: flt.h a0, fa1, fa0
-; RV32IZFH-NEXT: xori a0, a0, 1
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: fcmp_ule:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: flt.h a0, fa1, fa0
-; RV64IZFH-NEXT: xori a0, a0, 1
-; RV64IZFH-NEXT: ret
+;CHECKIZFH-LABEL: fcmp_ule:
+;CHECKIZFH: # %bb.0:
+;CHECKIZFH-NEXT: flt.h a0, fa1, fa0
+;CHECKIZFH-NEXT: xori a0, a0, 1
+;CHECKIZFH-NEXT: ret
;
; RV32I-LABEL: fcmp_ule:
; RV32I: # %bb.0:
@@ -426,17 +350,11 @@ define i32 @fcmp_ule(half %a, half %b) nounwind {
}
define i32 @fcmp_une(half %a, half %b) nounwind {
-; RV32IZFH-LABEL: fcmp_une:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: feq.h a0, fa0, fa1
-; RV32IZFH-NEXT: xori a0, a0, 1
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: fcmp_une:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: feq.h a0, fa0, fa1
-; RV64IZFH-NEXT: xori a0, a0, 1
-; RV64IZFH-NEXT: ret
+;CHECKIZFH-LABEL: fcmp_une:
+;CHECKIZFH: # %bb.0:
+;CHECKIZFH-NEXT: feq.h a0, fa0, fa1
+;CHECKIZFH-NEXT: xori a0, a0, 1
+;CHECKIZFH-NEXT: ret
;
; RV32I-LABEL: fcmp_une:
; RV32I: # %bb.0:
@@ -459,21 +377,13 @@ define i32 @fcmp_une(half %a, half %b) nounwind {
}
define i32 @fcmp_uno(half %a, half %b) nounwind {
-; RV32IZFH-LABEL: fcmp_uno:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: feq.h a0, fa1, fa1
-; RV32IZFH-NEXT: feq.h a1, fa0, fa0
-; RV32IZFH-NEXT: and a0, a1, a0
-; RV32IZFH-NEXT: xori a0, a0, 1
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: fcmp_uno:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: feq.h a0, fa1, fa1
-; RV64IZFH-NEXT: feq.h a1, fa0, fa0
-; RV64IZFH-NEXT: and a0, a1, a0
-; RV64IZFH-NEXT: xori a0, a0, 1
-; RV64IZFH-NEXT: ret
+;CHECKIZFH-LABEL: fcmp_uno:
+;CHECKIZFH: # %bb.0:
+;CHECKIZFH-NEXT: feq.h a0, fa1, fa1
+;CHECKIZFH-NEXT: feq.h a1, fa0, fa0
+;CHECKIZFH-NEXT: and a0, a1, a0
+;CHECKIZFH-NEXT: xori a0, a0, 1
+;CHECKIZFH-NEXT: ret
;
; RV32I-LABEL: fcmp_uno:
; RV32I: # %bb.0:
@@ -500,15 +410,10 @@ define i32 @fcmp_uno(half %a, half %b) nounwind {
}
define i32 @fcmp_true(half %a, half %b) nounwind {
-; RV32IZFH-LABEL: fcmp_true:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: li a0, 1
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: fcmp_true:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: li a0, 1
-; RV64IZFH-NEXT: ret
+;CHECKIZFH-LABEL: fcmp_true:
+;CHECKIZFH: # %bb.0:
+;CHECKIZFH-NEXT: li a0, 1
+;CHECKIZFH-NEXT: ret
;
; RV32I-LABEL: fcmp_true:
; RV32I: # %bb.0:
diff --git a/llvm/test/CodeGen/RISCV/half-imm.ll b/llvm/test/CodeGen/RISCV/half-imm.ll
index 3774b4df2c4a..04ded9d3e735 100644
--- a/llvm/test/CodeGen/RISCV/half-imm.ll
+++ b/llvm/test/CodeGen/RISCV/half-imm.ll
@@ -1,39 +1,26 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs \
-; RUN: -target-abi ilp32f < %s | FileCheck -check-prefix=RV32IZFH %s
+; RUN: -target-abi ilp32f < %s | FileCheck %s
; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs \
-; RUN: -target-abi lp64f < %s | FileCheck -check-prefix=RV64IZFH %s
+; RUN: -target-abi lp64f < %s | FileCheck %s
; TODO: constant pool shouldn't be necessary for RV32IZfh and RV64IZfh
define half @half_imm() nounwind {
-; RV32IZFH-LABEL: half_imm:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: lui a0, %hi(.LCPI0_0)
-; RV32IZFH-NEXT: flh fa0, %lo(.LCPI0_0)(a0)
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: half_imm:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: lui a0, %hi(.LCPI0_0)
-; RV64IZFH-NEXT: flh fa0, %lo(.LCPI0_0)(a0)
-; RV64IZFH-NEXT: ret
+; CHECK-LABEL: half_imm:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a0, %hi(.LCPI0_0)
+; CHECK-NEXT: flh fa0, %lo(.LCPI0_0)(a0)
+; CHECK-NEXT: ret
ret half 3.0
}
define half @half_imm_op(half %a) nounwind {
-; RV32IZFH-LABEL: half_imm_op:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: lui a0, %hi(.LCPI1_0)
-; RV32IZFH-NEXT: flh ft0, %lo(.LCPI1_0)(a0)
-; RV32IZFH-NEXT: fadd.h fa0, fa0, ft0
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: half_imm_op:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: lui a0, %hi(.LCPI1_0)
-; RV64IZFH-NEXT: flh ft0, %lo(.LCPI1_0)(a0)
-; RV64IZFH-NEXT: fadd.h fa0, fa0, ft0
-; RV64IZFH-NEXT: ret
+; CHECK-LABEL: half_imm_op:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a0, %hi(.LCPI1_0)
+; CHECK-NEXT: flh ft0, %lo(.LCPI1_0)(a0)
+; CHECK-NEXT: fadd.h fa0, fa0, ft0
+; CHECK-NEXT: ret
%1 = fadd half %a, 1.0
ret half %1
}
diff --git a/llvm/test/CodeGen/RISCV/half-intrinsics.ll b/llvm/test/CodeGen/RISCV/half-intrinsics.ll
index c8cafbbd5d2a..caa9f3708324 100644
--- a/llvm/test/CodeGen/RISCV/half-intrinsics.ll
+++ b/llvm/test/CodeGen/RISCV/half-intrinsics.ll
@@ -1,10 +1,10 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zfh \
; RUN: -verify-machineinstrs -target-abi ilp32f | \
-; RUN: FileCheck -check-prefix=RV32IZFH %s
+; RUN: FileCheck -check-prefixes=CHECKIZFH,RV32IZFH %s
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zfh \
; RUN: -verify-machineinstrs -target-abi lp64f | \
-; RUN: FileCheck -check-prefix=RV64IZFH %s
+; RUN: FileCheck -check-prefixes=CHECKIZFH,RV64IZFH %s
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+d \
; RUN: -mattr=+zfh -verify-machineinstrs -target-abi ilp32d | \
; RUN: FileCheck -check-prefix=RV32IDZFH %s
@@ -21,15 +21,10 @@
declare half @llvm.sqrt.f16(half)
define half @sqrt_f16(half %a) nounwind {
-; RV32IZFH-LABEL: sqrt_f16:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: fsqrt.h fa0, fa0
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: sqrt_f16:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fsqrt.h fa0, fa0
-; RV64IZFH-NEXT: ret
+; CHECKIZFH-LABEL: sqrt_f16:
+; CHECKIZFH: # %bb.0:
+; CHECKIZFH-NEXT: fsqrt.h fa0, fa0
+; CHECKIZFH-NEXT: ret
;
; RV32IDZFH-LABEL: sqrt_f16:
; RV32IDZFH: # %bb.0:
@@ -954,15 +949,10 @@ define half @log2_f16(half %a) nounwind {
declare half @llvm.fma.f16(half, half, half)
define half @fma_f16(half %a, half %b, half %c) nounwind {
-; RV32IZFH-LABEL: fma_f16:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: fmadd.h fa0, fa0, fa1, fa2
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: fma_f16:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fmadd.h fa0, fa0, fa1, fa2
-; RV64IZFH-NEXT: ret
+; CHECKIZFH-LABEL: fma_f16:
+; CHECKIZFH: # %bb.0:
+; CHECKIZFH-NEXT: fmadd.h fa0, fa0, fa1, fa2
+; CHECKIZFH-NEXT: ret
;
; RV32IDZFH-LABEL: fma_f16:
; RV32IDZFH: # %bb.0:
@@ -1046,15 +1036,10 @@ define half @fma_f16(half %a, half %b, half %c) nounwind {
declare half @llvm.fmuladd.f16(half, half, half)
define half @fmuladd_f16(half %a, half %b, half %c) nounwind {
-; RV32IZFH-LABEL: fmuladd_f16:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: fmadd.h fa0, fa0, fa1, fa2
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: fmuladd_f16:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fmadd.h fa0, fa0, fa1, fa2
-; RV64IZFH-NEXT: ret
+; CHECKIZFH-LABEL: fmuladd_f16:
+; CHECKIZFH: # %bb.0:
+; CHECKIZFH-NEXT: fmadd.h fa0, fa0, fa1, fa2
+; CHECKIZFH-NEXT: ret
;
; RV32IDZFH-LABEL: fmuladd_f16:
; RV32IDZFH: # %bb.0:
@@ -1148,15 +1133,10 @@ define half @fmuladd_f16(half %a, half %b, half %c) nounwind {
declare half @llvm.fabs.f16(half)
define half @fabs_f16(half %a) nounwind {
-; RV32IZFH-LABEL: fabs_f16:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: fabs.h fa0, fa0
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: fabs_f16:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fabs.h fa0, fa0
-; RV64IZFH-NEXT: ret
+; CHECKIZFH-LABEL: fabs_f16:
+; CHECKIZFH: # %bb.0:
+; CHECKIZFH-NEXT: fabs.h fa0, fa0
+; CHECKIZFH-NEXT: ret
;
; RV32IDZFH-LABEL: fabs_f16:
; RV32IDZFH: # %bb.0:
@@ -1186,15 +1166,10 @@ define half @fabs_f16(half %a) nounwind {
declare half @llvm.minnum.f16(half, half)
define half @minnum_f16(half %a, half %b) nounwind {
-; RV32IZFH-LABEL: minnum_f16:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: fmin.h fa0, fa0, fa1
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: minnum_f16:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fmin.h fa0, fa0, fa1
-; RV64IZFH-NEXT: ret
+; CHECKIZFH-LABEL: minnum_f16:
+; CHECKIZFH: # %bb.0:
+; CHECKIZFH-NEXT: fmin.h fa0, fa0, fa1
+; CHECKIZFH-NEXT: ret
;
; RV32IDZFH-LABEL: minnum_f16:
; RV32IDZFH: # %bb.0:
@@ -1264,15 +1239,10 @@ define half @minnum_f16(half %a, half %b) nounwind {
declare half @llvm.maxnum.f16(half, half)
define half @maxnum_f16(half %a, half %b) nounwind {
-; RV32IZFH-LABEL: maxnum_f16:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: fmax.h fa0, fa0, fa1
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: maxnum_f16:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fmax.h fa0, fa0, fa1
-; RV64IZFH-NEXT: ret
+; CHECKIZFH-LABEL: maxnum_f16:
+; CHECKIZFH: # %bb.0:
+; CHECKIZFH-NEXT: fmax.h fa0, fa0, fa1
+; CHECKIZFH-NEXT: ret
;
; RV32IDZFH-LABEL: maxnum_f16:
; RV32IDZFH: # %bb.0:
@@ -1359,15 +1329,10 @@ define half @maxnum_f16(half %a, half %b) nounwind {
declare half @llvm.copysign.f16(half, half)
define half @copysign_f16(half %a, half %b) nounwind {
-; RV32IZFH-LABEL: copysign_f16:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: fsgnj.h fa0, fa0, fa1
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: copysign_f16:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fsgnj.h fa0, fa0, fa1
-; RV64IZFH-NEXT: ret
+; CHECKIZFH-LABEL: copysign_f16:
+; CHECKIZFH: # %bb.0:
+; CHECKIZFH-NEXT: fsgnj.h fa0, fa0, fa1
+; CHECKIZFH-NEXT: ret
;
; RV32IDZFH-LABEL: copysign_f16:
; RV32IDZFH: # %bb.0:
diff --git a/llvm/test/CodeGen/RISCV/half-isnan.ll b/llvm/test/CodeGen/RISCV/half-isnan.ll
index 928af9d418eb..48a99e56b4cf 100644
--- a/llvm/test/CodeGen/RISCV/half-isnan.ll
+++ b/llvm/test/CodeGen/RISCV/half-isnan.ll
@@ -1,35 +1,24 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs \
-; RUN: -target-abi ilp32f < %s | FileCheck -check-prefix=RV32IZFH %s
+; RUN: -target-abi ilp32f < %s | FileCheck %s
; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs \
-; RUN: -target-abi lp64f < %s | FileCheck -check-prefix=RV64IZFH %s
+; RUN: -target-abi lp64f < %s | FileCheck %s
define zeroext i1 @half_is_nan(half %a) nounwind {
-; RV32IZFH-LABEL: half_is_nan:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: feq.h a0, fa0, fa0
-; RV32IZFH-NEXT: xori a0, a0, 1
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: half_is_nan:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: feq.h a0, fa0, fa0
-; RV64IZFH-NEXT: xori a0, a0, 1
-; RV64IZFH-NEXT: ret
+; CHECK-LABEL: half_is_nan:
+; CHECK: # %bb.0:
+; CHECK-NEXT: feq.h a0, fa0, fa0
+; CHECK-NEXT: xori a0, a0, 1
+; CHECK-NEXT: ret
%1 = fcmp uno half %a, 0.000000e+00
ret i1 %1
}
define zeroext i1 @half_not_nan(half %a) nounwind {
-; RV32IZFH-LABEL: half_not_nan:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: feq.h a0, fa0, fa0
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: half_not_nan:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: feq.h a0, fa0, fa0
-; RV64IZFH-NEXT: ret
+; CHECK-LABEL: half_not_nan:
+; CHECK: # %bb.0:
+; CHECK-NEXT: feq.h a0, fa0, fa0
+; CHECK-NEXT: ret
%1 = fcmp ord half %a, 0.000000e+00
ret i1 %1
}
diff --git a/llvm/test/CodeGen/RISCV/half-mem.ll b/llvm/test/CodeGen/RISCV/half-mem.ll
index 9049b92946a6..196ec2612bc2 100644
--- a/llvm/test/CodeGen/RISCV/half-mem.ll
+++ b/llvm/test/CodeGen/RISCV/half-mem.ll
@@ -1,23 +1,16 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs \
-; RUN: -target-abi ilp32f < %s | FileCheck -check-prefix=RV32IZFH %s
+; RUN: -target-abi ilp32f < %s | FileCheck -check-prefixes=CHECKIZFH,RV32IZFH %s
; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs \
-; RUN: -target-abi lp64f < %s | FileCheck -check-prefix=RV64IZFH %s
+; RUN: -target-abi lp64f < %s | FileCheck -check-prefixes=CHECKIZFH,RV64IZFH %s
define half @flh(half *%a) nounwind {
-; RV32IZFH-LABEL: flh:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: flh ft0, 0(a0)
-; RV32IZFH-NEXT: flh ft1, 6(a0)
-; RV32IZFH-NEXT: fadd.h fa0, ft0, ft1
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: flh:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: flh ft0, 0(a0)
-; RV64IZFH-NEXT: flh ft1, 6(a0)
-; RV64IZFH-NEXT: fadd.h fa0, ft0, ft1
-; RV64IZFH-NEXT: ret
+; CHECKIZFH-LABEL: flh:
+; CHECKIZFH: # %bb.0:
+; CHECKIZFH-NEXT: flh ft0, 0(a0)
+; CHECKIZFH-NEXT: flh ft1, 6(a0)
+; CHECKIZFH-NEXT: fadd.h fa0, ft0, ft1
+; CHECKIZFH-NEXT: ret
%1 = load half, half* %a
%2 = getelementptr half, half* %a, i32 3
%3 = load half, half* %2
@@ -30,19 +23,12 @@ define half @flh(half *%a) nounwind {
define dso_local void @fsh(half *%a, half %b, half %c) nounwind {
; Use %b and %c in an FP op to ensure half precision floating point registers
; are used, even for the soft half ABI
-; RV32IZFH-LABEL: fsh:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: fadd.h ft0, fa0, fa1
-; RV32IZFH-NEXT: fsh ft0, 0(a0)
-; RV32IZFH-NEXT: fsh ft0, 16(a0)
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: fsh:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fadd.h ft0, fa0, fa1
-; RV64IZFH-NEXT: fsh ft0, 0(a0)
-; RV64IZFH-NEXT: fsh ft0, 16(a0)
-; RV64IZFH-NEXT: ret
+; CHECKIZFH-LABEL: fsh:
+; CHECKIZFH: # %bb.0:
+; CHECKIZFH-NEXT: fadd.h ft0, fa0, fa1
+; CHECKIZFH-NEXT: fsh ft0, 0(a0)
+; CHECKIZFH-NEXT: fsh ft0, 16(a0)
+; CHECKIZFH-NEXT: ret
%1 = fadd half %b, %c
store half %1, half* %a
%2 = getelementptr half, half* %a, i32 8
@@ -56,27 +42,16 @@ define dso_local void @fsh(half *%a, half %b, half %c) nounwind {
define half @flh_fsh_global(half %a, half %b) nounwind {
; Use %a and %b in an FP op to ensure half precision floating point registers
; are used, even for the soft half ABI
-; RV32IZFH-LABEL: flh_fsh_global:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: fadd.h fa0, fa0, fa1
-; RV32IZFH-NEXT: lui a0, %hi(G)
-; RV32IZFH-NEXT: flh ft0, %lo(G)(a0)
-; RV32IZFH-NEXT: addi a1, a0, %lo(G)
-; RV32IZFH-NEXT: fsh fa0, %lo(G)(a0)
-; RV32IZFH-NEXT: flh ft0, 18(a1)
-; RV32IZFH-NEXT: fsh fa0, 18(a1)
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: flh_fsh_global:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fadd.h fa0, fa0, fa1
-; RV64IZFH-NEXT: lui a0, %hi(G)
-; RV64IZFH-NEXT: flh ft0, %lo(G)(a0)
-; RV64IZFH-NEXT: addi a1, a0, %lo(G)
-; RV64IZFH-NEXT: fsh fa0, %lo(G)(a0)
-; RV64IZFH-NEXT: flh ft0, 18(a1)
-; RV64IZFH-NEXT: fsh fa0, 18(a1)
-; RV64IZFH-NEXT: ret
+; CHECKIZFH-LABEL: flh_fsh_global:
+; CHECKIZFH: # %bb.0:
+; CHECKIZFH-NEXT: fadd.h fa0, fa0, fa1
+; CHECKIZFH-NEXT: lui a0, %hi(G)
+; CHECKIZFH-NEXT: flh ft0, %lo(G)(a0)
+; CHECKIZFH-NEXT: addi a1, a0, %lo(G)
+; CHECKIZFH-NEXT: fsh fa0, %lo(G)(a0)
+; CHECKIZFH-NEXT: flh ft0, 18(a1)
+; CHECKIZFH-NEXT: fsh fa0, 18(a1)
+; CHECKIZFH-NEXT: ret
%1 = fadd half %a, %b
%2 = load volatile half, half* @G
store half %1, half* @G
diff --git a/llvm/test/CodeGen/RISCV/half-round-conv-sat.ll b/llvm/test/CodeGen/RISCV/half-round-conv-sat.ll
index 163c792d8a9e..6041507faee6 100644
--- a/llvm/test/CodeGen/RISCV/half-round-conv-sat.ll
+++ b/llvm/test/CodeGen/RISCV/half-round-conv-sat.ll
@@ -1,27 +1,18 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs < %s \
-; RUN: -target-abi=ilp32f | FileCheck -check-prefix=RV32IZFH %s
+; RUN: -target-abi=ilp32f | FileCheck -check-prefixes=CHECKIZFH,RV32IZFH %s
; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs < %s \
-; RUN: -target-abi=lp64f | FileCheck -check-prefix=RV64IZFH %s
+; RUN: -target-abi=lp64f | FileCheck -check-prefixes=CHECKIZFH,RV64IZFH %s
define signext i32 @test_floor_si32(half %x) {
-; RV32IZFH-LABEL: test_floor_si32:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: feq.h a0, fa0, fa0
-; RV32IZFH-NEXT: beqz a0, .LBB0_2
-; RV32IZFH-NEXT: # %bb.1:
-; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rdn
-; RV32IZFH-NEXT: .LBB0_2:
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: test_floor_si32:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: feq.h a0, fa0, fa0
-; RV64IZFH-NEXT: beqz a0, .LBB0_2
-; RV64IZFH-NEXT: # %bb.1:
-; RV64IZFH-NEXT: fcvt.w.h a0, fa0, rdn
-; RV64IZFH-NEXT: .LBB0_2:
-; RV64IZFH-NEXT: ret
+; CHECKIZFH-LABEL: test_floor_si32:
+; CHECKIZFH: # %bb.0:
+; CHECKIZFH-NEXT: feq.h a0, fa0, fa0
+; CHECKIZFH-NEXT: beqz a0, .LBB0_2
+; CHECKIZFH-NEXT: # %bb.1:
+; CHECKIZFH-NEXT: fcvt.w.h a0, fa0, rdn
+; CHECKIZFH-NEXT: .LBB0_2:
+; CHECKIZFH-NEXT: ret
%a = call half @llvm.floor.f16(half %x)
%b = call i32 @llvm.fptosi.sat.i32.f16(half %a)
ret i32 %b
@@ -101,23 +92,14 @@ define i64 @test_floor_si64(half %x) nounwind {
}
define signext i32 @test_floor_ui32(half %x) {
-; RV32IZFH-LABEL: test_floor_ui32:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: feq.h a0, fa0, fa0
-; RV32IZFH-NEXT: beqz a0, .LBB2_2
-; RV32IZFH-NEXT: # %bb.1:
-; RV32IZFH-NEXT: fcvt.wu.h a0, fa0, rdn
-; RV32IZFH-NEXT: .LBB2_2:
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: test_floor_ui32:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: feq.h a0, fa0, fa0
-; RV64IZFH-NEXT: beqz a0, .LBB2_2
-; RV64IZFH-NEXT: # %bb.1:
-; RV64IZFH-NEXT: fcvt.wu.h a0, fa0, rdn
-; RV64IZFH-NEXT: .LBB2_2:
-; RV64IZFH-NEXT: ret
+; CHECKIZFH-LABEL: test_floor_ui32:
+; CHECKIZFH: # %bb.0:
+; CHECKIZFH-NEXT: feq.h a0, fa0, fa0
+; CHECKIZFH-NEXT: beqz a0, .LBB2_2
+; CHECKIZFH-NEXT: # %bb.1:
+; CHECKIZFH-NEXT: fcvt.wu.h a0, fa0, rdn
+; CHECKIZFH-NEXT: .LBB2_2:
+; CHECKIZFH-NEXT: ret
%a = call half @llvm.floor.f16(half %x)
%b = call i32 @llvm.fptoui.sat.i32.f16(half %a)
ret i32 %b
@@ -184,23 +166,14 @@ define i64 @test_floor_ui64(half %x) nounwind {
}
define signext i32 @test_ceil_si32(half %x) {
-; RV32IZFH-LABEL: test_ceil_si32:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: feq.h a0, fa0, fa0
-; RV32IZFH-NEXT: beqz a0, .LBB4_2
-; RV32IZFH-NEXT: # %bb.1:
-; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rup
-; RV32IZFH-NEXT: .LBB4_2:
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: test_ceil_si32:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: feq.h a0, fa0, fa0
-; RV64IZFH-NEXT: beqz a0, .LBB4_2
-; RV64IZFH-NEXT: # %bb.1:
-; RV64IZFH-NEXT: fcvt.w.h a0, fa0, rup
-; RV64IZFH-NEXT: .LBB4_2:
-; RV64IZFH-NEXT: ret
+; CHECKIZFH-LABEL: test_ceil_si32:
+; CHECKIZFH: # %bb.0:
+; CHECKIZFH-NEXT: feq.h a0, fa0, fa0
+; CHECKIZFH-NEXT: beqz a0, .LBB4_2
+; CHECKIZFH-NEXT: # %bb.1:
+; CHECKIZFH-NEXT: fcvt.w.h a0, fa0, rup
+; CHECKIZFH-NEXT: .LBB4_2:
+; CHECKIZFH-NEXT: ret
%a = call half @llvm.ceil.f16(half %x)
%b = call i32 @llvm.fptosi.sat.i32.f16(half %a)
ret i32 %b
@@ -280,23 +253,14 @@ define i64 @test_ceil_si64(half %x) nounwind {
}
define signext i32 @test_ceil_ui32(half %x) {
-; RV32IZFH-LABEL: test_ceil_ui32:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: feq.h a0, fa0, fa0
-; RV32IZFH-NEXT: beqz a0, .LBB6_2
-; RV32IZFH-NEXT: # %bb.1:
-; RV32IZFH-NEXT: fcvt.wu.h a0, fa0, rup
-; RV32IZFH-NEXT: .LBB6_2:
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: test_ceil_ui32:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: feq.h a0, fa0, fa0
-; RV64IZFH-NEXT: beqz a0, .LBB6_2
-; RV64IZFH-NEXT: # %bb.1:
-; RV64IZFH-NEXT: fcvt.wu.h a0, fa0, rup
-; RV64IZFH-NEXT: .LBB6_2:
-; RV64IZFH-NEXT: ret
+; CHECKIZFH-LABEL: test_ceil_ui32:
+; CHECKIZFH: # %bb.0:
+; CHECKIZFH-NEXT: feq.h a0, fa0, fa0
+; CHECKIZFH-NEXT: beqz a0, .LBB6_2
+; CHECKIZFH-NEXT: # %bb.1:
+; CHECKIZFH-NEXT: fcvt.wu.h a0, fa0, rup
+; CHECKIZFH-NEXT: .LBB6_2:
+; CHECKIZFH-NEXT: ret
%a = call half @llvm.ceil.f16(half %x)
%b = call i32 @llvm.fptoui.sat.i32.f16(half %a)
ret i32 %b
@@ -363,23 +327,14 @@ define i64 @test_ceil_ui64(half %x) nounwind {
}
define signext i32 @test_trunc_si32(half %x) {
-; RV32IZFH-LABEL: test_trunc_si32:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: feq.h a0, fa0, fa0
-; RV32IZFH-NEXT: beqz a0, .LBB8_2
-; RV32IZFH-NEXT: # %bb.1:
-; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rtz
-; RV32IZFH-NEXT: .LBB8_2:
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: test_trunc_si32:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: feq.h a0, fa0, fa0
-; RV64IZFH-NEXT: beqz a0, .LBB8_2
-; RV64IZFH-NEXT: # %bb.1:
-; RV64IZFH-NEXT: fcvt.w.h a0, fa0, rtz
-; RV64IZFH-NEXT: .LBB8_2:
-; RV64IZFH-NEXT: ret
+; CHECKIZFH-LABEL: test_trunc_si32:
+; CHECKIZFH: # %bb.0:
+; CHECKIZFH-NEXT: feq.h a0, fa0, fa0
+; CHECKIZFH-NEXT: beqz a0, .LBB8_2
+; CHECKIZFH-NEXT: # %bb.1:
+; CHECKIZFH-NEXT: fcvt.w.h a0, fa0, rtz
+; CHECKIZFH-NEXT: .LBB8_2:
+; CHECKIZFH-NEXT: ret
%a = call half @llvm.trunc.f16(half %x)
%b = call i32 @llvm.fptosi.sat.i32.f16(half %a)
ret i32 %b
@@ -459,23 +414,14 @@ define i64 @test_trunc_si64(half %x) nounwind {
}
define signext i32 @test_trunc_ui32(half %x) {
-; RV32IZFH-LABEL: test_trunc_ui32:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: feq.h a0, fa0, fa0
-; RV32IZFH-NEXT: beqz a0, .LBB10_2
-; RV32IZFH-NEXT: # %bb.1:
-; RV32IZFH-NEXT: fcvt.wu.h a0, fa0, rtz
-; RV32IZFH-NEXT: .LBB10_2:
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: test_trunc_ui32:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: feq.h a0, fa0, fa0
-; RV64IZFH-NEXT: beqz a0, .LBB10_2
-; RV64IZFH-NEXT: # %bb.1:
-; RV64IZFH-NEXT: fcvt.wu.h a0, fa0, rtz
-; RV64IZFH-NEXT: .LBB10_2:
-; RV64IZFH-NEXT: ret
+; CHECKIZFH-LABEL: test_trunc_ui32:
+; CHECKIZFH: # %bb.0:
+; CHECKIZFH-NEXT: feq.h a0, fa0, fa0
+; CHECKIZFH-NEXT: beqz a0, .LBB10_2
+; CHECKIZFH-NEXT: # %bb.1:
+; CHECKIZFH-NEXT: fcvt.wu.h a0, fa0, rtz
+; CHECKIZFH-NEXT: .LBB10_2:
+; CHECKIZFH-NEXT: ret
%a = call half @llvm.trunc.f16(half %x)
%b = call i32 @llvm.fptoui.sat.i32.f16(half %a)
ret i32 %b
@@ -542,23 +488,14 @@ define i64 @test_trunc_ui64(half %x) nounwind {
}
define signext i32 @test_round_si32(half %x) {
-; RV32IZFH-LABEL: test_round_si32:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: feq.h a0, fa0, fa0
-; RV32IZFH-NEXT: beqz a0, .LBB12_2
-; RV32IZFH-NEXT: # %bb.1:
-; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rmm
-; RV32IZFH-NEXT: .LBB12_2:
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: test_round_si32:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: feq.h a0, fa0, fa0
-; RV64IZFH-NEXT: beqz a0, .LBB12_2
-; RV64IZFH-NEXT: # %bb.1:
-; RV64IZFH-NEXT: fcvt.w.h a0, fa0, rmm
-; RV64IZFH-NEXT: .LBB12_2:
-; RV64IZFH-NEXT: ret
+; CHECKIZFH-LABEL: test_round_si32:
+; CHECKIZFH: # %bb.0:
+; CHECKIZFH-NEXT: feq.h a0, fa0, fa0
+; CHECKIZFH-NEXT: beqz a0, .LBB12_2
+; CHECKIZFH-NEXT: # %bb.1:
+; CHECKIZFH-NEXT: fcvt.w.h a0, fa0, rmm
+; CHECKIZFH-NEXT: .LBB12_2:
+; CHECKIZFH-NEXT: ret
%a = call half @llvm.round.f16(half %x)
%b = call i32 @llvm.fptosi.sat.i32.f16(half %a)
ret i32 %b
@@ -638,23 +575,14 @@ define i64 @test_round_si64(half %x) nounwind {
}
define signext i32 @test_round_ui32(half %x) {
-; RV32IZFH-LABEL: test_round_ui32:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: feq.h a0, fa0, fa0
-; RV32IZFH-NEXT: beqz a0, .LBB14_2
-; RV32IZFH-NEXT: # %bb.1:
-; RV32IZFH-NEXT: fcvt.wu.h a0, fa0, rmm
-; RV32IZFH-NEXT: .LBB14_2:
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: test_round_ui32:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: feq.h a0, fa0, fa0
-; RV64IZFH-NEXT: beqz a0, .LBB14_2
-; RV64IZFH-NEXT: # %bb.1:
-; RV64IZFH-NEXT: fcvt.wu.h a0, fa0, rmm
-; RV64IZFH-NEXT: .LBB14_2:
-; RV64IZFH-NEXT: ret
+; CHECKIZFH-LABEL: test_round_ui32:
+; CHECKIZFH: # %bb.0:
+; CHECKIZFH-NEXT: feq.h a0, fa0, fa0
+; CHECKIZFH-NEXT: beqz a0, .LBB14_2
+; CHECKIZFH-NEXT: # %bb.1:
+; CHECKIZFH-NEXT: fcvt.wu.h a0, fa0, rmm
+; CHECKIZFH-NEXT: .LBB14_2:
+; CHECKIZFH-NEXT: ret
%a = call half @llvm.round.f16(half %x)
%b = call i32 @llvm.fptoui.sat.i32.f16(half %a)
ret i32 %b
@@ -721,23 +649,14 @@ define i64 @test_round_ui64(half %x) nounwind {
}
define signext i32 @test_roundeven_si32(half %x) {
-; RV32IZFH-LABEL: test_roundeven_si32:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: feq.h a0, fa0, fa0
-; RV32IZFH-NEXT: beqz a0, .LBB16_2
-; RV32IZFH-NEXT: # %bb.1:
-; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rne
-; RV32IZFH-NEXT: .LBB16_2:
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: test_roundeven_si32:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: feq.h a0, fa0, fa0
-; RV64IZFH-NEXT: beqz a0, .LBB16_2
-; RV64IZFH-NEXT: # %bb.1:
-; RV64IZFH-NEXT: fcvt.w.h a0, fa0, rne
-; RV64IZFH-NEXT: .LBB16_2:
-; RV64IZFH-NEXT: ret
+; CHECKIZFH-LABEL: test_roundeven_si32:
+; CHECKIZFH: # %bb.0:
+; CHECKIZFH-NEXT: feq.h a0, fa0, fa0
+; CHECKIZFH-NEXT: beqz a0, .LBB16_2
+; CHECKIZFH-NEXT: # %bb.1:
+; CHECKIZFH-NEXT: fcvt.w.h a0, fa0, rne
+; CHECKIZFH-NEXT: .LBB16_2:
+; CHECKIZFH-NEXT: ret
%a = call half @llvm.roundeven.f16(half %x)
%b = call i32 @llvm.fptosi.sat.i32.f16(half %a)
ret i32 %b
@@ -817,23 +736,14 @@ define i64 @test_roundeven_si64(half %x) nounwind {
}
define signext i32 @test_roundeven_ui32(half %x) {
-; RV32IZFH-LABEL: test_roundeven_ui32:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: feq.h a0, fa0, fa0
-; RV32IZFH-NEXT: beqz a0, .LBB18_2
-; RV32IZFH-NEXT: # %bb.1:
-; RV32IZFH-NEXT: fcvt.wu.h a0, fa0, rne
-; RV32IZFH-NEXT: .LBB18_2:
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: test_roundeven_ui32:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: feq.h a0, fa0, fa0
-; RV64IZFH-NEXT: beqz a0, .LBB18_2
-; RV64IZFH-NEXT: # %bb.1:
-; RV64IZFH-NEXT: fcvt.wu.h a0, fa0, rne
-; RV64IZFH-NEXT: .LBB18_2:
-; RV64IZFH-NEXT: ret
+; CHECKIZFH-LABEL: test_roundeven_ui32:
+; CHECKIZFH: # %bb.0:
+; CHECKIZFH-NEXT: feq.h a0, fa0, fa0
+; CHECKIZFH-NEXT: beqz a0, .LBB18_2
+; CHECKIZFH-NEXT: # %bb.1:
+; CHECKIZFH-NEXT: fcvt.wu.h a0, fa0, rne
+; CHECKIZFH-NEXT: .LBB18_2:
+; CHECKIZFH-NEXT: ret
%a = call half @llvm.roundeven.f16(half %x)
%b = call i32 @llvm.fptoui.sat.i32.f16(half %a)
ret i32 %b
diff --git a/llvm/test/CodeGen/RISCV/half-round-conv.ll b/llvm/test/CodeGen/RISCV/half-round-conv.ll
index 997f0196a1e8..7511d3c2d15b 100644
--- a/llvm/test/CodeGen/RISCV/half-round-conv.ll
+++ b/llvm/test/CodeGen/RISCV/half-round-conv.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs < %s \
-; RUN: -target-abi=ilp32f | FileCheck -check-prefix=RV32IZFH %s
+; RUN: -target-abi=ilp32f | FileCheck -check-prefixes=CHECKIZFH,RV32IZFH %s
; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs < %s \
-; RUN: -target-abi=lp64f | FileCheck -check-prefix=RV64IZFH %s
+; RUN: -target-abi=lp64f | FileCheck -check-prefixes=CHECKIZFH,RV64IZFH %s
define signext i8 @test_floor_si8(half %x) {
; RV32IZFH-LABEL: test_floor_si8:
@@ -35,15 +35,10 @@ define signext i16 @test_floor_si16(half %x) {
}
define signext i32 @test_floor_si32(half %x) {
-; RV32IZFH-LABEL: test_floor_si32:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rdn
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: test_floor_si32:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fcvt.w.h a0, fa0, rdn
-; RV64IZFH-NEXT: ret
+; CHECKIZFH-LABEL: test_floor_si32:
+; CHECKIZFH: # %bb.0:
+; CHECKIZFH-NEXT: fcvt.w.h a0, fa0, rdn
+; CHECKIZFH-NEXT: ret
%a = call half @llvm.floor.f16(half %x)
%b = fptosi half %a to i32
ret i32 %b
@@ -104,15 +99,10 @@ define zeroext i16 @test_floor_ui16(half %x) {
}
define signext i32 @test_floor_ui32(half %x) {
-; RV32IZFH-LABEL: test_floor_ui32:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: fcvt.wu.h a0, fa0, rdn
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: test_floor_ui32:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fcvt.wu.h a0, fa0, rdn
-; RV64IZFH-NEXT: ret
+; CHECKIZFH-LABEL: test_floor_ui32:
+; CHECKIZFH: # %bb.0:
+; CHECKIZFH-NEXT: fcvt.wu.h a0, fa0, rdn
+; CHECKIZFH-NEXT: ret
%a = call half @llvm.floor.f16(half %x)
%b = fptoui half %a to i32
ret i32 %b
@@ -173,15 +163,10 @@ define signext i16 @test_ceil_si16(half %x) {
}
define signext i32 @test_ceil_si32(half %x) {
-; RV32IZFH-LABEL: test_ceil_si32:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rup
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: test_ceil_si32:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fcvt.w.h a0, fa0, rup
-; RV64IZFH-NEXT: ret
+; CHECKIZFH-LABEL: test_ceil_si32:
+; CHECKIZFH: # %bb.0:
+; CHECKIZFH-NEXT: fcvt.w.h a0, fa0, rup
+; CHECKIZFH-NEXT: ret
%a = call half @llvm.ceil.f16(half %x)
%b = fptosi half %a to i32
ret i32 %b
@@ -242,15 +227,10 @@ define zeroext i16 @test_ceil_ui16(half %x) {
}
define signext i32 @test_ceil_ui32(half %x) {
-; RV32IZFH-LABEL: test_ceil_ui32:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: fcvt.wu.h a0, fa0, rup
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: test_ceil_ui32:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fcvt.wu.h a0, fa0, rup
-; RV64IZFH-NEXT: ret
+; CHECKIZFH-LABEL: test_ceil_ui32:
+; CHECKIZFH: # %bb.0:
+; CHECKIZFH-NEXT: fcvt.wu.h a0, fa0, rup
+; CHECKIZFH-NEXT: ret
%a = call half @llvm.ceil.f16(half %x)
%b = fptoui half %a to i32
ret i32 %b
@@ -311,15 +291,10 @@ define signext i16 @test_trunc_si16(half %x) {
}
define signext i32 @test_trunc_si32(half %x) {
-; RV32IZFH-LABEL: test_trunc_si32:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rtz
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: test_trunc_si32:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fcvt.w.h a0, fa0, rtz
-; RV64IZFH-NEXT: ret
+; CHECKIZFH-LABEL: test_trunc_si32:
+; CHECKIZFH: # %bb.0:
+; CHECKIZFH-NEXT: fcvt.w.h a0, fa0, rtz
+; CHECKIZFH-NEXT: ret
%a = call half @llvm.trunc.f16(half %x)
%b = fptosi half %a to i32
ret i32 %b
@@ -380,15 +355,10 @@ define zeroext i16 @test_trunc_ui16(half %x) {
}
define signext i32 @test_trunc_ui32(half %x) {
-; RV32IZFH-LABEL: test_trunc_ui32:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: fcvt.wu.h a0, fa0, rtz
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: test_trunc_ui32:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fcvt.wu.h a0, fa0, rtz
-; RV64IZFH-NEXT: ret
+; CHECKIZFH-LABEL: test_trunc_ui32:
+; CHECKIZFH: # %bb.0:
+; CHECKIZFH-NEXT: fcvt.wu.h a0, fa0, rtz
+; CHECKIZFH-NEXT: ret
%a = call half @llvm.trunc.f16(half %x)
%b = fptoui half %a to i32
ret i32 %b
@@ -449,15 +419,10 @@ define signext i16 @test_round_si16(half %x) {
}
define signext i32 @test_round_si32(half %x) {
-; RV32IZFH-LABEL: test_round_si32:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rmm
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: test_round_si32:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fcvt.w.h a0, fa0, rmm
-; RV64IZFH-NEXT: ret
+; CHECKIZFH-LABEL: test_round_si32:
+; CHECKIZFH: # %bb.0:
+; CHECKIZFH-NEXT: fcvt.w.h a0, fa0, rmm
+; CHECKIZFH-NEXT: ret
%a = call half @llvm.round.f16(half %x)
%b = fptosi half %a to i32
ret i32 %b
@@ -518,15 +483,10 @@ define zeroext i16 @test_round_ui16(half %x) {
}
define signext i32 @test_round_ui32(half %x) {
-; RV32IZFH-LABEL: test_round_ui32:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: fcvt.wu.h a0, fa0, rmm
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: test_round_ui32:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fcvt.wu.h a0, fa0, rmm
-; RV64IZFH-NEXT: ret
+; CHECKIZFH-LABEL: test_round_ui32:
+; CHECKIZFH: # %bb.0:
+; CHECKIZFH-NEXT: fcvt.wu.h a0, fa0, rmm
+; CHECKIZFH-NEXT: ret
%a = call half @llvm.round.f16(half %x)
%b = fptoui half %a to i32
ret i32 %b
@@ -587,15 +547,10 @@ define signext i16 @test_roundeven_si16(half %x) {
}
define signext i32 @test_roundeven_si32(half %x) {
-; RV32IZFH-LABEL: test_roundeven_si32:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rne
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: test_roundeven_si32:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fcvt.w.h a0, fa0, rne
-; RV64IZFH-NEXT: ret
+; CHECKIZFH-LABEL: test_roundeven_si32:
+; CHECKIZFH: # %bb.0:
+; CHECKIZFH-NEXT: fcvt.w.h a0, fa0, rne
+; CHECKIZFH-NEXT: ret
%a = call half @llvm.roundeven.f16(half %x)
%b = fptosi half %a to i32
ret i32 %b
@@ -656,15 +611,10 @@ define zeroext i16 @test_roundeven_ui16(half %x) {
}
define signext i32 @test_roundeven_ui32(half %x) {
-; RV32IZFH-LABEL: test_roundeven_ui32:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: fcvt.wu.h a0, fa0, rne
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: test_roundeven_ui32:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fcvt.wu.h a0, fa0, rne
-; RV64IZFH-NEXT: ret
+; CHECKIZFH-LABEL: test_roundeven_ui32:
+; CHECKIZFH: # %bb.0:
+; CHECKIZFH-NEXT: fcvt.wu.h a0, fa0, rne
+; CHECKIZFH-NEXT: ret
%a = call half @llvm.roundeven.f16(half %x)
%b = fptoui half %a to i32
ret i32 %b
diff --git a/llvm/test/CodeGen/RISCV/half-select-fcmp.ll b/llvm/test/CodeGen/RISCV/half-select-fcmp.ll
index 9a5aaaabb73c..936f590f20bf 100644
--- a/llvm/test/CodeGen/RISCV/half-select-fcmp.ll
+++ b/llvm/test/CodeGen/RISCV/half-select-fcmp.ll
@@ -1,370 +1,227 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs \
-; RUN: -target-abi ilp32f < %s | FileCheck -check-prefix=RV32IZFH %s
+; RUN: -target-abi ilp32f < %s | FileCheck %s
; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs \
-; RUN: -target-abi lp64f < %s | FileCheck -check-prefix=RV64IZFH %s
+; RUN: -target-abi lp64f < %s | FileCheck %s
define half @select_fcmp_false(half %a, half %b) nounwind {
-; RV32IZFH-LABEL: select_fcmp_false:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: fmv.h fa0, fa1
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: select_fcmp_false:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fmv.h fa0, fa1
-; RV64IZFH-NEXT: ret
+; CHECK-LABEL: select_fcmp_false:
+; CHECK: # %bb.0:
+; CHECK-NEXT: fmv.h fa0, fa1
+; CHECK-NEXT: ret
%1 = fcmp false half %a, %b
%2 = select i1 %1, half %a, half %b
ret half %2
}
define half @select_fcmp_oeq(half %a, half %b) nounwind {
-; RV32IZFH-LABEL: select_fcmp_oeq:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: feq.h a0, fa0, fa1
-; RV32IZFH-NEXT: bnez a0, .LBB1_2
-; RV32IZFH-NEXT: # %bb.1:
-; RV32IZFH-NEXT: fmv.h fa0, fa1
-; RV32IZFH-NEXT: .LBB1_2:
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: select_fcmp_oeq:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: feq.h a0, fa0, fa1
-; RV64IZFH-NEXT: bnez a0, .LBB1_2
-; RV64IZFH-NEXT: # %bb.1:
-; RV64IZFH-NEXT: fmv.h fa0, fa1
-; RV64IZFH-NEXT: .LBB1_2:
-; RV64IZFH-NEXT: ret
+; CHECK-LABEL: select_fcmp_oeq:
+; CHECK: # %bb.0:
+; CHECK-NEXT: feq.h a0, fa0, fa1
+; CHECK-NEXT: bnez a0, .LBB1_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: fmv.h fa0, fa1
+; CHECK-NEXT: .LBB1_2:
+; CHECK-NEXT: ret
%1 = fcmp oeq half %a, %b
%2 = select i1 %1, half %a, half %b
ret half %2
}
define half @select_fcmp_ogt(half %a, half %b) nounwind {
-; RV32IZFH-LABEL: select_fcmp_ogt:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: flt.h a0, fa1, fa0
-; RV32IZFH-NEXT: bnez a0, .LBB2_2
-; RV32IZFH-NEXT: # %bb.1:
-; RV32IZFH-NEXT: fmv.h fa0, fa1
-; RV32IZFH-NEXT: .LBB2_2:
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: select_fcmp_ogt:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: flt.h a0, fa1, fa0
-; RV64IZFH-NEXT: bnez a0, .LBB2_2
-; RV64IZFH-NEXT: # %bb.1:
-; RV64IZFH-NEXT: fmv.h fa0, fa1
-; RV64IZFH-NEXT: .LBB2_2:
-; RV64IZFH-NEXT: ret
+; CHECK-LABEL: select_fcmp_ogt:
+; CHECK: # %bb.0:
+; CHECK-NEXT: flt.h a0, fa1, fa0
+; CHECK-NEXT: bnez a0, .LBB2_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: fmv.h fa0, fa1
+; CHECK-NEXT: .LBB2_2:
+; CHECK-NEXT: ret
%1 = fcmp ogt half %a, %b
%2 = select i1 %1, half %a, half %b
ret half %2
}
define half @select_fcmp_oge(half %a, half %b) nounwind {
-; RV32IZFH-LABEL: select_fcmp_oge:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: fle.h a0, fa1, fa0
-; RV32IZFH-NEXT: bnez a0, .LBB3_2
-; RV32IZFH-NEXT: # %bb.1:
-; RV32IZFH-NEXT: fmv.h fa0, fa1
-; RV32IZFH-NEXT: .LBB3_2:
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: select_fcmp_oge:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fle.h a0, fa1, fa0
-; RV64IZFH-NEXT: bnez a0, .LBB3_2
-; RV64IZFH-NEXT: # %bb.1:
-; RV64IZFH-NEXT: fmv.h fa0, fa1
-; RV64IZFH-NEXT: .LBB3_2:
-; RV64IZFH-NEXT: ret
+; CHECK-LABEL: select_fcmp_oge:
+; CHECK: # %bb.0:
+; CHECK-NEXT: fle.h a0, fa1, fa0
+; CHECK-NEXT: bnez a0, .LBB3_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: fmv.h fa0, fa1
+; CHECK-NEXT: .LBB3_2:
+; CHECK-NEXT: ret
%1 = fcmp oge half %a, %b
%2 = select i1 %1, half %a, half %b
ret half %2
}
define half @select_fcmp_olt(half %a, half %b) nounwind {
-; RV32IZFH-LABEL: select_fcmp_olt:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: flt.h a0, fa0, fa1
-; RV32IZFH-NEXT: bnez a0, .LBB4_2
-; RV32IZFH-NEXT: # %bb.1:
-; RV32IZFH-NEXT: fmv.h fa0, fa1
-; RV32IZFH-NEXT: .LBB4_2:
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: select_fcmp_olt:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: flt.h a0, fa0, fa1
-; RV64IZFH-NEXT: bnez a0, .LBB4_2
-; RV64IZFH-NEXT: # %bb.1:
-; RV64IZFH-NEXT: fmv.h fa0, fa1
-; RV64IZFH-NEXT: .LBB4_2:
-; RV64IZFH-NEXT: ret
+; CHECK-LABEL: select_fcmp_olt:
+; CHECK: # %bb.0:
+; CHECK-NEXT: flt.h a0, fa0, fa1
+; CHECK-NEXT: bnez a0, .LBB4_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: fmv.h fa0, fa1
+; CHECK-NEXT: .LBB4_2:
+; CHECK-NEXT: ret
%1 = fcmp olt half %a, %b
%2 = select i1 %1, half %a, half %b
ret half %2
}
define half @select_fcmp_ole(half %a, half %b) nounwind {
-; RV32IZFH-LABEL: select_fcmp_ole:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: fle.h a0, fa0, fa1
-; RV32IZFH-NEXT: bnez a0, .LBB5_2
-; RV32IZFH-NEXT: # %bb.1:
-; RV32IZFH-NEXT: fmv.h fa0, fa1
-; RV32IZFH-NEXT: .LBB5_2:
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: select_fcmp_ole:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fle.h a0, fa0, fa1
-; RV64IZFH-NEXT: bnez a0, .LBB5_2
-; RV64IZFH-NEXT: # %bb.1:
-; RV64IZFH-NEXT: fmv.h fa0, fa1
-; RV64IZFH-NEXT: .LBB5_2:
-; RV64IZFH-NEXT: ret
+; CHECK-LABEL: select_fcmp_ole:
+; CHECK: # %bb.0:
+; CHECK-NEXT: fle.h a0, fa0, fa1
+; CHECK-NEXT: bnez a0, .LBB5_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: fmv.h fa0, fa1
+; CHECK-NEXT: .LBB5_2:
+; CHECK-NEXT: ret
%1 = fcmp ole half %a, %b
%2 = select i1 %1, half %a, half %b
ret half %2
}
define half @select_fcmp_one(half %a, half %b) nounwind {
-; RV32IZFH-LABEL: select_fcmp_one:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: flt.h a0, fa0, fa1
-; RV32IZFH-NEXT: flt.h a1, fa1, fa0
-; RV32IZFH-NEXT: or a0, a1, a0
-; RV32IZFH-NEXT: bnez a0, .LBB6_2
-; RV32IZFH-NEXT: # %bb.1:
-; RV32IZFH-NEXT: fmv.h fa0, fa1
-; RV32IZFH-NEXT: .LBB6_2:
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: select_fcmp_one:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: flt.h a0, fa0, fa1
-; RV64IZFH-NEXT: flt.h a1, fa1, fa0
-; RV64IZFH-NEXT: or a0, a1, a0
-; RV64IZFH-NEXT: bnez a0, .LBB6_2
-; RV64IZFH-NEXT: # %bb.1:
-; RV64IZFH-NEXT: fmv.h fa0, fa1
-; RV64IZFH-NEXT: .LBB6_2:
-; RV64IZFH-NEXT: ret
+; CHECK-LABEL: select_fcmp_one:
+; CHECK: # %bb.0:
+; CHECK-NEXT: flt.h a0, fa0, fa1
+; CHECK-NEXT: flt.h a1, fa1, fa0
+; CHECK-NEXT: or a0, a1, a0
+; CHECK-NEXT: bnez a0, .LBB6_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: fmv.h fa0, fa1
+; CHECK-NEXT: .LBB6_2:
+; CHECK-NEXT: ret
%1 = fcmp one half %a, %b
%2 = select i1 %1, half %a, half %b
ret half %2
}
define half @select_fcmp_ord(half %a, half %b) nounwind {
-; RV32IZFH-LABEL: select_fcmp_ord:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: feq.h a0, fa1, fa1
-; RV32IZFH-NEXT: feq.h a1, fa0, fa0
-; RV32IZFH-NEXT: and a0, a1, a0
-; RV32IZFH-NEXT: bnez a0, .LBB7_2
-; RV32IZFH-NEXT: # %bb.1:
-; RV32IZFH-NEXT: fmv.h fa0, fa1
-; RV32IZFH-NEXT: .LBB7_2:
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: select_fcmp_ord:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: feq.h a0, fa1, fa1
-; RV64IZFH-NEXT: feq.h a1, fa0, fa0
-; RV64IZFH-NEXT: and a0, a1, a0
-; RV64IZFH-NEXT: bnez a0, .LBB7_2
-; RV64IZFH-NEXT: # %bb.1:
-; RV64IZFH-NEXT: fmv.h fa0, fa1
-; RV64IZFH-NEXT: .LBB7_2:
-; RV64IZFH-NEXT: ret
+; CHECK-LABEL: select_fcmp_ord:
+; CHECK: # %bb.0:
+; CHECK-NEXT: feq.h a0, fa1, fa1
+; CHECK-NEXT: feq.h a1, fa0, fa0
+; CHECK-NEXT: and a0, a1, a0
+; CHECK-NEXT: bnez a0, .LBB7_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: fmv.h fa0, fa1
+; CHECK-NEXT: .LBB7_2:
+; CHECK-NEXT: ret
%1 = fcmp ord half %a, %b
%2 = select i1 %1, half %a, half %b
ret half %2
}
define half @select_fcmp_ueq(half %a, half %b) nounwind {
-; RV32IZFH-LABEL: select_fcmp_ueq:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: flt.h a0, fa0, fa1
-; RV32IZFH-NEXT: flt.h a1, fa1, fa0
-; RV32IZFH-NEXT: or a0, a1, a0
-; RV32IZFH-NEXT: beqz a0, .LBB8_2
-; RV32IZFH-NEXT: # %bb.1:
-; RV32IZFH-NEXT: fmv.h fa0, fa1
-; RV32IZFH-NEXT: .LBB8_2:
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: select_fcmp_ueq:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: flt.h a0, fa0, fa1
-; RV64IZFH-NEXT: flt.h a1, fa1, fa0
-; RV64IZFH-NEXT: or a0, a1, a0
-; RV64IZFH-NEXT: beqz a0, .LBB8_2
-; RV64IZFH-NEXT: # %bb.1:
-; RV64IZFH-NEXT: fmv.h fa0, fa1
-; RV64IZFH-NEXT: .LBB8_2:
-; RV64IZFH-NEXT: ret
+; CHECK-LABEL: select_fcmp_ueq:
+; CHECK: # %bb.0:
+; CHECK-NEXT: flt.h a0, fa0, fa1
+; CHECK-NEXT: flt.h a1, fa1, fa0
+; CHECK-NEXT: or a0, a1, a0
+; CHECK-NEXT: beqz a0, .LBB8_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: fmv.h fa0, fa1
+; CHECK-NEXT: .LBB8_2:
+; CHECK-NEXT: ret
%1 = fcmp ueq half %a, %b
%2 = select i1 %1, half %a, half %b
ret half %2
}
define half @select_fcmp_ugt(half %a, half %b) nounwind {
-; RV32IZFH-LABEL: select_fcmp_ugt:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: fle.h a0, fa0, fa1
-; RV32IZFH-NEXT: beqz a0, .LBB9_2
-; RV32IZFH-NEXT: # %bb.1:
-; RV32IZFH-NEXT: fmv.h fa0, fa1
-; RV32IZFH-NEXT: .LBB9_2:
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: select_fcmp_ugt:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fle.h a0, fa0, fa1
-; RV64IZFH-NEXT: beqz a0, .LBB9_2
-; RV64IZFH-NEXT: # %bb.1:
-; RV64IZFH-NEXT: fmv.h fa0, fa1
-; RV64IZFH-NEXT: .LBB9_2:
-; RV64IZFH-NEXT: ret
+; CHECK-LABEL: select_fcmp_ugt:
+; CHECK: # %bb.0:
+; CHECK-NEXT: fle.h a0, fa0, fa1
+; CHECK-NEXT: beqz a0, .LBB9_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: fmv.h fa0, fa1
+; CHECK-NEXT: .LBB9_2:
+; CHECK-NEXT: ret
%1 = fcmp ugt half %a, %b
%2 = select i1 %1, half %a, half %b
ret half %2
}
define half @select_fcmp_uge(half %a, half %b) nounwind {
-; RV32IZFH-LABEL: select_fcmp_uge:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: flt.h a0, fa0, fa1
-; RV32IZFH-NEXT: beqz a0, .LBB10_2
-; RV32IZFH-NEXT: # %bb.1:
-; RV32IZFH-NEXT: fmv.h fa0, fa1
-; RV32IZFH-NEXT: .LBB10_2:
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: select_fcmp_uge:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: flt.h a0, fa0, fa1
-; RV64IZFH-NEXT: beqz a0, .LBB10_2
-; RV64IZFH-NEXT: # %bb.1:
-; RV64IZFH-NEXT: fmv.h fa0, fa1
-; RV64IZFH-NEXT: .LBB10_2:
-; RV64IZFH-NEXT: ret
+; CHECK-LABEL: select_fcmp_uge:
+; CHECK: # %bb.0:
+; CHECK-NEXT: flt.h a0, fa0, fa1
+; CHECK-NEXT: beqz a0, .LBB10_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: fmv.h fa0, fa1
+; CHECK-NEXT: .LBB10_2:
+; CHECK-NEXT: ret
%1 = fcmp uge half %a, %b
%2 = select i1 %1, half %a, half %b
ret half %2
}
define half @select_fcmp_ult(half %a, half %b) nounwind {
-; RV32IZFH-LABEL: select_fcmp_ult:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: fle.h a0, fa1, fa0
-; RV32IZFH-NEXT: beqz a0, .LBB11_2
-; RV32IZFH-NEXT: # %bb.1:
-; RV32IZFH-NEXT: fmv.h fa0, fa1
-; RV32IZFH-NEXT: .LBB11_2:
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: select_fcmp_ult:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fle.h a0, fa1, fa0
-; RV64IZFH-NEXT: beqz a0, .LBB11_2
-; RV64IZFH-NEXT: # %bb.1:
-; RV64IZFH-NEXT: fmv.h fa0, fa1
-; RV64IZFH-NEXT: .LBB11_2:
-; RV64IZFH-NEXT: ret
+; CHECK-LABEL: select_fcmp_ult:
+; CHECK: # %bb.0:
+; CHECK-NEXT: fle.h a0, fa1, fa0
+; CHECK-NEXT: beqz a0, .LBB11_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: fmv.h fa0, fa1
+; CHECK-NEXT: .LBB11_2:
+; CHECK-NEXT: ret
%1 = fcmp ult half %a, %b
%2 = select i1 %1, half %a, half %b
ret half %2
}
define half @select_fcmp_ule(half %a, half %b) nounwind {
-; RV32IZFH-LABEL: select_fcmp_ule:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: flt.h a0, fa1, fa0
-; RV32IZFH-NEXT: beqz a0, .LBB12_2
-; RV32IZFH-NEXT: # %bb.1:
-; RV32IZFH-NEXT: fmv.h fa0, fa1
-; RV32IZFH-NEXT: .LBB12_2:
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: select_fcmp_ule:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: flt.h a0, fa1, fa0
-; RV64IZFH-NEXT: beqz a0, .LBB12_2
-; RV64IZFH-NEXT: # %bb.1:
-; RV64IZFH-NEXT: fmv.h fa0, fa1
-; RV64IZFH-NEXT: .LBB12_2:
-; RV64IZFH-NEXT: ret
+; CHECK-LABEL: select_fcmp_ule:
+; CHECK: # %bb.0:
+; CHECK-NEXT: flt.h a0, fa1, fa0
+; CHECK-NEXT: beqz a0, .LBB12_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: fmv.h fa0, fa1
+; CHECK-NEXT: .LBB12_2:
+; CHECK-NEXT: ret
%1 = fcmp ule half %a, %b
%2 = select i1 %1, half %a, half %b
ret half %2
}
define half @select_fcmp_une(half %a, half %b) nounwind {
-; RV32IZFH-LABEL: select_fcmp_une:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: feq.h a0, fa0, fa1
-; RV32IZFH-NEXT: beqz a0, .LBB13_2
-; RV32IZFH-NEXT: # %bb.1:
-; RV32IZFH-NEXT: fmv.h fa0, fa1
-; RV32IZFH-NEXT: .LBB13_2:
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: select_fcmp_une:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: feq.h a0, fa0, fa1
-; RV64IZFH-NEXT: beqz a0, .LBB13_2
-; RV64IZFH-NEXT: # %bb.1:
-; RV64IZFH-NEXT: fmv.h fa0, fa1
-; RV64IZFH-NEXT: .LBB13_2:
-; RV64IZFH-NEXT: ret
+; CHECK-LABEL: select_fcmp_une:
+; CHECK: # %bb.0:
+; CHECK-NEXT: feq.h a0, fa0, fa1
+; CHECK-NEXT: beqz a0, .LBB13_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: fmv.h fa0, fa1
+; CHECK-NEXT: .LBB13_2:
+; CHECK-NEXT: ret
%1 = fcmp une half %a, %b
%2 = select i1 %1, half %a, half %b
ret half %2
}
define half @select_fcmp_uno(half %a, half %b) nounwind {
-; RV32IZFH-LABEL: select_fcmp_uno:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: feq.h a0, fa1, fa1
-; RV32IZFH-NEXT: feq.h a1, fa0, fa0
-; RV32IZFH-NEXT: and a0, a1, a0
-; RV32IZFH-NEXT: beqz a0, .LBB14_2
-; RV32IZFH-NEXT: # %bb.1:
-; RV32IZFH-NEXT: fmv.h fa0, fa1
-; RV32IZFH-NEXT: .LBB14_2:
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: select_fcmp_uno:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: feq.h a0, fa1, fa1
-; RV64IZFH-NEXT: feq.h a1, fa0, fa0
-; RV64IZFH-NEXT: and a0, a1, a0
-; RV64IZFH-NEXT: beqz a0, .LBB14_2
-; RV64IZFH-NEXT: # %bb.1:
-; RV64IZFH-NEXT: fmv.h fa0, fa1
-; RV64IZFH-NEXT: .LBB14_2:
-; RV64IZFH-NEXT: ret
+; CHECK-LABEL: select_fcmp_uno:
+; CHECK: # %bb.0:
+; CHECK-NEXT: feq.h a0, fa1, fa1
+; CHECK-NEXT: feq.h a1, fa0, fa0
+; CHECK-NEXT: and a0, a1, a0
+; CHECK-NEXT: beqz a0, .LBB14_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: fmv.h fa0, fa1
+; CHECK-NEXT: .LBB14_2:
+; CHECK-NEXT: ret
%1 = fcmp uno half %a, %b
%2 = select i1 %1, half %a, half %b
ret half %2
}
define half @select_fcmp_true(half %a, half %b) nounwind {
-; RV32IZFH-LABEL: select_fcmp_true:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: select_fcmp_true:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: ret
+; CHECK-LABEL: select_fcmp_true:
+; CHECK: # %bb.0:
+; CHECK-NEXT: ret
%1 = fcmp true half %a, %b
%2 = select i1 %1, half %a, half %b
ret half %2
@@ -372,23 +229,14 @@ define half @select_fcmp_true(half %a, half %b) nounwind {
; Ensure that ISel succeeds for a select+fcmp that has an i32 result type.
define i32 @i32_select_fcmp_oeq(half %a, half %b, i32 %c, i32 %d) nounwind {
-; RV32IZFH-LABEL: i32_select_fcmp_oeq:
-; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: feq.h a2, fa0, fa1
-; RV32IZFH-NEXT: bnez a2, .LBB16_2
-; RV32IZFH-NEXT: # %bb.1:
-; RV32IZFH-NEXT: mv a0, a1
-; RV32IZFH-NEXT: .LBB16_2:
-; RV32IZFH-NEXT: ret
-;
-; RV64IZFH-LABEL: i32_select_fcmp_oeq:
-; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: feq.h a2, fa0, fa1
-; RV64IZFH-NEXT: bnez a2, .LBB16_2
-; RV64IZFH-NEXT: # %bb.1:
-; RV64IZFH-NEXT: mv a0, a1
-; RV64IZFH-NEXT: .LBB16_2:
-; RV64IZFH-NEXT: ret
+; CHECK-LABEL: i32_select_fcmp_oeq:
+; CHECK: # %bb.0:
+; CHECK-NEXT: feq.h a2, fa0, fa1
+; CHECK-NEXT: bnez a2, .LBB16_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: mv a0, a1
+; CHECK-NEXT: .LBB16_2:
+; CHECK-NEXT: ret
%1 = fcmp oeq half %a, %b
%2 = select i1 %1, i32 %c, i32 %d
ret i32 %2
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