[PATCH] D123845: [BPF] Enable IAS in backend

[Brad Smith via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rGc2d27c89593e: [BPF] Enable IAS in backend (authored by brad).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D123845/new/

https://reviews.llvm.org/D123845

Files:
  llvm/lib/Target/BPF/MCTargetDesc/BPFMCAsmInfo.h
  llvm/test/CodeGen/BPF/inline_asm.ll


Index: llvm/test/CodeGen/BPF/inline_asm.ll
===================================================================
--- llvm/test/CodeGen/BPF/inline_asm.ll
+++ llvm/test/CodeGen/BPF/inline_asm.ll
@@ -35,10 +35,10 @@
   %2 = tail call i32 asm sideeffect "$0 = $1 ll", "=r,i"(i64 333333333333) #2
 ; CHECK: r1 = 333333333333 ll
   %3 = call i32 asm sideeffect "$0 = *(u16 *) $1", "=r,*m"(i32* elementtype(i32) nonnull %a) #2
-; CHECK: r1 = *(u16 *) (r10 - 4)
+; CHECK: r1 = *(u16 *)(r10 - 4)
   %4 = call i32 asm sideeffect "$0 = *(u32 *) $1", "=r,*m"(i32* elementtype(i32) getelementptr inbounds ([2 x i32], [2 x i32]* @g, i64 0, i64 1)) #2
 ; CHECK: r1 = g ll
-; CHECK: r0 = *(u32 *) (r1 + 4)
+; CHECK: r0 = *(u32 *)(r1 + 4)
   call void @llvm.lifetime.end.p0i8(i64 4, i8* nonnull %0) #2
   ret i32 %4
 }
Index: llvm/lib/Target/BPF/MCTargetDesc/BPFMCAsmInfo.h
===================================================================
--- llvm/lib/Target/BPF/MCTargetDesc/BPFMCAsmInfo.h
+++ llvm/lib/Target/BPF/MCTargetDesc/BPFMCAsmInfo.h
@@ -41,8 +41,6 @@
     // section will be parsable, but with odd offsets and
     // line numbers, etc.
     CodePointerSize = 8;
-
-    UseIntegratedAssembler = false;
   }
 
   void setDwarfUsesRelocationsAcrossSections(bool enable) {


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