[PATCH] D127045: [BOLT] Use 32-bit MOV to zero 64-bit register in instrumentation code

[Amir Ayupov via Phabricator via llvm-commits]

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clang-format


Instead of `movabsq $0x0, %rax` emit shorter equivalent `movl $0x0, %eax`.
Intel SDM, 3.4.1.1 General-Purpose Registers in 64-Bit Mode:

> 32-bit operands generate a 32-bit result, zero-extended to a 64-bit result in 
>  the destination general-purpose register.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D127045

Files:
  bolt/lib/Target/X86/X86MCPlusBuilder.cpp


Index: bolt/lib/Target/X86/X86MCPlusBuilder.cpp
===================================================================
--- bolt/lib/Target/X86/X86MCPlusBuilder.cpp
+++ bolt/lib/Target/X86/X86MCPlusBuilder.cpp
@@ -3129,7 +3129,12 @@
     case 1: Opcode = X86::MOV8ri; break;
     case 2: Opcode = X86::MOV16ri; break;
     case 4: Opcode = X86::MOV32ri; break;
-    case 8: Opcode = X86::MOV64ri; break;
+    // Writing to a 32-bit register always zeros the upper 32 bits of the
+    // full-width register
+    case 8:
+      Opcode = X86::MOV32ri;
+      Reg = getAliasSized(Reg, 4);
+      break;
     default:
       llvm_unreachable("Unexpected size");
     }


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