[PATCH] D126986: [RISCV] Support LUI+ADDIW in doPeepholeLoadStoreADDI.
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Jun 3 18:07:40 PDT 2022
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGcc3bd4353358: [RISCV] Support LUI+ADDIW in doPeepholeLoadStoreADDI. (authored by craig.topper).
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D126986/new/
https://reviews.llvm.org/D126986
Files:
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
llvm/test/CodeGen/RISCV/fold-addi-loadstore.ll
Index: llvm/test/CodeGen/RISCV/fold-addi-loadstore.ll
===================================================================
--- llvm/test/CodeGen/RISCV/fold-addi-loadstore.ll
+++ llvm/test/CodeGen/RISCV/fold-addi-loadstore.ll
@@ -328,14 +328,16 @@
; RV64I-LABEL: load_const_medium:
; RV64I: # %bb.0: # %entry
; RV64I-NEXT: lui a0, 1
-; RV64I-NEXT: addiw a0, a0, -16
-; RV64I-NEXT: lw a0, 0(a0)
+; RV64I-NEXT: lw a0, -16(a0)
; RV64I-NEXT: ret
entry:
%0 = load i32, i32* inttoptr (i64 4080 to i32*)
ret i32 %0
}
+; The constant here is 0x7ffff800, this value requires LUI+ADDIW on RV64,
+; LUI+ADDI would produce a different constant so we can't fold into the load
+; offset.
define dso_local i32 @load_const_large() nounwind {
; RV32I-LABEL: load_const_large:
; RV32I: # %bb.0: # %entry
Index: llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -2233,9 +2233,23 @@
if (!Base.isMachineOpcode())
return false;
- // If the base is an ADDI, we can merge it in to the load/store.
- if (Base.getMachineOpcode() != RISCV::ADDI)
- return false;
+ if (Base.getMachineOpcode() == RISCV::ADDI) {
+ // If the base is an ADDI, we can merge it in to the load/store.
+ } else if (Base.getMachineOpcode() == RISCV::ADDIW &&
+ isa<ConstantSDNode>(Base.getOperand(1)) &&
+ Base.getOperand(0).isMachineOpcode() &&
+ Base.getOperand(0).getMachineOpcode() == RISCV::LUI &&
+ isa<ConstantSDNode>(Base.getOperand(0).getOperand(0))) {
+ // ADDIW can be merged if it's part of LUI+ADDIW constant materialization
+ // and LUI+ADDI would have produced the same result. This is true for all
+ // simm32 values except 0x7ffff800-0x7fffffff.
+ int64_t Offset =
+ SignExtend64<32>(Base.getOperand(0).getConstantOperandVal(0) << 12);
+ Offset += cast<ConstantSDNode>(Base.getOperand(1))->getSExtValue();
+ if (!isInt<32>(Offset))
+ return false;
+ } else
+ return false;
SDValue ImmOperand = Base.getOperand(1);
uint64_t Offset2 = N->getConstantOperandVal(OffsetOpIdx);
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