[llvm] 485432f - [ARM] Make a narrow tMOVi8 where possible in SEH prologues

[Martin Storsjö via llvm-commits]

Author: Martin Storsjö
Date: 2022-06-03T22:33:55+03:00
New Revision: 485432f3c85a240e3fca23aad59ca44193c7113a

URL: https://github.com/llvm/llvm-project/commit/485432f3c85a240e3fca23aad59ca44193c7113a
DIFF: https://github.com/llvm/llvm-project/commit/485432f3c85a240e3fca23aad59ca44193c7113a.diff

LOG: [ARM] Make a narrow tMOVi8 where possible in SEH prologues

We intentionally disable Thumb2SizeReduction for SEH
prologues/epilogues, to avoid needing to guess what will happen with
the instructions in a potential future pass in frame lowering.

But for this specific case, where we know we can express the
intent with a narrow instruction, change to that instruction form
directly in frame lowering.

Differential Revision: https://reviews.llvm.org/D126949

Added: 
    

Modified: 
    llvm/lib/Target/ARM/ARMFrameLowering.cpp
    llvm/test/CodeGen/ARM/Windows/wineh-opcodes.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/ARM/ARMFrameLowering.cpp b/llvm/lib/Target/ARM/ARMFrameLowering.cpp
index a660c99dc96f8..014b81c1a653a 100644
--- a/llvm/lib/Target/ARM/ARMFrameLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMFrameLowering.cpp
@@ -301,7 +301,6 @@ static MachineBasicBlock::iterator insertSEH(MachineBasicBlock::iterator MBBI,
   case ARM::t2ADDri:   // add.w r11, sp, #xx
   case ARM::t2ADDri12: // add.w r11, sp, #xx
   case ARM::t2MOVTi16: // movt  r4, #xx
-  case ARM::t2MOVi16:  // movw  r4, #xx
   case ARM::tBL:       // bl __chkstk
     // These are harmless if used for just setting up a frame pointer,
     // but that frame pointer can't be relied upon for unwinding, unless
@@ -311,6 +310,23 @@ static MachineBasicBlock::iterator insertSEH(MachineBasicBlock::iterator MBBI,
               .setMIFlags(Flags);
     break;
 
+  case ARM::t2MOVi16: { // mov(w) r4, #xx
+    bool Wide = MBBI->getOperand(1).getImm() >= 256;
+    if (!Wide) {
+      MachineInstrBuilder NewInstr =
+          BuildMI(MF, DL, TII.get(ARM::tMOVi8)).setMIFlags(MBBI->getFlags());
+      NewInstr.add(MBBI->getOperand(0));
+      NewInstr.add(t1CondCodeOp(/*isDead=*/true));
+      for (unsigned i = 1, NumOps = MBBI->getNumOperands(); i != NumOps; ++i)
+        NewInstr.add(MBBI->getOperand(i));
+      MachineBasicBlock::iterator NewMBBI = MBB->insertAfter(MBBI, NewInstr);
+      MBB->erase(MBBI);
+      MBBI = NewMBBI;
+    }
+    MIB = BuildMI(MF, DL, TII.get(ARM::SEH_Nop)).addImm(Wide).setMIFlags(Flags);
+    break;
+  }
+
   case ARM::tBLXr: // blx r12 (__chkstk)
     MIB = BuildMI(MF, DL, TII.get(ARM::SEH_Nop))
               .addImm(/*Wide=*/0)

diff  --git a/llvm/test/CodeGen/ARM/Windows/wineh-opcodes.ll b/llvm/test/CodeGen/ARM/Windows/wineh-opcodes.ll
index ded0d8f7b6ea4..e97da669d65aa 100644
--- a/llvm/test/CodeGen/ARM/Windows/wineh-opcodes.ll
+++ b/llvm/test/CodeGen/ARM/Windows/wineh-opcodes.ll
@@ -249,8 +249,8 @@ entry:
 ; CHECK-NEXT: @ %bb.0:                                @ %entry
 ; CHECK-NEXT:         push    {r4, r5, r6, lr}
 ; CHECK-NEXT:         .seh_save_regs  {r4-r6, lr}
-; CHECK-NEXT:         movw    r4, #0
-; CHECK-NEXT:         .seh_nop_w
+; CHECK-NEXT:         movs    r4, #0
+; CHECK-NEXT:         .seh_nop
 ; CHECK-NEXT:         movt    r4, #1
 ; CHECK-NEXT:         .seh_nop_w
 ; CHECK-NEXT:         bl      __chkstk