[llvm] 170c550 - [RISCV] Use SelectionDAG::isBaseWithConstantOffset in scalar load/store address matching.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Fri Jun 3 11:02:13 PDT 2022
Author: Craig Topper
Date: 2022-06-03T10:55:28-07:00
New Revision: 170c550ca8e3c4174db4c8332257376bdc869a1c
URL: https://github.com/llvm/llvm-project/commit/170c550ca8e3c4174db4c8332257376bdc869a1c
DIFF: https://github.com/llvm/llvm-project/commit/170c550ca8e3c4174db4c8332257376bdc869a1c.diff
LOG: [RISCV] Use SelectionDAG::isBaseWithConstantOffset in scalar load/store address matching.
Test changes are because isBaseWithConstantOffset uses computeKnownBits
and that is able to see that an earlier AND instruction guaranteed
alignment so that we can treat an OR as an ADD.
Reviewed By: reames
Differential Revision: https://reviews.llvm.org/D126970
Added:
Modified:
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
llvm/test/CodeGen/RISCV/vararg.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index 6ddb75337bb90..2d7b652b00bd9 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -1863,19 +1863,17 @@ bool RISCVDAGToDAGISel::SelectFrameAddrRegImm(SDValue Addr, SDValue &Base,
return true;
}
- // TODO: Use SelectionDAG::isBaseWithConstantOffset.
- if (Addr.getOpcode() == ISD::ADD ||
- (Addr.getOpcode() == ISD::OR && isOrEquivalentToAdd(Addr.getNode()))) {
- if (auto *FIN = dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) {
- if (auto *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
- if (isInt<12>(CN->getSExtValue())) {
- Base = CurDAG->getTargetFrameIndex(FIN->getIndex(),
- Subtarget->getXLenVT());
- Offset = CurDAG->getTargetConstant(CN->getSExtValue(), SDLoc(Addr),
- Subtarget->getXLenVT());
- return true;
- }
- }
+ if (!CurDAG->isBaseWithConstantOffset(Addr))
+ return false;
+
+ if (auto *FIN = dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) {
+ auto *CN = cast<ConstantSDNode>(Addr.getOperand(1));
+ if (isInt<12>(CN->getSExtValue())) {
+ Base = CurDAG->getTargetFrameIndex(FIN->getIndex(),
+ Subtarget->getXLenVT());
+ Offset = CurDAG->getTargetConstant(CN->getSExtValue(), SDLoc(Addr),
+ Subtarget->getXLenVT());
+ return true;
}
}
@@ -1894,29 +1892,12 @@ bool RISCVDAGToDAGISel::SelectBaseAddr(SDValue Addr, SDValue &Base) {
bool RISCVDAGToDAGISel::SelectAddrRegImm(SDValue Addr, SDValue &Base,
SDValue &Offset) {
- if (Addr.getOpcode() == ISD::ADD) {
- if (auto *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
- if (isInt<12>(CN->getSExtValue())) {
- SelectBaseAddr(Addr.getOperand(0), Base);
- Offset = CurDAG->getTargetConstant(CN->getSExtValue(), SDLoc(Addr),
- Subtarget->getXLenVT());
- return true;
- }
- }
- } else if (Addr.getOpcode() == ISD::OR) {
- // We might be able to treat this OR as an ADD.
- // TODO: Use SelectionDAG::isBaseWithConstantOffset.
- if (auto *FIN = dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) {
- if (auto *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
- if (isInt<12>(CN->getSExtValue()) &&
- isOrEquivalentToAdd(Addr.getNode())) {
- Base = CurDAG->getTargetFrameIndex(FIN->getIndex(),
- Subtarget->getXLenVT());
- Offset = CurDAG->getTargetConstant(CN->getSExtValue(), SDLoc(Addr),
- Subtarget->getXLenVT());
- return true;
- }
- }
+ if (CurDAG->isBaseWithConstantOffset(Addr)) {
+ auto *CN = cast<ConstantSDNode>(Addr.getOperand(1));
+ if (isInt<12>(CN->getSExtValue())) {
+ Offset = CurDAG->getTargetConstant(CN->getSExtValue(), SDLoc(Addr),
+ Subtarget->getXLenVT());
+ return SelectBaseAddr(Addr.getOperand(0), Base);
}
}
diff --git a/llvm/test/CodeGen/RISCV/vararg.ll b/llvm/test/CodeGen/RISCV/vararg.ll
index 877fe12460cd1..cad6d19539f82 100644
--- a/llvm/test/CodeGen/RISCV/vararg.ll
+++ b/llvm/test/CodeGen/RISCV/vararg.ll
@@ -493,19 +493,18 @@ define i64 @va2(i8 *%fmt, ...) nounwind {
; ILP32-ILP32F-FPELIM: # %bb.0:
; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, -48
; ILP32-ILP32F-FPELIM-NEXT: sw a7, 44(sp)
-; ILP32-ILP32F-FPELIM-NEXT: sw a6, 40(sp)
; ILP32-ILP32F-FPELIM-NEXT: sw a5, 36(sp)
; ILP32-ILP32F-FPELIM-NEXT: sw a4, 32(sp)
; ILP32-ILP32F-FPELIM-NEXT: sw a3, 28(sp)
-; ILP32-ILP32F-FPELIM-NEXT: sw a2, 24(sp)
; ILP32-ILP32F-FPELIM-NEXT: sw a1, 20(sp)
+; ILP32-ILP32F-FPELIM-NEXT: sw a6, 40(sp)
+; ILP32-ILP32F-FPELIM-NEXT: sw a2, 24(sp)
; ILP32-ILP32F-FPELIM-NEXT: addi a0, sp, 27
-; ILP32-ILP32F-FPELIM-NEXT: andi a1, a0, -8
-; ILP32-ILP32F-FPELIM-NEXT: addi a0, sp, 35
-; ILP32-ILP32F-FPELIM-NEXT: sw a0, 12(sp)
-; ILP32-ILP32F-FPELIM-NEXT: lw a0, 0(a1)
-; ILP32-ILP32F-FPELIM-NEXT: ori a1, a1, 4
-; ILP32-ILP32F-FPELIM-NEXT: lw a1, 0(a1)
+; ILP32-ILP32F-FPELIM-NEXT: andi a0, a0, -8
+; ILP32-ILP32F-FPELIM-NEXT: addi a1, sp, 35
+; ILP32-ILP32F-FPELIM-NEXT: sw a1, 12(sp)
+; ILP32-ILP32F-FPELIM-NEXT: lw a1, 4(a0)
+; ILP32-ILP32F-FPELIM-NEXT: lw a0, 0(a0)
; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, 48
; ILP32-ILP32F-FPELIM-NEXT: ret
;
@@ -516,19 +515,18 @@ define i64 @va2(i8 *%fmt, ...) nounwind {
; ILP32-ILP32F-WITHFP-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; ILP32-ILP32F-WITHFP-NEXT: addi s0, sp, 16
; ILP32-ILP32F-WITHFP-NEXT: sw a7, 28(s0)
-; ILP32-ILP32F-WITHFP-NEXT: sw a6, 24(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a5, 20(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a4, 16(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a3, 12(s0)
-; ILP32-ILP32F-WITHFP-NEXT: sw a2, 8(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a1, 4(s0)
+; ILP32-ILP32F-WITHFP-NEXT: sw a6, 24(s0)
+; ILP32-ILP32F-WITHFP-NEXT: sw a2, 8(s0)
; ILP32-ILP32F-WITHFP-NEXT: addi a0, s0, 11
-; ILP32-ILP32F-WITHFP-NEXT: andi a1, a0, -8
-; ILP32-ILP32F-WITHFP-NEXT: addi a0, s0, 19
-; ILP32-ILP32F-WITHFP-NEXT: sw a0, -12(s0)
-; ILP32-ILP32F-WITHFP-NEXT: lw a0, 0(a1)
-; ILP32-ILP32F-WITHFP-NEXT: ori a1, a1, 4
-; ILP32-ILP32F-WITHFP-NEXT: lw a1, 0(a1)
+; ILP32-ILP32F-WITHFP-NEXT: andi a0, a0, -8
+; ILP32-ILP32F-WITHFP-NEXT: addi a1, s0, 19
+; ILP32-ILP32F-WITHFP-NEXT: sw a1, -12(s0)
+; ILP32-ILP32F-WITHFP-NEXT: lw a1, 4(a0)
+; ILP32-ILP32F-WITHFP-NEXT: lw a0, 0(a0)
; ILP32-ILP32F-WITHFP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; ILP32-ILP32F-WITHFP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, 48
@@ -538,19 +536,18 @@ define i64 @va2(i8 *%fmt, ...) nounwind {
; RV32D-ILP32-ILP32F-ILP32D-FPELIM: # %bb.0:
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, -48
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a7, 44(sp)
-; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a6, 40(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a5, 36(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a4, 32(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a3, 28(sp)
-; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a2, 24(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a1, 20(sp)
+; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a6, 40(sp)
+; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a2, 24(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a0, sp, 27
-; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: andi a1, a0, -8
-; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a0, sp, 35
-; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a0, 12(sp)
-; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lw a0, 0(a1)
-; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: ori a1, a1, 4
-; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lw a1, 0(a1)
+; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: andi a0, a0, -8
+; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a1, sp, 35
+; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a1, 12(sp)
+; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lw a1, 4(a0)
+; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lw a0, 0(a0)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, 48
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: ret
;
@@ -640,12 +637,12 @@ define i64 @va2_va_arg(i8 *%fmt, ...) nounwind {
; ILP32-ILP32F-FPELIM-NEXT: sw a1, 20(sp)
; ILP32-ILP32F-FPELIM-NEXT: addi a0, sp, 27
; ILP32-ILP32F-FPELIM-NEXT: andi a1, a0, -8
-; ILP32-ILP32F-FPELIM-NEXT: ori a2, a1, 4
-; ILP32-ILP32F-FPELIM-NEXT: sw a2, 12(sp)
+; ILP32-ILP32F-FPELIM-NEXT: ori a0, a1, 4
+; ILP32-ILP32F-FPELIM-NEXT: sw a0, 12(sp)
; ILP32-ILP32F-FPELIM-NEXT: lw a0, 0(a1)
-; ILP32-ILP32F-FPELIM-NEXT: addi a1, a1, 8
-; ILP32-ILP32F-FPELIM-NEXT: sw a1, 12(sp)
-; ILP32-ILP32F-FPELIM-NEXT: lw a1, 0(a2)
+; ILP32-ILP32F-FPELIM-NEXT: addi a2, a1, 8
+; ILP32-ILP32F-FPELIM-NEXT: sw a2, 12(sp)
+; ILP32-ILP32F-FPELIM-NEXT: lw a1, 4(a1)
; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, 48
; ILP32-ILP32F-FPELIM-NEXT: ret
;
@@ -664,12 +661,12 @@ define i64 @va2_va_arg(i8 *%fmt, ...) nounwind {
; ILP32-ILP32F-WITHFP-NEXT: sw a1, 4(s0)
; ILP32-ILP32F-WITHFP-NEXT: addi a0, s0, 11
; ILP32-ILP32F-WITHFP-NEXT: andi a1, a0, -8
-; ILP32-ILP32F-WITHFP-NEXT: ori a2, a1, 4
-; ILP32-ILP32F-WITHFP-NEXT: sw a2, -12(s0)
+; ILP32-ILP32F-WITHFP-NEXT: ori a0, a1, 4
+; ILP32-ILP32F-WITHFP-NEXT: sw a0, -12(s0)
; ILP32-ILP32F-WITHFP-NEXT: lw a0, 0(a1)
-; ILP32-ILP32F-WITHFP-NEXT: addi a1, a1, 8
-; ILP32-ILP32F-WITHFP-NEXT: sw a1, -12(s0)
-; ILP32-ILP32F-WITHFP-NEXT: lw a1, 0(a2)
+; ILP32-ILP32F-WITHFP-NEXT: addi a2, a1, 8
+; ILP32-ILP32F-WITHFP-NEXT: sw a2, -12(s0)
+; ILP32-ILP32F-WITHFP-NEXT: lw a1, 4(a1)
; ILP32-ILP32F-WITHFP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; ILP32-ILP32F-WITHFP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, 48
@@ -814,20 +811,19 @@ define i64 @va3(i32 %a, i64 %b, ...) nounwind {
; ILP32-ILP32F-FPELIM: # %bb.0:
; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, -32
; ILP32-ILP32F-FPELIM-NEXT: sw a7, 28(sp)
+; ILP32-ILP32F-FPELIM-NEXT: sw a6, 24(sp)
; ILP32-ILP32F-FPELIM-NEXT: sw a5, 20(sp)
; ILP32-ILP32F-FPELIM-NEXT: sw a4, 16(sp)
; ILP32-ILP32F-FPELIM-NEXT: sw a3, 12(sp)
-; ILP32-ILP32F-FPELIM-NEXT: sw a6, 24(sp)
; ILP32-ILP32F-FPELIM-NEXT: addi a0, sp, 19
; ILP32-ILP32F-FPELIM-NEXT: andi a0, a0, -8
; ILP32-ILP32F-FPELIM-NEXT: addi a3, sp, 27
; ILP32-ILP32F-FPELIM-NEXT: sw a3, 4(sp)
-; ILP32-ILP32F-FPELIM-NEXT: lw a3, 0(a0)
-; ILP32-ILP32F-FPELIM-NEXT: ori a0, a0, 4
-; ILP32-ILP32F-FPELIM-NEXT: lw a4, 0(a0)
-; ILP32-ILP32F-FPELIM-NEXT: add a0, a1, a3
+; ILP32-ILP32F-FPELIM-NEXT: lw a3, 4(a0)
+; ILP32-ILP32F-FPELIM-NEXT: lw a0, 0(a0)
+; ILP32-ILP32F-FPELIM-NEXT: add a2, a2, a3
+; ILP32-ILP32F-FPELIM-NEXT: add a0, a1, a0
; ILP32-ILP32F-FPELIM-NEXT: sltu a1, a0, a1
-; ILP32-ILP32F-FPELIM-NEXT: add a2, a2, a4
; ILP32-ILP32F-FPELIM-NEXT: add a1, a2, a1
; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, 32
; ILP32-ILP32F-FPELIM-NEXT: ret
@@ -839,20 +835,19 @@ define i64 @va3(i32 %a, i64 %b, ...) nounwind {
; ILP32-ILP32F-WITHFP-NEXT: sw s0, 16(sp) # 4-byte Folded Spill
; ILP32-ILP32F-WITHFP-NEXT: addi s0, sp, 24
; ILP32-ILP32F-WITHFP-NEXT: sw a7, 20(s0)
+; ILP32-ILP32F-WITHFP-NEXT: sw a6, 16(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a5, 12(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a4, 8(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a3, 4(s0)
-; ILP32-ILP32F-WITHFP-NEXT: sw a6, 16(s0)
; ILP32-ILP32F-WITHFP-NEXT: addi a0, s0, 11
; ILP32-ILP32F-WITHFP-NEXT: andi a0, a0, -8
; ILP32-ILP32F-WITHFP-NEXT: addi a3, s0, 19
; ILP32-ILP32F-WITHFP-NEXT: sw a3, -12(s0)
-; ILP32-ILP32F-WITHFP-NEXT: lw a3, 0(a0)
-; ILP32-ILP32F-WITHFP-NEXT: ori a0, a0, 4
-; ILP32-ILP32F-WITHFP-NEXT: lw a4, 0(a0)
-; ILP32-ILP32F-WITHFP-NEXT: add a0, a1, a3
+; ILP32-ILP32F-WITHFP-NEXT: lw a3, 4(a0)
+; ILP32-ILP32F-WITHFP-NEXT: lw a0, 0(a0)
+; ILP32-ILP32F-WITHFP-NEXT: add a2, a2, a3
+; ILP32-ILP32F-WITHFP-NEXT: add a0, a1, a0
; ILP32-ILP32F-WITHFP-NEXT: sltu a1, a0, a1
-; ILP32-ILP32F-WITHFP-NEXT: add a2, a2, a4
; ILP32-ILP32F-WITHFP-NEXT: add a1, a2, a1
; ILP32-ILP32F-WITHFP-NEXT: lw ra, 20(sp) # 4-byte Folded Reload
; ILP32-ILP32F-WITHFP-NEXT: lw s0, 16(sp) # 4-byte Folded Reload
@@ -863,20 +858,19 @@ define i64 @va3(i32 %a, i64 %b, ...) nounwind {
; RV32D-ILP32-ILP32F-ILP32D-FPELIM: # %bb.0:
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, -32
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a7, 28(sp)
+; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a6, 24(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a5, 20(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a4, 16(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a3, 12(sp)
-; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a6, 24(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a0, sp, 19
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: andi a0, a0, -8
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a3, sp, 27
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a3, 4(sp)
-; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lw a3, 0(a0)
-; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: ori a0, a0, 4
-; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lw a4, 0(a0)
-; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: add a0, a1, a3
+; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lw a3, 4(a0)
+; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lw a0, 0(a0)
+; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: add a2, a2, a3
+; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: add a0, a1, a0
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sltu a1, a0, a1
-; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: add a2, a2, a4
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: add a1, a2, a1
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, 32
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: ret
@@ -968,13 +962,13 @@ define i64 @va3_va_arg(i32 %a, i64 %b, ...) nounwind {
; ILP32-ILP32F-FPELIM-NEXT: andi a0, a0, -8
; ILP32-ILP32F-FPELIM-NEXT: ori a3, a0, 4
; ILP32-ILP32F-FPELIM-NEXT: sw a3, 4(sp)
-; ILP32-ILP32F-FPELIM-NEXT: lw a4, 0(a0)
-; ILP32-ILP32F-FPELIM-NEXT: addi a0, a0, 8
-; ILP32-ILP32F-FPELIM-NEXT: sw a0, 4(sp)
-; ILP32-ILP32F-FPELIM-NEXT: lw a3, 0(a3)
-; ILP32-ILP32F-FPELIM-NEXT: add a0, a1, a4
+; ILP32-ILP32F-FPELIM-NEXT: lw a3, 0(a0)
+; ILP32-ILP32F-FPELIM-NEXT: addi a4, a0, 8
+; ILP32-ILP32F-FPELIM-NEXT: sw a4, 4(sp)
+; ILP32-ILP32F-FPELIM-NEXT: lw a4, 4(a0)
+; ILP32-ILP32F-FPELIM-NEXT: add a0, a1, a3
; ILP32-ILP32F-FPELIM-NEXT: sltu a1, a0, a1
-; ILP32-ILP32F-FPELIM-NEXT: add a2, a2, a3
+; ILP32-ILP32F-FPELIM-NEXT: add a2, a2, a4
; ILP32-ILP32F-FPELIM-NEXT: add a1, a2, a1
; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, 32
; ILP32-ILP32F-FPELIM-NEXT: ret
@@ -994,13 +988,13 @@ define i64 @va3_va_arg(i32 %a, i64 %b, ...) nounwind {
; ILP32-ILP32F-WITHFP-NEXT: andi a0, a0, -8
; ILP32-ILP32F-WITHFP-NEXT: ori a3, a0, 4
; ILP32-ILP32F-WITHFP-NEXT: sw a3, -12(s0)
-; ILP32-ILP32F-WITHFP-NEXT: lw a4, 0(a0)
-; ILP32-ILP32F-WITHFP-NEXT: addi a0, a0, 8
-; ILP32-ILP32F-WITHFP-NEXT: sw a0, -12(s0)
-; ILP32-ILP32F-WITHFP-NEXT: lw a3, 0(a3)
-; ILP32-ILP32F-WITHFP-NEXT: add a0, a1, a4
+; ILP32-ILP32F-WITHFP-NEXT: lw a3, 0(a0)
+; ILP32-ILP32F-WITHFP-NEXT: addi a4, a0, 8
+; ILP32-ILP32F-WITHFP-NEXT: sw a4, -12(s0)
+; ILP32-ILP32F-WITHFP-NEXT: lw a4, 4(a0)
+; ILP32-ILP32F-WITHFP-NEXT: add a0, a1, a3
; ILP32-ILP32F-WITHFP-NEXT: sltu a1, a0, a1
-; ILP32-ILP32F-WITHFP-NEXT: add a2, a2, a3
+; ILP32-ILP32F-WITHFP-NEXT: add a2, a2, a4
; ILP32-ILP32F-WITHFP-NEXT: add a1, a2, a1
; ILP32-ILP32F-WITHFP-NEXT: lw ra, 20(sp) # 4-byte Folded Reload
; ILP32-ILP32F-WITHFP-NEXT: lw s0, 16(sp) # 4-byte Folded Reload
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