[PATCH] D126932: [RISCV] Reduce scalar load/store isel patterns to a single ComplexPattern. NFCI

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp:1920
+    // We might be able to treat this OR as an ADD.
+    if (auto *FIN = dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) {
+      if (auto *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
----------------
reames wrote:
> Why does this case need to be restricted to frame index?  I think you maybe copy pasted this and didn't adjust?
This was an attempt to preserve the original isel pattern. isOrEquivalentToAdd only handles frame index and the isel pattern used AddrFI.

I'm considering using the more powerful SelectionDAG::isBaseWithConstantOffset that uses computeKnownBits for OR instead of special casing FrameIndex.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D126932/new/

https://reviews.llvm.org/D126932