[PATCH] D126794: [RISCV] Lower VLEFF/VLSEGFF SDNodes to MachineInstrs with VL outputs.

[Yeting Kuo via Phabricator via llvm-commits]

fakepaper56 marked an inline comment as done.
fakepaper56 added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp:1439
+          BuildMI(MBB, I, DL, TII->get(NewOpc), MI.getOperand(0).getReg());
+      unsigned Cur = 2;
+
----------------
reames wrote:
> It looks like this block of code is just copying all the operands right?  If so, simpler to write it that way.
Done.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D126794/new/

https://reviews.llvm.org/D126794