[PATCH] D126949: [ARM] Make a narrow tMOVi8 where possible in SEH prologues

[Martin Storsjö via Phabricator via llvm-commits]

mstorsjo created this revision.
mstorsjo added reviewers: efriedma, zzheng.
Herald added subscribers: hiraditya, kristof.beyls.
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This does the same as D126948 <https://reviews.llvm.org/D126948>, but for t2MOVi16. I guess it's not
strictly necessary though, as the overhead of this should be quite
minimal compared to the pushes/pops.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D126949

Files:
  llvm/lib/Target/ARM/ARMFrameLowering.cpp
  llvm/test/CodeGen/ARM/Windows/wineh-opcodes.ll


Index: llvm/test/CodeGen/ARM/Windows/wineh-opcodes.ll
===================================================================
--- llvm/test/CodeGen/ARM/Windows/wineh-opcodes.ll
+++ llvm/test/CodeGen/ARM/Windows/wineh-opcodes.ll
@@ -249,8 +249,8 @@
 ; CHECK-NEXT: @ %bb.0:                                @ %entry
 ; CHECK-NEXT:         push    {r4, r5, r6, lr}
 ; CHECK-NEXT:         .seh_save_regs  {r4-r6, lr}
-; CHECK-NEXT:         movw    r4, #0
-; CHECK-NEXT:         .seh_nop_w
+; CHECK-NEXT:         movs    r4, #0
+; CHECK-NEXT:         .seh_nop
 ; CHECK-NEXT:         movt    r4, #1
 ; CHECK-NEXT:         .seh_nop_w
 ; CHECK-NEXT:         bl      __chkstk
Index: llvm/lib/Target/ARM/ARMFrameLowering.cpp
===================================================================
--- llvm/lib/Target/ARM/ARMFrameLowering.cpp
+++ llvm/lib/Target/ARM/ARMFrameLowering.cpp
@@ -301,7 +301,6 @@
   case ARM::t2ADDri:   // add.w r11, sp, #xx
   case ARM::t2ADDri12: // add.w r11, sp, #xx
   case ARM::t2MOVTi16: // movt  r4, #xx
-  case ARM::t2MOVi16:  // movw  r4, #xx
   case ARM::tBL:       // bl __chkstk
     // These are harmless if used for just setting up a frame pointer,
     // but that frame pointer can't be relied upon for unwinding, unless
@@ -311,6 +310,23 @@
               .setMIFlags(Flags);
     break;
 
+  case ARM::t2MOVi16: { // mov(w) r4, #xx
+    bool Wide = MBBI->getOperand(1).getImm() >= 256;
+    if (!Wide) {
+      MachineInstrBuilder NewInstr =
+          BuildMI(MF, DL, TII.get(ARM::tMOVi8)).setMIFlags(MBBI->getFlags());
+      NewInstr.add(MBBI->getOperand(0));
+      NewInstr.add(t1CondCodeOp(/*isDead=*/true));
+      for (unsigned i = 1, NumOps = MBBI->getNumOperands(); i != NumOps; ++i)
+        NewInstr.add(MBBI->getOperand(i));
+      MachineBasicBlock::iterator NewMBBI = MBB->insertAfter(MBBI, NewInstr);
+      MBB->erase(MBBI);
+      MBBI = NewMBBI;
+    }
+    MIB = BuildMI(MF, DL, TII.get(ARM::SEH_Nop)).addImm(Wide).setMIFlags(Flags);
+    break;
+  }
+
   case ARM::tBLXr: // blx r12 (__chkstk)
     MIB = BuildMI(MF, DL, TII.get(ARM::SEH_Nop))
               .addImm(/*Wide=*/0)


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