[PATCH] D126794: [RISCV] Lower VLEFF/VLSEGFF SDNodes to MachineInstrs with VL outputs.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp:1438
+      MachineInstrBuilder MIB =
+          BuildMI(MBB, I, DL, TII->get(NewOpc), MI.getOperand(0).getReg());
+      unsigned Cur = 2;
----------------
reames wrote:
> Did you play with what happens if you just set the second destination register to VL?
> 
> If that works, then we'd avoid the need for the second set of pseudos.  Not sure it does, but maybe?
The register class wouldn't match, so I doubt it would work.

Might be able to use an OptionalDef though?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D126794/new/

https://reviews.llvm.org/D126794