[PATCH] D126921: [RISCV] Untangle instruction properties from VSETVLIInfo [NFC]
Philip Reames via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Jun 2 14:10:16 PDT 2022
reames created this revision.
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The abstract state used in the data flow should not know anything about the instructions which produced the abstract states. Instead, when comparing two states, we can simply use information about the machine instr at that time.
In the old design, basically any use of the instruction flags on the current (as opposed to a "Require" - aka upcoming state) would be a bug. We don't seem to actually have any such bugs, but we can make this much more obvious with code structure.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D126921
Files:
llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
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