[PATCH] D126914: [BOLT][NFC] Simplify MCPlusBuilder::getRegSize
Amir Ayupov via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Jun 2 13:28:24 PDT 2022
Amir created this revision.
Herald added a reviewer: rafauler.
Herald added a subscriber: ayermolo.
Herald added a reviewer: maksfb.
Herald added a project: All.
Amir requested review of this revision.
Herald added subscribers: llvm-commits, yota9.
Herald added a project: LLVM.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D126914
Files:
bolt/lib/Core/MCPlusBuilder.cpp
Index: bolt/lib/Core/MCPlusBuilder.cpp
===================================================================
--- bolt/lib/Core/MCPlusBuilder.cpp
+++ bolt/lib/Core/MCPlusBuilder.cpp
@@ -494,16 +494,13 @@
// SizeMap caches a mapping of registers to their sizes
static std::vector<uint8_t> SizeMap;
- if (SizeMap.size() > 0) {
+ if (SizeMap.size() > 0)
return SizeMap[Reg];
- }
+
SizeMap = std::vector<uint8_t>(RegInfo->getNumRegs());
// Build size map
- for (auto I = RegInfo->regclass_begin(), E = RegInfo->regclass_end(); I != E;
- ++I) {
- for (MCPhysReg Reg : *I)
- SizeMap[Reg] = I->getSizeInBits() / 8;
- }
+ for (const MCRegisterClass &RC : RegInfo->regclasses())
+ for_each(RC, [&](MCPhysReg Reg) { SizeMap[Reg] = RC.getSizeInBits() / 8; });
return SizeMap[Reg];
}
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