[PATCH] D126576: [RISCV] Add custom isel for (add X, imm) used by load/stores.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

In D126576#3554172 <https://reviews.llvm.org/D126576#3554172>, @reames wrote:

> LGTM
>
> Not entirely thrilled with this, but don't want perfection to be the enemy of the good here.  We can take this and continue to think about other approaches to the problem.

Part of me wonders if we should move load/store addressing match to ComplexPat that finds the register and offset. Similar to how we do address matching on X86. I think that would allow us to remove the late peephole. Does that sound like a direction I should investigate?


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https://reviews.llvm.org/D126576