[PATCH] D125271: [riscv] Enable strict assertions in InsertVSETVLI data flow

Thu Jun 2 08:18:37 PDT 2022

reames added a comment.

In D125271#3549187 <https://reviews.llvm.org/D125271#3549187>, @pcwang-thead wrote:

> In D125271#3547840 <https://reviews.llvm.org/D125271#3547840>, @reames wrote:
>
>> In D125271#3544933 <https://reviews.llvm.org/D125271#3544933>, @pcwang-thead wrote:
>>
>>> @reames can you take a look at this?
>>
>> Happy to, but first I need a stand alone reproducer.
>>
>> I tried your LL file, and did not see a crash on the following command line:
>> ./llc -O3 -march=riscv64 < <your-ir>
>>
>> Please provide the exact llc command line you saw a failure with.
>
> Thanks! The command is: `llc -O2 -march=riscv64 -mattr=+v -riscv-v-vector-bits-max=128 -riscv-v-vector-bits-min=128 reduced.ll`. The key is that we will get crash if `vector-bits` is specified.
> And here is an example on Compiler Explorer: https://godbolt.org/z/41x691Y6x

This appears to have been a duplicate of the issue fixed in dcdb0bf <https://reviews.llvm.org/rGdcdb0bf25bc83e4ae4e7da87311dd93030e9c9ce>.  Can you confirm that the original issue is resolved for you?

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https://reviews.llvm.org/D125271