[PATCH] D126854: [RISCV] Define risc-v's own register class to model FP Register.

[Kito Cheng via Phabricator via llvm-commits]

kito-cheng added inline comments.


================
Comment at: llvm/test/Transforms/LoopVectorize/RISCV/reg-usage.ll:22
 ; CHECK-LMUL1:      LV(REG): Found max usage: 2 item
-; CHECK-LMUL1-NEXT: LV(REG): RegisterClass: Generic::ScalarRC, 2 registers
-; CHECK-LMUL1-NEXT: LV(REG): RegisterClass: Generic::VectorRC, 2 registers
+; CHECK-LMUL1-NEXT: LV(REG): RegisterClass: RISCV::GPRRC, 2 registers
+; CHECK-LMUL1-NEXT: LV(REG): RegisterClass: RISCV::VRRC, 2 registers
----------------
ym1813382441 wrote:
> kito-cheng wrote:
> > Curious why there is still `GPRRC` here? I thought that should be `FPRRC` after this patch?
> Here is the register usage after VF is selected, all float types in this loop has been changed to the vector type after vectorization.
> Only Uniform and Scalar instructions after vectorization are computed into scalar registers.
> The output here may not be complete enough to cause you to misunderstand.
Yeah, make sense, does it possible to add some testcase to show `FPRRC`?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D126854/new/

https://reviews.llvm.org/D126854