[PATCH] D98002: [RISCV] Add scheduling resources for V

[Zixuan Wu via Phabricator via llvm-commits]

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In D98002#2657460 <https://reviews.llvm.org/D98002#2657460>, @evandro wrote:

> In D98002#2657389 <https://reviews.llvm.org/D98002#2657389>, @NickHung wrote:
>
>> Adding those "sched" information into base RVV instructions seems redundant? The scheduler works on PseudoRVV instructions.
>
> Not redundant, as some tools do use the information at this level, e.g., `llvm-mca`.
>
> Moreover, this patch captures the resources in a way that it makes it easier to add latency information to specific targets later.
>
>> SchedReadWrite needs to consider pseudo instructions with LMUL? Their latency should be different.
>
> And SEW.  I'm working on this feature, of which this patch introduces the preliminary information.

Hi, I am wondering is there any patch to construct Write/Read Sched for pseudo instructions with every different LMUL now? @evandro


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