[PATCH] D126854: [RISCV] Define risc-v's own register class to model FP Register.

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The default RegisterClass is not enough to model RISCV Register.
We define risc-v's own register class to model FP Register.
This helps to better estimate the register pressure in the loop-vectorize.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D126854

Files:
  llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
  llvm/test/Transforms/LoopVectorize/RISCV/reg-usage.ll

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