[PATCH] D125648: [ARM SEH 6] [ARM] Add SEH opcodes in frame lowering

[Eli Friedman via Phabricator via llvm-commits]

efriedma added inline comments.


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Comment at: llvm/lib/Target/ARM/ARMFrameLowering.cpp:315
+  case ARM::t2MOVi16: { // mov(w) r4, #xx
+    bool Wide = MBBI->getOperand(1).getImm() >= 256;
+    MIB = BuildMI(MF, DL, TII.get(ARM::SEH_Nop)).addImm(Wide).setMIFlags(Flags);
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Looking at this again, this is actually sort of scary.  In particular, this is dependent on looking into the future: trying to predict what Thumb2SizeReduction will do with a given instruction. Which is at best fragile, at worst broken if Thumb2SizeReduction doesn't run, or decides to do something different.

I guess you can sort of predict what will happen for t2MOVi16 and t2LDMIA_RET/t2LDMIA_UPD/t2STMDB_UPD.  But it's less clear in other cases; we currently don't optimize t2SUBspImm, but we could.  Or for TCRETURNdi, we don't actually decide the size until we hit the assembler.

I'm thinking we might want to disable Thumb2SizeReduction on instructions with SEH opcodes.  (Or equivalently, on FrameSetup instructions if SEH unwind is enabled.)


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D125648/new/

https://reviews.llvm.org/D125648