[llvm] a0dcbe4 - llvm-reduce: Add reduction pass to remove regalloc hints
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Wed Jun 1 06:19:28 PDT 2022
Author: Matt Arsenault
Date: 2022-06-01T09:15:41-04:00
New Revision: a0dcbe45bd8387da51f94e4d171c3ecc3d266e64
URL: https://github.com/llvm/llvm-project/commit/a0dcbe45bd8387da51f94e4d171c3ecc3d266e64
DIFF: https://github.com/llvm/llvm-project/commit/a0dcbe45bd8387da51f94e4d171c3ecc3d266e64.diff
LOG: llvm-reduce: Add reduction pass to remove regalloc hints
I'm a bit confused by what's actually stored for the allocation
hints. The MIR parser only handles the "simple" case where there's a
single hint. I don't really understand the assertion in
clearSimpleHint, or under what circumstances there are multiple hint
registers.
Added:
llvm/test/tools/llvm-reduce/mir/reduce-register-hints.mir
llvm/tools/llvm-reduce/deltas/ReduceVirtualRegisters.cpp
llvm/tools/llvm-reduce/deltas/ReduceVirtualRegisters.h
Modified:
llvm/test/tools/llvm-reduce/mir/preserve-reg-hints.mir
llvm/tools/llvm-reduce/CMakeLists.txt
llvm/tools/llvm-reduce/DeltaManager.cpp
llvm/tools/llvm-reduce/ReducerWorkItem.cpp
Removed:
################################################################################
diff --git a/llvm/test/tools/llvm-reduce/mir/preserve-reg-hints.mir b/llvm/test/tools/llvm-reduce/mir/preserve-reg-hints.mir
index 72dd027c45e2..2589be95b09a 100644
--- a/llvm/test/tools/llvm-reduce/mir/preserve-reg-hints.mir
+++ b/llvm/test/tools/llvm-reduce/mir/preserve-reg-hints.mir
@@ -1,5 +1,5 @@
# REQUIRES: amdgpu-registered-target
-# RUN: llvm-reduce -mtriple=amdgcn-amd-amdhsa --test FileCheck --test-arg --check-prefix=CHECK-INTERESTINGNESS --test-arg %s --test-arg --input-file %s -o %t 2> %t.log
+# RUN: llvm-reduce -mtriple=amdgcn-amd-amdhsa --delta-passes=instructions --test FileCheck --test-arg --check-prefix=CHECK-INTERESTINGNESS --test-arg %s --test-arg --input-file %s -o %t 2> %t.log
# RUN: FileCheck --match-full-lines --check-prefix=RESULT %s < %t
# CHECK-INTERESTINGNESS: S_NOP 0
diff --git a/llvm/test/tools/llvm-reduce/mir/reduce-register-hints.mir b/llvm/test/tools/llvm-reduce/mir/reduce-register-hints.mir
new file mode 100644
index 000000000000..5d6fd45c17bc
--- /dev/null
+++ b/llvm/test/tools/llvm-reduce/mir/reduce-register-hints.mir
@@ -0,0 +1,38 @@
+# REQUIRES: amdgpu-registered-target
+# RUN: llvm-reduce -simplify-mir --delta-passes=register-hints -mtriple=amdgcn-amd-amdhsa --test FileCheck --test-arg --check-prefix=CHECK-INTERESTINGNESS --test-arg %s --test-arg --input-file %s -o %t 2> %t.log
+# RUN: FileCheck --check-prefix=RESULT %s < %t
+
+# CHECK-INTERESTINGNESS: - { id: 0, class: vgpr_32, preferred-register: '$vgpr0' }
+# CHECK-INTERESTINGNESS: - { id: 2, class: vgpr_32, preferred-register: '%1' }
+# CHECK-INTERESTINGNESS-COUNT-5: V_MOV_B32
+
+# RESULT: registers:
+# RESULT-NEXT: - { id: 0, class: vgpr_32, preferred-register: '$vgpr0' }
+# RESULT-NEXT: - { id: 1, class: vgpr_32 }
+# RESULT-NEXT: - { id: 2, class: vgpr_32, preferred-register: '%1' }
+# RESULT-NEXT: - { id: 3, class: vgpr_32 }
+# RESULT-NEXT: - { id: 4, class: vgpr_32 }
+
+---
+name: func
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: vgpr_32, preferred-register: '$vgpr0' }
+ - { id: 1, class: vgpr_32, preferred-register: '' }
+ - { id: 2, class: vgpr_32, preferred-register: '%1' }
+ - { id: 3, class: vgpr_32, preferred-register: '%4' }
+ - { id: 4, class: vgpr_32, preferred-register: '%3' }
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1
+
+ S_WAITCNT 0
+ %0:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+ %1:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
+ %2:vgpr_32 = V_MOV_B32_e32 2, implicit $exec
+ %3:vgpr_32 = V_MOV_B32_e32 3, implicit $exec
+ %4:vgpr_32 = V_MOV_B32_e32 4, implicit $exec
+ S_NOP 0
+ S_ENDPGM 0, implicit %0, implicit %1, implicit %2, implicit %3, implicit %4
+...
+
diff --git a/llvm/tools/llvm-reduce/CMakeLists.txt b/llvm/tools/llvm-reduce/CMakeLists.txt
index 21151d7e4708..b077f1849898 100644
--- a/llvm/tools/llvm-reduce/CMakeLists.txt
+++ b/llvm/tools/llvm-reduce/CMakeLists.txt
@@ -41,6 +41,7 @@ add_llvm_tool(llvm-reduce
deltas/ReduceInstructionsMIR.cpp
deltas/ReduceInstructionFlagsMIR.cpp
deltas/ReduceIRReferences.cpp
+ deltas/ReduceVirtualRegisters.cpp
llvm-reduce.cpp
DEPENDS
diff --git a/llvm/tools/llvm-reduce/DeltaManager.cpp b/llvm/tools/llvm-reduce/DeltaManager.cpp
index a5b6c1779eb9..ed9d105223db 100644
--- a/llvm/tools/llvm-reduce/DeltaManager.cpp
+++ b/llvm/tools/llvm-reduce/DeltaManager.cpp
@@ -35,6 +35,7 @@
#include "deltas/ReduceOperandsSkip.h"
#include "deltas/ReduceOperandsToArgs.h"
#include "deltas/ReduceSpecialGlobals.h"
+#include "deltas/ReduceVirtualRegisters.h"
#include "llvm/Support/CommandLine.h"
using namespace llvm;
@@ -74,7 +75,8 @@ static cl::opt<std::string>
reduceIRInstructionReferencesDeltaPass) \
DELTA_PASS("ir-block-references", reduceIRBlockReferencesDeltaPass) \
DELTA_PASS("ir-function-references", reduceIRFunctionReferencesDeltaPass) \
- DELTA_PASS("instruction-flags", reduceInstructionFlagsMIRDeltaPass)
+ DELTA_PASS("instruction-flags", reduceInstructionFlagsMIRDeltaPass) \
+ DELTA_PASS("register-hints", reduceVirtualRegisterHintsDeltaPass)
static void runAllDeltaPasses(TestRunner &Tester) {
#define DELTA_PASS(NAME, FUNC) FUNC(Tester);
diff --git a/llvm/tools/llvm-reduce/ReducerWorkItem.cpp b/llvm/tools/llvm-reduce/ReducerWorkItem.cpp
index 91ea75268479..fbae2a6ba849 100644
--- a/llvm/tools/llvm-reduce/ReducerWorkItem.cpp
+++ b/llvm/tools/llvm-reduce/ReducerWorkItem.cpp
@@ -496,6 +496,12 @@ static uint64_t computeMIRComplexityScoreImpl(const MachineFunction &MF) {
// Add in the block count.
Score += 2 * MF.size();
+ const MachineRegisterInfo &MRI = MF.getRegInfo();
+ for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) {
+ Register Reg = Register::index2VirtReg(I);
+ Score += MRI.getRegAllocationHints(Reg).second.size();
+ }
+
for (const MachineBasicBlock &MBB : MF) {
for (const MachineInstr &MI : MBB) {
const unsigned Opc = MI.getOpcode();
diff --git a/llvm/tools/llvm-reduce/deltas/ReduceVirtualRegisters.cpp b/llvm/tools/llvm-reduce/deltas/ReduceVirtualRegisters.cpp
new file mode 100644
index 000000000000..1c5bda8ac33b
--- /dev/null
+++ b/llvm/tools/llvm-reduce/deltas/ReduceVirtualRegisters.cpp
@@ -0,0 +1,46 @@
+//===- ReduceVirtualRegisters.cpp - Specialized Delta Pass ----------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements a function which calls the Generic Delta pass in order
+// to simplify virtual registers in MIR.
+//
+//===----------------------------------------------------------------------===//
+
+#include "ReduceVirtualRegisters.h"
+#include "Delta.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
+
+using namespace llvm;
+
+static void dropRegisterHintsFromFunction(Oracle &O, MachineFunction &MF) {
+ MachineRegisterInfo &MRI = MF.getRegInfo();
+ for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) {
+ Register Reg = Register::index2VirtReg(I);
+
+ const std::pair<Register, SmallVector<Register, 4>> &Hints =
+ MRI.getRegAllocationHints(Reg);
+ if (Hints.second.empty())
+ continue;
+
+ if (!O.shouldKeep())
+ MRI.clearSimpleHint(Reg);
+ }
+}
+
+static void dropRegisterHintsFromFunctions(Oracle &O,
+ ReducerWorkItem &WorkItem) {
+ for (const Function &F : WorkItem.getModule()) {
+ if (auto *MF = WorkItem.MMI->getMachineFunction(F))
+ dropRegisterHintsFromFunction(O, *MF);
+ }
+}
+
+void llvm::reduceVirtualRegisterHintsDeltaPass(TestRunner &Test) {
+ outs() << "*** Reducing virtual register hints from functions...\n";
+ runDeltaPass(Test, dropRegisterHintsFromFunctions);
+}
diff --git a/llvm/tools/llvm-reduce/deltas/ReduceVirtualRegisters.h b/llvm/tools/llvm-reduce/deltas/ReduceVirtualRegisters.h
new file mode 100644
index 000000000000..405ba31703e5
--- /dev/null
+++ b/llvm/tools/llvm-reduce/deltas/ReduceVirtualRegisters.h
@@ -0,0 +1,25 @@
+//===- ReduceVirtualRegisters.h - Specialized Delta Pass -------*- c++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements a function which calls the Generic Delta pass in order
+// to simplify virtual register information.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_TOOLS_LLVM_REDUCE_DELTAS_REDUCEVIRTUALREGISTERS_H
+#define LLVM_TOOLS_LLVM_REDUCE_DELTAS_REDUCEVIRTUALREGISTERS_H
+
+namespace llvm {
+class TestRunner;
+
+/// Remove register allocation hints from virtual registes.
+void reduceVirtualRegisterHintsDeltaPass(TestRunner &Test);
+
+} // namespace llvm
+
+#endif
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