[PATCH] D126617: [InstCombine] Optimize shl+lshr+and conversion pattern

[chenglin.bi via Phabricator via llvm-commits]

bcl5980 added inline comments.


================
Comment at: llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp:1892-1894
+    if (C->isPowerOf2() &&
+        match(Op0,
+              m_OneUse(m_LShr(m_Shl(m_APInt(C1), m_Value(X)), m_APInt(C2)))) &&
----------------
spatel wrote:
> What happens if we reduce the pattern to:
> https://alive2.llvm.org/ce/z/7snGRd
> 
> That's the same transform that I suggested in D126591, but invert the shift direction (lshr instead of shl).
The latest version is based on your suggetion:
https://alive2.llvm.org/ce/z/7snGRd
https://alive2.llvm.org/ce/z/jA_tNb

I'm still worry if we can transform shift+and to cmp+select.
Generally most highend cpu should prefer shift+and because the cmp instruction ports is less than shift/and.
But in cmp instruction the immediate value can be imm operation but shift may need extra mov instruction on some mainstream backend.
One other question is this transform can fix the case @shl_lshr_pow2_const.
Can you help to review which way should I do ?


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  https://reviews.llvm.org/D126617/new/

https://reviews.llvm.org/D126617