[PATCH] D126726: [X86][Disassembler] Fix displacement operand size for symbolizer

[Maksim Panchenko via Phabricator via llvm-commits]

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On 64-bit X86, 0x66 operand-size override prefix will change the size of
the instruction operand, e.g. from 32 bits to 16 bits, but it will not
modify the size of the displacement operand used for memory addressing,
which will always be 32 bits.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D126726

Files:
  llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp
  llvm/unittests/MC/X86/X86MCDisassemblerTest.cpp


Index: llvm/unittests/MC/X86/X86MCDisassemblerTest.cpp
===================================================================
--- llvm/unittests/MC/X86/X86MCDisassemblerTest.cpp
+++ llvm/unittests/MC/X86/X86MCDisassemblerTest.cpp
@@ -142,4 +142,10 @@
   checkBytes({0x49, 0xc7, 0x04, 0x24, 0xf5, 0xfe, 0xff, 0xff});
   checkOperand(0, 0, 4, 0);
   checkOperand(1, 0xfffffffffffffef5, 4, 4);
+
+  // mov    %ax, 0x1568179(%rip)
+  // Test that the displacement operand size is not affected by the operand
+  // size override prefix.
+  checkBytes({0x66, 0x89, 0x05, 0x79, 0x81, 0x56, 0x01});
+  checkOperand(0, 0x1568180, 3, 4);
 }
Index: llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp
===================================================================
--- llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp
+++ llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp
@@ -502,7 +502,7 @@
     } else {
       insn->registerSize = (insn->hasOpSize ? 2 : 4);
       insn->addressSize = (insn->hasAdSize ? 4 : 8);
-      insn->displacementSize = (insn->hasOpSize ? 2 : 4);
+      insn->displacementSize = 4;
       insn->immediateSize = (insn->hasOpSize ? 2 : 4);
     }
   }


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