[PATCH] D125602: [X86][AMX][fastalloc] Allocate tile register separately.

[Matthias Braun via Phabricator via llvm-commits]

MatzeB added a comment.

There's a lot going on here.

- Could you extract the `ShouldAllocClass` fixes for fastregalloc into a separate diff so we can get discuss them separately and get feedback from AMDGPU folks who introduced this and are the major other user of this AFAIK.
- I am still wrapping my head around tile registers and tile register configs; specifically I wonder if the support for that really needs to be integrated into the generic register allocation code or whether there is a way to materialize the register configurations in a post-pass. For example do you know how the legacy x86 x87-FPU support works, where we use the register allocator to allocate pseudo FP register fp0-fp7 and then use a post-pass in `X86FloatingPoint` to insert the necessary stack management operations after the fact. I am not saying it's the same problem, but it is an example of an instance where we managed to have the regalloc allocate to some intermediate pseudo registers and adapt to the complications (in that case register stacks) in a target-specific pass so we wouldn't need to introduce the concept of register stacks to the generic code.


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  https://reviews.llvm.org/D125602/new/

https://reviews.llvm.org/D125602