[llvm] 62c4609 - [AMDGPU][DOC][NFC] Add GFX90C and GFX940 assembler syntax description
Dmitry Preobrazhensky via llvm-commits
llvm-commits at lists.llvm.org
Tue May 31 04:35:54 PDT 2022
Author: Dmitry Preobrazhensky
Date: 2022-05-31T14:29:06+03:00
New Revision: 62c46093f18f744be80758bfc6c9110e65b4434c
URL: https://github.com/llvm/llvm-project/commit/62c46093f18f744be80758bfc6c9110e65b4434c
DIFF: https://github.com/llvm/llvm-project/commit/62c46093f18f744be80758bfc6c9110e65b4434c.diff
LOG: [AMDGPU][DOC][NFC] Add GFX90C and GFX940 assembler syntax description
Added:
llvm/docs/AMDGPU/AMDGPUAsmGFX940.rst
llvm/docs/AMDGPU/gfx940_dst_4f3f9a.rst
llvm/docs/AMDGPU/gfx940_dst_95761f.rst
llvm/docs/AMDGPU/gfx940_fx_operand.rst
llvm/docs/AMDGPU/gfx940_hwreg.rst
llvm/docs/AMDGPU/gfx940_imask.rst
llvm/docs/AMDGPU/gfx940_imm16_73139a.rst
llvm/docs/AMDGPU/gfx940_imm16_a04fb3.rst
llvm/docs/AMDGPU/gfx940_label.rst
llvm/docs/AMDGPU/gfx940_m_254bcb.rst
llvm/docs/AMDGPU/gfx940_m_f5d306.rst
llvm/docs/AMDGPU/gfx940_msg.rst
llvm/docs/AMDGPU/gfx940_opt_0d447d.rst
llvm/docs/AMDGPU/gfx940_opt_7c211e.rst
llvm/docs/AMDGPU/gfx940_probe.rst
llvm/docs/AMDGPU/gfx940_saddr_22dbc1.rst
llvm/docs/AMDGPU/gfx940_saddr_a37373.rst
llvm/docs/AMDGPU/gfx940_sbase_010ce0.rst
llvm/docs/AMDGPU/gfx940_sbase_044055.rst
llvm/docs/AMDGPU/gfx940_sbase_0cd545.rst
llvm/docs/AMDGPU/gfx940_sdata_595c25.rst
llvm/docs/AMDGPU/gfx940_sdata_7cbd60.rst
llvm/docs/AMDGPU/gfx940_sdata_aefe00.rst
llvm/docs/AMDGPU/gfx940_sdata_c6aec1.rst
llvm/docs/AMDGPU/gfx940_sdata_e9f591.rst
llvm/docs/AMDGPU/gfx940_sdata_eb6f2a.rst
llvm/docs/AMDGPU/gfx940_sdst_06b266.rst
llvm/docs/AMDGPU/gfx940_sdst_0804b1.rst
llvm/docs/AMDGPU/gfx940_sdst_362c37.rst
llvm/docs/AMDGPU/gfx940_sdst_3bc700.rst
llvm/docs/AMDGPU/gfx940_sdst_59204c.rst
llvm/docs/AMDGPU/gfx940_sdst_718cc4.rst
llvm/docs/AMDGPU/gfx940_sdst_94342d.rst
llvm/docs/AMDGPU/gfx940_sdst_a319e6.rst
llvm/docs/AMDGPU/gfx940_simm32_6f0844.rst
llvm/docs/AMDGPU/gfx940_simm32_a3e80c.rst
llvm/docs/AMDGPU/gfx940_simm32_be0c1c.rst
llvm/docs/AMDGPU/gfx940_soffset_4318ca.rst
llvm/docs/AMDGPU/gfx940_soffset_7b8c50.rst
llvm/docs/AMDGPU/gfx940_soffset_f33c5c.rst
llvm/docs/AMDGPU/gfx940_src_4de5c6.rst
llvm/docs/AMDGPU/gfx940_src_56ed80.rst
llvm/docs/AMDGPU/gfx940_src_64ea89.rst
llvm/docs/AMDGPU/gfx940_src_6cfc4e.rst
llvm/docs/AMDGPU/gfx940_src_a578ba.rst
llvm/docs/AMDGPU/gfx940_src_af08be.rst
llvm/docs/AMDGPU/gfx940_src_d578c4.rst
llvm/docs/AMDGPU/gfx940_src_d95796.rst
llvm/docs/AMDGPU/gfx940_src_e1561c.rst
llvm/docs/AMDGPU/gfx940_src_e5cc81.rst
llvm/docs/AMDGPU/gfx940_src_f73668.rst
llvm/docs/AMDGPU/gfx940_srsrc.rst
llvm/docs/AMDGPU/gfx940_ssrc_4db4a9.rst
llvm/docs/AMDGPU/gfx940_ssrc_57838b.rst
llvm/docs/AMDGPU/gfx940_ssrc_595c25.rst
llvm/docs/AMDGPU/gfx940_ssrc_65f041.rst
llvm/docs/AMDGPU/gfx940_ssrc_aee59c.rst
llvm/docs/AMDGPU/gfx940_ssrc_c31902.rst
llvm/docs/AMDGPU/gfx940_ssrc_c5d631.rst
llvm/docs/AMDGPU/gfx940_ssrc_c8a322.rst
llvm/docs/AMDGPU/gfx940_ssrc_e9f591.rst
llvm/docs/AMDGPU/gfx940_type_deviation.rst
llvm/docs/AMDGPU/gfx940_vaddr_0212e3.rst
llvm/docs/AMDGPU/gfx940_vaddr_6ab80d.rst
llvm/docs/AMDGPU/gfx940_vaddr_9f7133.rst
llvm/docs/AMDGPU/gfx940_vaddr_b73dc0.rst
llvm/docs/AMDGPU/gfx940_vaddr_f20ee4.rst
llvm/docs/AMDGPU/gfx940_vcc.rst
llvm/docs/AMDGPU/gfx940_vdata0_9ad749.rst
llvm/docs/AMDGPU/gfx940_vdata0_be4895.rst
llvm/docs/AMDGPU/gfx940_vdata1_9ad749.rst
llvm/docs/AMDGPU/gfx940_vdata1_be4895.rst
llvm/docs/AMDGPU/gfx940_vdata_24882b.rst
llvm/docs/AMDGPU/gfx940_vdata_5eef12.rst
llvm/docs/AMDGPU/gfx940_vdata_848ff7.rst
llvm/docs/AMDGPU/gfx940_vdata_9ad749.rst
llvm/docs/AMDGPU/gfx940_vdata_be4895.rst
llvm/docs/AMDGPU/gfx940_vdata_c8a58b.rst
llvm/docs/AMDGPU/gfx940_vdata_cfb402.rst
llvm/docs/AMDGPU/gfx940_vdst_08b5ba.rst
llvm/docs/AMDGPU/gfx940_vdst_0c37de.rst
llvm/docs/AMDGPU/gfx940_vdst_0f48d1.rst
llvm/docs/AMDGPU/gfx940_vdst_180bef.rst
llvm/docs/AMDGPU/gfx940_vdst_260aca.rst
llvm/docs/AMDGPU/gfx940_vdst_5258b4.rst
llvm/docs/AMDGPU/gfx940_vdst_56baf6.rst
llvm/docs/AMDGPU/gfx940_vdst_63b743.rst
llvm/docs/AMDGPU/gfx940_vdst_69a144.rst
llvm/docs/AMDGPU/gfx940_vdst_78dd0a.rst
llvm/docs/AMDGPU/gfx940_vdst_89680f.rst
llvm/docs/AMDGPU/gfx940_vdst_8c77d4.rst
llvm/docs/AMDGPU/gfx940_vdst_a32035.rst
llvm/docs/AMDGPU/gfx940_vdst_bce42a.rst
llvm/docs/AMDGPU/gfx940_vdst_bdb32f.rst
llvm/docs/AMDGPU/gfx940_vdst_c3d63a.rst
llvm/docs/AMDGPU/gfx940_vdst_c8d317.rst
llvm/docs/AMDGPU/gfx940_vdst_d0c0cb.rst
llvm/docs/AMDGPU/gfx940_vdst_d6f4bd.rst
llvm/docs/AMDGPU/gfx940_vdst_d8236e.rst
llvm/docs/AMDGPU/gfx940_vdst_e2898f.rst
llvm/docs/AMDGPU/gfx940_vdst_fa7dbd.rst
llvm/docs/AMDGPU/gfx940_vsrc_1027ca.rst
llvm/docs/AMDGPU/gfx940_vsrc_6802ce.rst
llvm/docs/AMDGPU/gfx940_vsrc_848ff7.rst
llvm/docs/AMDGPU/gfx940_vsrc_9ad749.rst
llvm/docs/AMDGPU/gfx940_vsrc_be4895.rst
llvm/docs/AMDGPU/gfx940_vsrc_e016a1.rst
llvm/docs/AMDGPU/gfx940_vsrc_fd235e.rst
llvm/docs/AMDGPU/gfx940_waitcnt.rst
Modified:
llvm/docs/AMDGPU/AMDGPUAsmGFX900.rst
llvm/docs/AMDGPUModifierSyntax.rst
llvm/docs/AMDGPUUsage.rst
Removed:
################################################################################
diff --git a/llvm/docs/AMDGPU/AMDGPUAsmGFX900.rst b/llvm/docs/AMDGPU/AMDGPUAsmGFX900.rst
index c85163069615f..b0ab856c44243 100644
--- a/llvm/docs/AMDGPU/AMDGPUAsmGFX900.rst
+++ b/llvm/docs/AMDGPU/AMDGPUAsmGFX900.rst
@@ -6,7 +6,7 @@
**************************************************
====================================================================================
-Syntax of gfx900, gfx902 and gfx909 Instructions
+Syntax of gfx900, gfx902, gfx909 and gfx90c Instructions
====================================================================================
.. contents::
@@ -15,9 +15,9 @@ Syntax of gfx900, gfx902 and gfx909 Instructions
Introduction
============
-This document describes the syntax of *instructions specific to gfx900, gfx902 and gfx909*.
+This document describes the syntax of *instructions specific to gfx900, gfx902, gfx909 and gfx90c*.
-For a description of other gfx900, gfx902 and gfx909 instructions see :doc:`Syntax of Core GFX9 Instructions<AMDGPUAsmGFX9>`.
+For a description of other gfx900, gfx902, gfx909 and gfx90c instructions see :doc:`Syntax of Core GFX9 Instructions<AMDGPUAsmGFX9>`.
Notation
========
diff --git a/llvm/docs/AMDGPU/AMDGPUAsmGFX940.rst b/llvm/docs/AMDGPU/AMDGPUAsmGFX940.rst
new file mode 100644
index 0000000000000..a1089960d7c41
--- /dev/null
+++ b/llvm/docs/AMDGPU/AMDGPUAsmGFX940.rst
@@ -0,0 +1,2118 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+====================================================================================
+Syntax of GFX940 Instructions
+====================================================================================
+
+.. contents::
+ :local:
+
+Introduction
+============
+
+This document describes the syntax of GFX940 instructions.
+
+Notation
+========
+
+Notation used in this document is explained :ref:`here<amdgpu_syn_instruction_notation>`.
+
+Overview
+========
+
+An overview of generic syntax and other features of AMDGPU instructions may be found :ref:`in this document<amdgpu_syn_instructions>`.
+
+Instructions
+============
+
+
+DS
+--
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ ds_add_f32 :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_add_f64 :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_9ad749>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_add_rtn_f32 :ref:`vdst<amdgpu_synid_gfx940_vdst_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_add_rtn_f64 :ref:`vdst<amdgpu_synid_gfx940_vdst_0f48d1>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_9ad749>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_add_rtn_u32 :ref:`vdst<amdgpu_synid_gfx940_vdst_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_add_rtn_u64 :ref:`vdst<amdgpu_synid_gfx940_vdst_0f48d1>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_9ad749>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_add_u32 :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_add_u64 :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_9ad749>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_and_b32 :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_and_b64 :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_9ad749>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_and_rtn_b32 :ref:`vdst<amdgpu_synid_gfx940_vdst_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_and_rtn_b64 :ref:`vdst<amdgpu_synid_gfx940_vdst_0f48d1>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_9ad749>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_append :ref:`vdst<amdgpu_synid_gfx940_vdst_fa7dbd>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_bpermute_b32 :ref:`vdst<amdgpu_synid_gfx940_vdst_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>` :ref:`offset<amdgpu_synid_ds_offset16>`
+ ds_cmpst_b32 :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata0<amdgpu_synid_gfx940_vdata0_be4895>`, :ref:`vdata1<amdgpu_synid_gfx940_vdata1_be4895>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_cmpst_b64 :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata0<amdgpu_synid_gfx940_vdata0_9ad749>`, :ref:`vdata1<amdgpu_synid_gfx940_vdata1_9ad749>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_cmpst_f32 :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata0<amdgpu_synid_gfx940_vdata0_be4895>`, :ref:`vdata1<amdgpu_synid_gfx940_vdata1_be4895>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_cmpst_f64 :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata0<amdgpu_synid_gfx940_vdata0_9ad749>`, :ref:`vdata1<amdgpu_synid_gfx940_vdata1_9ad749>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_cmpst_rtn_b32 :ref:`vdst<amdgpu_synid_gfx940_vdst_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata0<amdgpu_synid_gfx940_vdata0_be4895>`, :ref:`vdata1<amdgpu_synid_gfx940_vdata1_be4895>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_cmpst_rtn_b64 :ref:`vdst<amdgpu_synid_gfx940_vdst_0f48d1>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata0<amdgpu_synid_gfx940_vdata0_9ad749>`, :ref:`vdata1<amdgpu_synid_gfx940_vdata1_9ad749>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_cmpst_rtn_f32 :ref:`vdst<amdgpu_synid_gfx940_vdst_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata0<amdgpu_synid_gfx940_vdata0_be4895>`, :ref:`vdata1<amdgpu_synid_gfx940_vdata1_be4895>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_cmpst_rtn_f64 :ref:`vdst<amdgpu_synid_gfx940_vdst_0f48d1>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata0<amdgpu_synid_gfx940_vdata0_9ad749>`, :ref:`vdata1<amdgpu_synid_gfx940_vdata1_9ad749>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_condxchg32_rtn_b64 :ref:`vdst<amdgpu_synid_gfx940_vdst_0f48d1>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_9ad749>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_consume :ref:`vdst<amdgpu_synid_gfx940_vdst_fa7dbd>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_dec_rtn_u32 :ref:`vdst<amdgpu_synid_gfx940_vdst_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_dec_rtn_u64 :ref:`vdst<amdgpu_synid_gfx940_vdst_0f48d1>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_9ad749>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_dec_u32 :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_dec_u64 :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_9ad749>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_gws_barrier :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_gws_init :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_gws_sema_br :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_gws_sema_p :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_gws_sema_release_all :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_gws_sema_v :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_inc_rtn_u32 :ref:`vdst<amdgpu_synid_gfx940_vdst_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_inc_rtn_u64 :ref:`vdst<amdgpu_synid_gfx940_vdst_0f48d1>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_9ad749>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_inc_u32 :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_inc_u64 :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_9ad749>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_f32 :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_f64 :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_9ad749>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_i32 :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_i64 :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_9ad749>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_rtn_f32 :ref:`vdst<amdgpu_synid_gfx940_vdst_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_rtn_f64 :ref:`vdst<amdgpu_synid_gfx940_vdst_0f48d1>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_9ad749>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_rtn_i32 :ref:`vdst<amdgpu_synid_gfx940_vdst_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_rtn_i64 :ref:`vdst<amdgpu_synid_gfx940_vdst_0f48d1>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_9ad749>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_rtn_u32 :ref:`vdst<amdgpu_synid_gfx940_vdst_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_rtn_u64 :ref:`vdst<amdgpu_synid_gfx940_vdst_0f48d1>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_9ad749>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_u32 :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_u64 :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_9ad749>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_f32 :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_f64 :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_9ad749>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_i32 :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_i64 :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_9ad749>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_rtn_f32 :ref:`vdst<amdgpu_synid_gfx940_vdst_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_rtn_f64 :ref:`vdst<amdgpu_synid_gfx940_vdst_0f48d1>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_9ad749>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_rtn_i32 :ref:`vdst<amdgpu_synid_gfx940_vdst_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_rtn_i64 :ref:`vdst<amdgpu_synid_gfx940_vdst_0f48d1>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_9ad749>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_rtn_u32 :ref:`vdst<amdgpu_synid_gfx940_vdst_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_rtn_u64 :ref:`vdst<amdgpu_synid_gfx940_vdst_0f48d1>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_9ad749>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_u32 :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_u64 :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_9ad749>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_mskor_b32 :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata0<amdgpu_synid_gfx940_vdata0_be4895>`, :ref:`vdata1<amdgpu_synid_gfx940_vdata1_be4895>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_mskor_b64 :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata0<amdgpu_synid_gfx940_vdata0_9ad749>`, :ref:`vdata1<amdgpu_synid_gfx940_vdata1_9ad749>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_mskor_rtn_b32 :ref:`vdst<amdgpu_synid_gfx940_vdst_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata0<amdgpu_synid_gfx940_vdata0_be4895>`, :ref:`vdata1<amdgpu_synid_gfx940_vdata1_be4895>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_mskor_rtn_b64 :ref:`vdst<amdgpu_synid_gfx940_vdst_0f48d1>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata0<amdgpu_synid_gfx940_vdata0_9ad749>`, :ref:`vdata1<amdgpu_synid_gfx940_vdata1_9ad749>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_nop
+ ds_or_b32 :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_or_b64 :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_9ad749>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_or_rtn_b32 :ref:`vdst<amdgpu_synid_gfx940_vdst_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_or_rtn_b64 :ref:`vdst<amdgpu_synid_gfx940_vdst_0f48d1>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_9ad749>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_permute_b32 :ref:`vdst<amdgpu_synid_gfx940_vdst_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>` :ref:`offset<amdgpu_synid_ds_offset16>`
+ ds_pk_add_bf16 :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_pk_add_f16 :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_pk_add_rtn_bf16 :ref:`vdst<amdgpu_synid_gfx940_vdst_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_pk_add_rtn_f16 :ref:`vdst<amdgpu_synid_gfx940_vdst_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read2_b32 :ref:`vdst<amdgpu_synid_gfx940_vdst_0f48d1>`::ref:`b32x2<amdgpu_synid_gfx940_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read2_b64 :ref:`vdst<amdgpu_synid_gfx940_vdst_180bef>`::ref:`b64x2<amdgpu_synid_gfx940_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read2st64_b32 :ref:`vdst<amdgpu_synid_gfx940_vdst_0f48d1>`::ref:`b32x2<amdgpu_synid_gfx940_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read2st64_b64 :ref:`vdst<amdgpu_synid_gfx940_vdst_180bef>`::ref:`b64x2<amdgpu_synid_gfx940_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_addtid_b32 :ref:`vdst<amdgpu_synid_gfx940_vdst_fa7dbd>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_b128 :ref:`vdst<amdgpu_synid_gfx940_vdst_180bef>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_b32 :ref:`vdst<amdgpu_synid_gfx940_vdst_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_b64 :ref:`vdst<amdgpu_synid_gfx940_vdst_0f48d1>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_b96 :ref:`vdst<amdgpu_synid_gfx940_vdst_260aca>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_i16 :ref:`vdst<amdgpu_synid_gfx940_vdst_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_i8 :ref:`vdst<amdgpu_synid_gfx940_vdst_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_i8_d16 :ref:`vdst<amdgpu_synid_gfx940_vdst_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_i8_d16_hi :ref:`vdst<amdgpu_synid_gfx940_vdst_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_u16 :ref:`vdst<amdgpu_synid_gfx940_vdst_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_u16_d16 :ref:`vdst<amdgpu_synid_gfx940_vdst_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_u16_d16_hi :ref:`vdst<amdgpu_synid_gfx940_vdst_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_u8 :ref:`vdst<amdgpu_synid_gfx940_vdst_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_u8_d16 :ref:`vdst<amdgpu_synid_gfx940_vdst_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_u8_d16_hi :ref:`vdst<amdgpu_synid_gfx940_vdst_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_rsub_rtn_u32 :ref:`vdst<amdgpu_synid_gfx940_vdst_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_rsub_rtn_u64 :ref:`vdst<amdgpu_synid_gfx940_vdst_0f48d1>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_9ad749>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_rsub_u32 :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_rsub_u64 :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_9ad749>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_sub_rtn_u32 :ref:`vdst<amdgpu_synid_gfx940_vdst_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_sub_rtn_u64 :ref:`vdst<amdgpu_synid_gfx940_vdst_0f48d1>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_9ad749>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_sub_u32 :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_sub_u64 :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_9ad749>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_swizzle_b32 :ref:`vdst<amdgpu_synid_gfx940_vdst_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>` :ref:`pattern<amdgpu_synid_sw_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_wrap_rtn_b32 :ref:`vdst<amdgpu_synid_gfx940_vdst_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata0<amdgpu_synid_gfx940_vdata0_be4895>`, :ref:`vdata1<amdgpu_synid_gfx940_vdata1_be4895>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write2_b32 :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata0<amdgpu_synid_gfx940_vdata0_be4895>`, :ref:`vdata1<amdgpu_synid_gfx940_vdata1_be4895>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write2_b64 :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata0<amdgpu_synid_gfx940_vdata0_9ad749>`, :ref:`vdata1<amdgpu_synid_gfx940_vdata1_9ad749>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write2st64_b32 :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata0<amdgpu_synid_gfx940_vdata0_be4895>`, :ref:`vdata1<amdgpu_synid_gfx940_vdata1_be4895>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write2st64_b64 :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata0<amdgpu_synid_gfx940_vdata0_9ad749>`, :ref:`vdata1<amdgpu_synid_gfx940_vdata1_9ad749>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write_addtid_b32 :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write_b128 :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_848ff7>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write_b16 :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write_b16_d16_hi :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write_b32 :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write_b64 :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_9ad749>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write_b8 :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write_b8_d16_hi :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write_b96 :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_cfb402>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_wrxchg2_rtn_b32 :ref:`vdst<amdgpu_synid_gfx940_vdst_0f48d1>`::ref:`b32x2<amdgpu_synid_gfx940_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata0<amdgpu_synid_gfx940_vdata0_be4895>`, :ref:`vdata1<amdgpu_synid_gfx940_vdata1_be4895>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`gds<amdgpu_synid_gds>`
+ ds_wrxchg2_rtn_b64 :ref:`vdst<amdgpu_synid_gfx940_vdst_180bef>`::ref:`b64x2<amdgpu_synid_gfx940_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata0<amdgpu_synid_gfx940_vdata0_9ad749>`, :ref:`vdata1<amdgpu_synid_gfx940_vdata1_9ad749>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`gds<amdgpu_synid_gds>`
+ ds_wrxchg2st64_rtn_b32 :ref:`vdst<amdgpu_synid_gfx940_vdst_0f48d1>`::ref:`b32x2<amdgpu_synid_gfx940_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata0<amdgpu_synid_gfx940_vdata0_be4895>`, :ref:`vdata1<amdgpu_synid_gfx940_vdata1_be4895>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`gds<amdgpu_synid_gds>`
+ ds_wrxchg2st64_rtn_b64 :ref:`vdst<amdgpu_synid_gfx940_vdst_180bef>`::ref:`b64x2<amdgpu_synid_gfx940_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata0<amdgpu_synid_gfx940_vdata0_9ad749>`, :ref:`vdata1<amdgpu_synid_gfx940_vdata1_9ad749>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`gds<amdgpu_synid_gds>`
+ ds_wrxchg_rtn_b32 :ref:`vdst<amdgpu_synid_gfx940_vdst_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_wrxchg_rtn_b64 :ref:`vdst<amdgpu_synid_gfx940_vdst_0f48d1>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_9ad749>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_xor_b32 :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_xor_b64 :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_9ad749>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_xor_rtn_b32 :ref:`vdst<amdgpu_synid_gfx940_vdst_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_xor_rtn_b64 :ref:`vdst<amdgpu_synid_gfx940_vdst_0f48d1>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_9ad749>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+
+FLAT
+----
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ flat_atomic_add :ref:`vdst<amdgpu_synid_gfx940_vdst_56baf6>`::ref:`opt<amdgpu_synid_gfx940_opt_7c211e>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ flat_atomic_add_f32 :ref:`vdst<amdgpu_synid_gfx940_vdst_56baf6>`::ref:`opt<amdgpu_synid_gfx940_opt_7c211e>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ flat_atomic_add_f64 :ref:`vdst<amdgpu_synid_gfx940_vdst_bce42a>`::ref:`opt<amdgpu_synid_gfx940_opt_7c211e>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_9ad749>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ flat_atomic_add_x2 :ref:`vdst<amdgpu_synid_gfx940_vdst_bce42a>`::ref:`opt<amdgpu_synid_gfx940_opt_7c211e>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_9ad749>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ flat_atomic_and :ref:`vdst<amdgpu_synid_gfx940_vdst_56baf6>`::ref:`opt<amdgpu_synid_gfx940_opt_7c211e>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ flat_atomic_and_x2 :ref:`vdst<amdgpu_synid_gfx940_vdst_bce42a>`::ref:`opt<amdgpu_synid_gfx940_opt_7c211e>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_9ad749>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ flat_atomic_cmpswap :ref:`vdst<amdgpu_synid_gfx940_vdst_56baf6>`::ref:`opt<amdgpu_synid_gfx940_opt_7c211e>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_9ad749>`::ref:`b32x2<amdgpu_synid_gfx940_type_deviation>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ flat_atomic_cmpswap_x2 :ref:`vdst<amdgpu_synid_gfx940_vdst_bce42a>`::ref:`opt<amdgpu_synid_gfx940_opt_7c211e>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_848ff7>`::ref:`b64x2<amdgpu_synid_gfx940_type_deviation>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ flat_atomic_dec :ref:`vdst<amdgpu_synid_gfx940_vdst_56baf6>`::ref:`opt<amdgpu_synid_gfx940_opt_7c211e>`::ref:`u32<amdgpu_synid_gfx940_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>`::ref:`u32<amdgpu_synid_gfx940_type_deviation>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ flat_atomic_dec_x2 :ref:`vdst<amdgpu_synid_gfx940_vdst_bce42a>`::ref:`opt<amdgpu_synid_gfx940_opt_7c211e>`::ref:`u64<amdgpu_synid_gfx940_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_9ad749>`::ref:`u64<amdgpu_synid_gfx940_type_deviation>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ flat_atomic_inc :ref:`vdst<amdgpu_synid_gfx940_vdst_56baf6>`::ref:`opt<amdgpu_synid_gfx940_opt_7c211e>`::ref:`u32<amdgpu_synid_gfx940_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>`::ref:`u32<amdgpu_synid_gfx940_type_deviation>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ flat_atomic_inc_x2 :ref:`vdst<amdgpu_synid_gfx940_vdst_bce42a>`::ref:`opt<amdgpu_synid_gfx940_opt_7c211e>`::ref:`u64<amdgpu_synid_gfx940_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_9ad749>`::ref:`u64<amdgpu_synid_gfx940_type_deviation>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ flat_atomic_max_f64 :ref:`vdst<amdgpu_synid_gfx940_vdst_bce42a>`::ref:`opt<amdgpu_synid_gfx940_opt_7c211e>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_9ad749>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ flat_atomic_min_f64 :ref:`vdst<amdgpu_synid_gfx940_vdst_bce42a>`::ref:`opt<amdgpu_synid_gfx940_opt_7c211e>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_9ad749>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ flat_atomic_or :ref:`vdst<amdgpu_synid_gfx940_vdst_56baf6>`::ref:`opt<amdgpu_synid_gfx940_opt_7c211e>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ flat_atomic_or_x2 :ref:`vdst<amdgpu_synid_gfx940_vdst_bce42a>`::ref:`opt<amdgpu_synid_gfx940_opt_7c211e>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_9ad749>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ flat_atomic_pk_add_bf16 :ref:`vdst<amdgpu_synid_gfx940_vdst_56baf6>`::ref:`opt<amdgpu_synid_gfx940_opt_7c211e>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ flat_atomic_pk_add_f16 :ref:`vdst<amdgpu_synid_gfx940_vdst_56baf6>`::ref:`opt<amdgpu_synid_gfx940_opt_7c211e>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ flat_atomic_smax :ref:`vdst<amdgpu_synid_gfx940_vdst_56baf6>`::ref:`opt<amdgpu_synid_gfx940_opt_7c211e>`::ref:`i32<amdgpu_synid_gfx940_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>`::ref:`i32<amdgpu_synid_gfx940_type_deviation>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ flat_atomic_smax_x2 :ref:`vdst<amdgpu_synid_gfx940_vdst_bce42a>`::ref:`opt<amdgpu_synid_gfx940_opt_7c211e>`::ref:`i64<amdgpu_synid_gfx940_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_9ad749>`::ref:`i64<amdgpu_synid_gfx940_type_deviation>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ flat_atomic_smin :ref:`vdst<amdgpu_synid_gfx940_vdst_56baf6>`::ref:`opt<amdgpu_synid_gfx940_opt_7c211e>`::ref:`i32<amdgpu_synid_gfx940_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>`::ref:`i32<amdgpu_synid_gfx940_type_deviation>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ flat_atomic_smin_x2 :ref:`vdst<amdgpu_synid_gfx940_vdst_bce42a>`::ref:`opt<amdgpu_synid_gfx940_opt_7c211e>`::ref:`i64<amdgpu_synid_gfx940_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_9ad749>`::ref:`i64<amdgpu_synid_gfx940_type_deviation>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ flat_atomic_sub :ref:`vdst<amdgpu_synid_gfx940_vdst_56baf6>`::ref:`opt<amdgpu_synid_gfx940_opt_7c211e>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ flat_atomic_sub_x2 :ref:`vdst<amdgpu_synid_gfx940_vdst_bce42a>`::ref:`opt<amdgpu_synid_gfx940_opt_7c211e>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_9ad749>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ flat_atomic_swap :ref:`vdst<amdgpu_synid_gfx940_vdst_56baf6>`::ref:`opt<amdgpu_synid_gfx940_opt_7c211e>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ flat_atomic_swap_x2 :ref:`vdst<amdgpu_synid_gfx940_vdst_bce42a>`::ref:`opt<amdgpu_synid_gfx940_opt_7c211e>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_9ad749>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ flat_atomic_umax :ref:`vdst<amdgpu_synid_gfx940_vdst_56baf6>`::ref:`opt<amdgpu_synid_gfx940_opt_7c211e>`::ref:`u32<amdgpu_synid_gfx940_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>`::ref:`u32<amdgpu_synid_gfx940_type_deviation>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ flat_atomic_umax_x2 :ref:`vdst<amdgpu_synid_gfx940_vdst_bce42a>`::ref:`opt<amdgpu_synid_gfx940_opt_7c211e>`::ref:`u64<amdgpu_synid_gfx940_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_9ad749>`::ref:`u64<amdgpu_synid_gfx940_type_deviation>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ flat_atomic_umin :ref:`vdst<amdgpu_synid_gfx940_vdst_56baf6>`::ref:`opt<amdgpu_synid_gfx940_opt_7c211e>`::ref:`u32<amdgpu_synid_gfx940_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>`::ref:`u32<amdgpu_synid_gfx940_type_deviation>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ flat_atomic_umin_x2 :ref:`vdst<amdgpu_synid_gfx940_vdst_bce42a>`::ref:`opt<amdgpu_synid_gfx940_opt_7c211e>`::ref:`u64<amdgpu_synid_gfx940_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_9ad749>`::ref:`u64<amdgpu_synid_gfx940_type_deviation>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ flat_atomic_xor :ref:`vdst<amdgpu_synid_gfx940_vdst_56baf6>`::ref:`opt<amdgpu_synid_gfx940_opt_7c211e>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ flat_atomic_xor_x2 :ref:`vdst<amdgpu_synid_gfx940_vdst_bce42a>`::ref:`opt<amdgpu_synid_gfx940_opt_7c211e>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_9ad749>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ flat_load_dword :ref:`vdst<amdgpu_synid_gfx940_vdst_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_9f7133>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ flat_load_dwordx2 :ref:`vdst<amdgpu_synid_gfx940_vdst_0f48d1>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_9f7133>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ flat_load_dwordx3 :ref:`vdst<amdgpu_synid_gfx940_vdst_260aca>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_9f7133>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ flat_load_dwordx4 :ref:`vdst<amdgpu_synid_gfx940_vdst_180bef>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_9f7133>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ flat_load_sbyte :ref:`vdst<amdgpu_synid_gfx940_vdst_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_9f7133>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ flat_load_sbyte_d16 :ref:`vdst<amdgpu_synid_gfx940_vdst_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_9f7133>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ flat_load_sbyte_d16_hi :ref:`vdst<amdgpu_synid_gfx940_vdst_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_9f7133>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ flat_load_short_d16 :ref:`vdst<amdgpu_synid_gfx940_vdst_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_9f7133>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ flat_load_short_d16_hi :ref:`vdst<amdgpu_synid_gfx940_vdst_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_9f7133>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ flat_load_sshort :ref:`vdst<amdgpu_synid_gfx940_vdst_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_9f7133>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ flat_load_ubyte :ref:`vdst<amdgpu_synid_gfx940_vdst_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_9f7133>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ flat_load_ubyte_d16 :ref:`vdst<amdgpu_synid_gfx940_vdst_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_9f7133>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ flat_load_ubyte_d16_hi :ref:`vdst<amdgpu_synid_gfx940_vdst_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_9f7133>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ flat_load_ushort :ref:`vdst<amdgpu_synid_gfx940_vdst_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_9f7133>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ flat_store_byte :ref:`vaddr<amdgpu_synid_gfx940_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ flat_store_byte_d16_hi :ref:`vaddr<amdgpu_synid_gfx940_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ flat_store_dword :ref:`vaddr<amdgpu_synid_gfx940_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ flat_store_dwordx2 :ref:`vaddr<amdgpu_synid_gfx940_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_9ad749>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ flat_store_dwordx3 :ref:`vaddr<amdgpu_synid_gfx940_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_cfb402>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ flat_store_dwordx4 :ref:`vaddr<amdgpu_synid_gfx940_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_848ff7>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ flat_store_short :ref:`vaddr<amdgpu_synid_gfx940_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ flat_store_short_d16_hi :ref:`vaddr<amdgpu_synid_gfx940_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ global_atomic_add :ref:`vdst<amdgpu_synid_gfx940_vdst_56baf6>`::ref:`opt<amdgpu_synid_gfx940_opt_7c211e>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_0212e3>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>`, :ref:`saddr<amdgpu_synid_gfx940_saddr_a37373>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ global_atomic_add_f32 :ref:`vdst<amdgpu_synid_gfx940_vdst_56baf6>`::ref:`opt<amdgpu_synid_gfx940_opt_7c211e>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_0212e3>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>`, :ref:`saddr<amdgpu_synid_gfx940_saddr_a37373>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ global_atomic_add_f64 :ref:`vdst<amdgpu_synid_gfx940_vdst_bce42a>`::ref:`opt<amdgpu_synid_gfx940_opt_7c211e>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_0212e3>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_9ad749>`, :ref:`saddr<amdgpu_synid_gfx940_saddr_a37373>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ global_atomic_add_x2 :ref:`vdst<amdgpu_synid_gfx940_vdst_bce42a>`::ref:`opt<amdgpu_synid_gfx940_opt_7c211e>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_0212e3>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_9ad749>`, :ref:`saddr<amdgpu_synid_gfx940_saddr_a37373>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ global_atomic_and :ref:`vdst<amdgpu_synid_gfx940_vdst_56baf6>`::ref:`opt<amdgpu_synid_gfx940_opt_7c211e>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_0212e3>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>`, :ref:`saddr<amdgpu_synid_gfx940_saddr_a37373>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ global_atomic_and_x2 :ref:`vdst<amdgpu_synid_gfx940_vdst_bce42a>`::ref:`opt<amdgpu_synid_gfx940_opt_7c211e>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_0212e3>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_9ad749>`, :ref:`saddr<amdgpu_synid_gfx940_saddr_a37373>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ global_atomic_cmpswap :ref:`vdst<amdgpu_synid_gfx940_vdst_56baf6>`::ref:`opt<amdgpu_synid_gfx940_opt_7c211e>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_0212e3>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_9ad749>`::ref:`b32x2<amdgpu_synid_gfx940_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx940_saddr_a37373>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ global_atomic_cmpswap_x2 :ref:`vdst<amdgpu_synid_gfx940_vdst_bce42a>`::ref:`opt<amdgpu_synid_gfx940_opt_7c211e>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_0212e3>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_848ff7>`::ref:`b64x2<amdgpu_synid_gfx940_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx940_saddr_a37373>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ global_atomic_dec :ref:`vdst<amdgpu_synid_gfx940_vdst_56baf6>`::ref:`opt<amdgpu_synid_gfx940_opt_7c211e>`::ref:`u32<amdgpu_synid_gfx940_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_0212e3>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>`::ref:`u32<amdgpu_synid_gfx940_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx940_saddr_a37373>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ global_atomic_dec_x2 :ref:`vdst<amdgpu_synid_gfx940_vdst_bce42a>`::ref:`opt<amdgpu_synid_gfx940_opt_7c211e>`::ref:`u64<amdgpu_synid_gfx940_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_0212e3>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_9ad749>`::ref:`u64<amdgpu_synid_gfx940_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx940_saddr_a37373>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ global_atomic_inc :ref:`vdst<amdgpu_synid_gfx940_vdst_56baf6>`::ref:`opt<amdgpu_synid_gfx940_opt_7c211e>`::ref:`u32<amdgpu_synid_gfx940_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_0212e3>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>`::ref:`u32<amdgpu_synid_gfx940_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx940_saddr_a37373>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ global_atomic_inc_x2 :ref:`vdst<amdgpu_synid_gfx940_vdst_bce42a>`::ref:`opt<amdgpu_synid_gfx940_opt_7c211e>`::ref:`u64<amdgpu_synid_gfx940_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_0212e3>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_9ad749>`::ref:`u64<amdgpu_synid_gfx940_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx940_saddr_a37373>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ global_atomic_max_f64 :ref:`vdst<amdgpu_synid_gfx940_vdst_bce42a>`::ref:`opt<amdgpu_synid_gfx940_opt_7c211e>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_0212e3>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_9ad749>`, :ref:`saddr<amdgpu_synid_gfx940_saddr_a37373>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ global_atomic_min_f64 :ref:`vdst<amdgpu_synid_gfx940_vdst_bce42a>`::ref:`opt<amdgpu_synid_gfx940_opt_7c211e>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_0212e3>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_9ad749>`, :ref:`saddr<amdgpu_synid_gfx940_saddr_a37373>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ global_atomic_or :ref:`vdst<amdgpu_synid_gfx940_vdst_56baf6>`::ref:`opt<amdgpu_synid_gfx940_opt_7c211e>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_0212e3>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>`, :ref:`saddr<amdgpu_synid_gfx940_saddr_a37373>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ global_atomic_or_x2 :ref:`vdst<amdgpu_synid_gfx940_vdst_bce42a>`::ref:`opt<amdgpu_synid_gfx940_opt_7c211e>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_0212e3>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_9ad749>`, :ref:`saddr<amdgpu_synid_gfx940_saddr_a37373>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ global_atomic_pk_add_bf16 :ref:`vdst<amdgpu_synid_gfx940_vdst_56baf6>`::ref:`opt<amdgpu_synid_gfx940_opt_7c211e>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_0212e3>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>`, :ref:`saddr<amdgpu_synid_gfx940_saddr_a37373>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ global_atomic_pk_add_f16 :ref:`vdst<amdgpu_synid_gfx940_vdst_56baf6>`::ref:`opt<amdgpu_synid_gfx940_opt_7c211e>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_0212e3>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>`, :ref:`saddr<amdgpu_synid_gfx940_saddr_a37373>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ global_atomic_smax :ref:`vdst<amdgpu_synid_gfx940_vdst_56baf6>`::ref:`opt<amdgpu_synid_gfx940_opt_7c211e>`::ref:`i32<amdgpu_synid_gfx940_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_0212e3>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>`::ref:`i32<amdgpu_synid_gfx940_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx940_saddr_a37373>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ global_atomic_smax_x2 :ref:`vdst<amdgpu_synid_gfx940_vdst_bce42a>`::ref:`opt<amdgpu_synid_gfx940_opt_7c211e>`::ref:`i64<amdgpu_synid_gfx940_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_0212e3>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_9ad749>`::ref:`i64<amdgpu_synid_gfx940_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx940_saddr_a37373>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ global_atomic_smin :ref:`vdst<amdgpu_synid_gfx940_vdst_56baf6>`::ref:`opt<amdgpu_synid_gfx940_opt_7c211e>`::ref:`i32<amdgpu_synid_gfx940_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_0212e3>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>`::ref:`i32<amdgpu_synid_gfx940_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx940_saddr_a37373>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ global_atomic_smin_x2 :ref:`vdst<amdgpu_synid_gfx940_vdst_bce42a>`::ref:`opt<amdgpu_synid_gfx940_opt_7c211e>`::ref:`i64<amdgpu_synid_gfx940_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_0212e3>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_9ad749>`::ref:`i64<amdgpu_synid_gfx940_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx940_saddr_a37373>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ global_atomic_sub :ref:`vdst<amdgpu_synid_gfx940_vdst_56baf6>`::ref:`opt<amdgpu_synid_gfx940_opt_7c211e>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_0212e3>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>`, :ref:`saddr<amdgpu_synid_gfx940_saddr_a37373>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ global_atomic_sub_x2 :ref:`vdst<amdgpu_synid_gfx940_vdst_bce42a>`::ref:`opt<amdgpu_synid_gfx940_opt_7c211e>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_0212e3>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_9ad749>`, :ref:`saddr<amdgpu_synid_gfx940_saddr_a37373>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ global_atomic_swap :ref:`vdst<amdgpu_synid_gfx940_vdst_56baf6>`::ref:`opt<amdgpu_synid_gfx940_opt_7c211e>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_0212e3>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>`, :ref:`saddr<amdgpu_synid_gfx940_saddr_a37373>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ global_atomic_swap_x2 :ref:`vdst<amdgpu_synid_gfx940_vdst_bce42a>`::ref:`opt<amdgpu_synid_gfx940_opt_7c211e>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_0212e3>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_9ad749>`, :ref:`saddr<amdgpu_synid_gfx940_saddr_a37373>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ global_atomic_umax :ref:`vdst<amdgpu_synid_gfx940_vdst_56baf6>`::ref:`opt<amdgpu_synid_gfx940_opt_7c211e>`::ref:`u32<amdgpu_synid_gfx940_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_0212e3>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>`::ref:`u32<amdgpu_synid_gfx940_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx940_saddr_a37373>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ global_atomic_umax_x2 :ref:`vdst<amdgpu_synid_gfx940_vdst_bce42a>`::ref:`opt<amdgpu_synid_gfx940_opt_7c211e>`::ref:`u64<amdgpu_synid_gfx940_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_0212e3>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_9ad749>`::ref:`u64<amdgpu_synid_gfx940_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx940_saddr_a37373>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ global_atomic_umin :ref:`vdst<amdgpu_synid_gfx940_vdst_56baf6>`::ref:`opt<amdgpu_synid_gfx940_opt_7c211e>`::ref:`u32<amdgpu_synid_gfx940_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_0212e3>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>`::ref:`u32<amdgpu_synid_gfx940_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx940_saddr_a37373>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ global_atomic_umin_x2 :ref:`vdst<amdgpu_synid_gfx940_vdst_bce42a>`::ref:`opt<amdgpu_synid_gfx940_opt_7c211e>`::ref:`u64<amdgpu_synid_gfx940_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_0212e3>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_9ad749>`::ref:`u64<amdgpu_synid_gfx940_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx940_saddr_a37373>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ global_atomic_xor :ref:`vdst<amdgpu_synid_gfx940_vdst_56baf6>`::ref:`opt<amdgpu_synid_gfx940_opt_7c211e>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_0212e3>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>`, :ref:`saddr<amdgpu_synid_gfx940_saddr_a37373>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ global_atomic_xor_x2 :ref:`vdst<amdgpu_synid_gfx940_vdst_bce42a>`::ref:`opt<amdgpu_synid_gfx940_opt_7c211e>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_0212e3>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_9ad749>`, :ref:`saddr<amdgpu_synid_gfx940_saddr_a37373>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ global_load_dword :ref:`vdst<amdgpu_synid_gfx940_vdst_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_0212e3>`, :ref:`saddr<amdgpu_synid_gfx940_saddr_a37373>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ global_load_dwordx2 :ref:`vdst<amdgpu_synid_gfx940_vdst_0f48d1>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_0212e3>`, :ref:`saddr<amdgpu_synid_gfx940_saddr_a37373>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ global_load_dwordx3 :ref:`vdst<amdgpu_synid_gfx940_vdst_260aca>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_0212e3>`, :ref:`saddr<amdgpu_synid_gfx940_saddr_a37373>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ global_load_dwordx4 :ref:`vdst<amdgpu_synid_gfx940_vdst_180bef>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_0212e3>`, :ref:`saddr<amdgpu_synid_gfx940_saddr_a37373>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ global_load_lds_dword :ref:`vaddr<amdgpu_synid_gfx940_vaddr_0212e3>`, :ref:`saddr<amdgpu_synid_gfx940_saddr_a37373>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ global_load_lds_sbyte :ref:`vaddr<amdgpu_synid_gfx940_vaddr_0212e3>`, :ref:`saddr<amdgpu_synid_gfx940_saddr_a37373>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ global_load_lds_sshort :ref:`vaddr<amdgpu_synid_gfx940_vaddr_0212e3>`, :ref:`saddr<amdgpu_synid_gfx940_saddr_a37373>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ global_load_lds_ubyte :ref:`vaddr<amdgpu_synid_gfx940_vaddr_0212e3>`, :ref:`saddr<amdgpu_synid_gfx940_saddr_a37373>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ global_load_lds_ushort :ref:`vaddr<amdgpu_synid_gfx940_vaddr_0212e3>`, :ref:`saddr<amdgpu_synid_gfx940_saddr_a37373>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ global_load_sbyte :ref:`vdst<amdgpu_synid_gfx940_vdst_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_0212e3>`, :ref:`saddr<amdgpu_synid_gfx940_saddr_a37373>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ global_load_sbyte_d16 :ref:`vdst<amdgpu_synid_gfx940_vdst_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_0212e3>`, :ref:`saddr<amdgpu_synid_gfx940_saddr_a37373>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ global_load_sbyte_d16_hi :ref:`vdst<amdgpu_synid_gfx940_vdst_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_0212e3>`, :ref:`saddr<amdgpu_synid_gfx940_saddr_a37373>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ global_load_short_d16 :ref:`vdst<amdgpu_synid_gfx940_vdst_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_0212e3>`, :ref:`saddr<amdgpu_synid_gfx940_saddr_a37373>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ global_load_short_d16_hi :ref:`vdst<amdgpu_synid_gfx940_vdst_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_0212e3>`, :ref:`saddr<amdgpu_synid_gfx940_saddr_a37373>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ global_load_sshort :ref:`vdst<amdgpu_synid_gfx940_vdst_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_0212e3>`, :ref:`saddr<amdgpu_synid_gfx940_saddr_a37373>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ global_load_ubyte :ref:`vdst<amdgpu_synid_gfx940_vdst_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_0212e3>`, :ref:`saddr<amdgpu_synid_gfx940_saddr_a37373>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ global_load_ubyte_d16 :ref:`vdst<amdgpu_synid_gfx940_vdst_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_0212e3>`, :ref:`saddr<amdgpu_synid_gfx940_saddr_a37373>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ global_load_ubyte_d16_hi :ref:`vdst<amdgpu_synid_gfx940_vdst_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_0212e3>`, :ref:`saddr<amdgpu_synid_gfx940_saddr_a37373>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ global_load_ushort :ref:`vdst<amdgpu_synid_gfx940_vdst_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_0212e3>`, :ref:`saddr<amdgpu_synid_gfx940_saddr_a37373>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ global_store_byte :ref:`vaddr<amdgpu_synid_gfx940_vaddr_0212e3>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>`, :ref:`saddr<amdgpu_synid_gfx940_saddr_a37373>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ global_store_byte_d16_hi :ref:`vaddr<amdgpu_synid_gfx940_vaddr_0212e3>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>`, :ref:`saddr<amdgpu_synid_gfx940_saddr_a37373>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ global_store_dword :ref:`vaddr<amdgpu_synid_gfx940_vaddr_0212e3>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>`, :ref:`saddr<amdgpu_synid_gfx940_saddr_a37373>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ global_store_dwordx2 :ref:`vaddr<amdgpu_synid_gfx940_vaddr_0212e3>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_9ad749>`, :ref:`saddr<amdgpu_synid_gfx940_saddr_a37373>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ global_store_dwordx3 :ref:`vaddr<amdgpu_synid_gfx940_vaddr_0212e3>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_cfb402>`, :ref:`saddr<amdgpu_synid_gfx940_saddr_a37373>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ global_store_dwordx4 :ref:`vaddr<amdgpu_synid_gfx940_vaddr_0212e3>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_848ff7>`, :ref:`saddr<amdgpu_synid_gfx940_saddr_a37373>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ global_store_short :ref:`vaddr<amdgpu_synid_gfx940_vaddr_0212e3>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>`, :ref:`saddr<amdgpu_synid_gfx940_saddr_a37373>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ global_store_short_d16_hi :ref:`vaddr<amdgpu_synid_gfx940_vaddr_0212e3>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>`, :ref:`saddr<amdgpu_synid_gfx940_saddr_a37373>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ scratch_load_dword :ref:`vdst<amdgpu_synid_gfx940_vdst_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_6ab80d>`, :ref:`saddr<amdgpu_synid_gfx940_saddr_22dbc1>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ scratch_load_dwordx2 :ref:`vdst<amdgpu_synid_gfx940_vdst_0f48d1>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_6ab80d>`, :ref:`saddr<amdgpu_synid_gfx940_saddr_22dbc1>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ scratch_load_dwordx3 :ref:`vdst<amdgpu_synid_gfx940_vdst_260aca>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_6ab80d>`, :ref:`saddr<amdgpu_synid_gfx940_saddr_22dbc1>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ scratch_load_dwordx4 :ref:`vdst<amdgpu_synid_gfx940_vdst_180bef>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_6ab80d>`, :ref:`saddr<amdgpu_synid_gfx940_saddr_22dbc1>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ scratch_load_lds_dword :ref:`vaddr<amdgpu_synid_gfx940_vaddr_6ab80d>`, :ref:`saddr<amdgpu_synid_gfx940_saddr_22dbc1>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ scratch_load_lds_sbyte :ref:`vaddr<amdgpu_synid_gfx940_vaddr_6ab80d>`, :ref:`saddr<amdgpu_synid_gfx940_saddr_22dbc1>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ scratch_load_lds_sshort :ref:`vaddr<amdgpu_synid_gfx940_vaddr_6ab80d>`, :ref:`saddr<amdgpu_synid_gfx940_saddr_22dbc1>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ scratch_load_lds_ubyte :ref:`vaddr<amdgpu_synid_gfx940_vaddr_6ab80d>`, :ref:`saddr<amdgpu_synid_gfx940_saddr_22dbc1>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ scratch_load_lds_ushort :ref:`vaddr<amdgpu_synid_gfx940_vaddr_6ab80d>`, :ref:`saddr<amdgpu_synid_gfx940_saddr_22dbc1>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ scratch_load_sbyte :ref:`vdst<amdgpu_synid_gfx940_vdst_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_6ab80d>`, :ref:`saddr<amdgpu_synid_gfx940_saddr_22dbc1>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ scratch_load_sbyte_d16 :ref:`vdst<amdgpu_synid_gfx940_vdst_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_6ab80d>`, :ref:`saddr<amdgpu_synid_gfx940_saddr_22dbc1>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ scratch_load_sbyte_d16_hi :ref:`vdst<amdgpu_synid_gfx940_vdst_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_6ab80d>`, :ref:`saddr<amdgpu_synid_gfx940_saddr_22dbc1>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ scratch_load_short_d16 :ref:`vdst<amdgpu_synid_gfx940_vdst_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_6ab80d>`, :ref:`saddr<amdgpu_synid_gfx940_saddr_22dbc1>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ scratch_load_short_d16_hi :ref:`vdst<amdgpu_synid_gfx940_vdst_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_6ab80d>`, :ref:`saddr<amdgpu_synid_gfx940_saddr_22dbc1>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ scratch_load_sshort :ref:`vdst<amdgpu_synid_gfx940_vdst_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_6ab80d>`, :ref:`saddr<amdgpu_synid_gfx940_saddr_22dbc1>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ scratch_load_ubyte :ref:`vdst<amdgpu_synid_gfx940_vdst_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_6ab80d>`, :ref:`saddr<amdgpu_synid_gfx940_saddr_22dbc1>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ scratch_load_ubyte_d16 :ref:`vdst<amdgpu_synid_gfx940_vdst_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_6ab80d>`, :ref:`saddr<amdgpu_synid_gfx940_saddr_22dbc1>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ scratch_load_ubyte_d16_hi :ref:`vdst<amdgpu_synid_gfx940_vdst_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_6ab80d>`, :ref:`saddr<amdgpu_synid_gfx940_saddr_22dbc1>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ scratch_load_ushort :ref:`vdst<amdgpu_synid_gfx940_vdst_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_6ab80d>`, :ref:`saddr<amdgpu_synid_gfx940_saddr_22dbc1>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ scratch_store_byte :ref:`vaddr<amdgpu_synid_gfx940_vaddr_6ab80d>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>`, :ref:`saddr<amdgpu_synid_gfx940_saddr_22dbc1>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ scratch_store_byte_d16_hi :ref:`vaddr<amdgpu_synid_gfx940_vaddr_6ab80d>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>`, :ref:`saddr<amdgpu_synid_gfx940_saddr_22dbc1>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ scratch_store_dword :ref:`vaddr<amdgpu_synid_gfx940_vaddr_6ab80d>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>`, :ref:`saddr<amdgpu_synid_gfx940_saddr_22dbc1>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ scratch_store_dwordx2 :ref:`vaddr<amdgpu_synid_gfx940_vaddr_6ab80d>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_9ad749>`, :ref:`saddr<amdgpu_synid_gfx940_saddr_22dbc1>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ scratch_store_dwordx3 :ref:`vaddr<amdgpu_synid_gfx940_vaddr_6ab80d>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_cfb402>`, :ref:`saddr<amdgpu_synid_gfx940_saddr_22dbc1>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ scratch_store_dwordx4 :ref:`vaddr<amdgpu_synid_gfx940_vaddr_6ab80d>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_848ff7>`, :ref:`saddr<amdgpu_synid_gfx940_saddr_22dbc1>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ scratch_store_short :ref:`vaddr<amdgpu_synid_gfx940_vaddr_6ab80d>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>`, :ref:`saddr<amdgpu_synid_gfx940_saddr_22dbc1>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ scratch_store_short_d16_hi :ref:`vaddr<amdgpu_synid_gfx940_vaddr_6ab80d>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>`, :ref:`saddr<amdgpu_synid_gfx940_saddr_22dbc1>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+
+MTBUF
+-----
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **SRC3** **MODIFIERS**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ tbuffer_load_format_d16_x :ref:`vdst<amdgpu_synid_gfx940_vdst_c3d63a>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx940_srsrc>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_4318ca>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ tbuffer_load_format_d16_xy :ref:`vdst<amdgpu_synid_gfx940_vdst_c3d63a>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx940_srsrc>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_4318ca>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ tbuffer_load_format_d16_xyz :ref:`vdst<amdgpu_synid_gfx940_vdst_0c37de>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx940_srsrc>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_4318ca>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ tbuffer_load_format_d16_xyzw :ref:`vdst<amdgpu_synid_gfx940_vdst_0c37de>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx940_srsrc>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_4318ca>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ tbuffer_load_format_x :ref:`vdst<amdgpu_synid_gfx940_vdst_c3d63a>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx940_srsrc>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_4318ca>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ tbuffer_load_format_xy :ref:`vdst<amdgpu_synid_gfx940_vdst_0c37de>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx940_srsrc>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_4318ca>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ tbuffer_load_format_xyz :ref:`vdst<amdgpu_synid_gfx940_vdst_63b743>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx940_srsrc>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_4318ca>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ tbuffer_load_format_xyzw :ref:`vdst<amdgpu_synid_gfx940_vdst_08b5ba>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx940_srsrc>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_4318ca>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ tbuffer_store_format_d16_x :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx940_srsrc>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_4318ca>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ tbuffer_store_format_d16_xy :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx940_srsrc>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_4318ca>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ tbuffer_store_format_d16_xyz :ref:`vdata<amdgpu_synid_gfx940_vdata_9ad749>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx940_srsrc>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_4318ca>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ tbuffer_store_format_d16_xyzw :ref:`vdata<amdgpu_synid_gfx940_vdata_9ad749>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx940_srsrc>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_4318ca>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ tbuffer_store_format_x :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx940_srsrc>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_4318ca>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ tbuffer_store_format_xy :ref:`vdata<amdgpu_synid_gfx940_vdata_9ad749>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx940_srsrc>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_4318ca>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ tbuffer_store_format_xyz :ref:`vdata<amdgpu_synid_gfx940_vdata_cfb402>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx940_srsrc>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_4318ca>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ tbuffer_store_format_xyzw :ref:`vdata<amdgpu_synid_gfx940_vdata_848ff7>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx940_srsrc>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_4318ca>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+
+MUBUF
+-----
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **SRC3** **MODIFIERS**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ buffer_atomic_add :ref:`vdata<amdgpu_synid_gfx940_vdata_24882b>`::ref:`dst<amdgpu_synid_gfx940_dst_4f3f9a>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx940_srsrc>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_4318ca>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ buffer_atomic_add_f32 :ref:`vdata<amdgpu_synid_gfx940_vdata_24882b>`::ref:`dst<amdgpu_synid_gfx940_dst_4f3f9a>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx940_srsrc>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_4318ca>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ buffer_atomic_add_f64 :ref:`vdata<amdgpu_synid_gfx940_vdata_c8a58b>`::ref:`dst<amdgpu_synid_gfx940_dst_4f3f9a>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx940_srsrc>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_4318ca>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ buffer_atomic_add_x2 :ref:`vdata<amdgpu_synid_gfx940_vdata_c8a58b>`::ref:`dst<amdgpu_synid_gfx940_dst_4f3f9a>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx940_srsrc>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_4318ca>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ buffer_atomic_and :ref:`vdata<amdgpu_synid_gfx940_vdata_24882b>`::ref:`dst<amdgpu_synid_gfx940_dst_4f3f9a>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx940_srsrc>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_4318ca>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ buffer_atomic_and_x2 :ref:`vdata<amdgpu_synid_gfx940_vdata_c8a58b>`::ref:`dst<amdgpu_synid_gfx940_dst_4f3f9a>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx940_srsrc>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_4318ca>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ buffer_atomic_cmpswap :ref:`vdata<amdgpu_synid_gfx940_vdata_c8a58b>`::ref:`dst<amdgpu_synid_gfx940_dst_4f3f9a>`::ref:`b32x2<amdgpu_synid_gfx940_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx940_srsrc>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_4318ca>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ buffer_atomic_cmpswap_x2 :ref:`vdata<amdgpu_synid_gfx940_vdata_5eef12>`::ref:`dst<amdgpu_synid_gfx940_dst_4f3f9a>`::ref:`b64x2<amdgpu_synid_gfx940_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx940_srsrc>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_4318ca>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ buffer_atomic_dec :ref:`vdata<amdgpu_synid_gfx940_vdata_24882b>`::ref:`dst<amdgpu_synid_gfx940_dst_4f3f9a>`::ref:`u32<amdgpu_synid_gfx940_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx940_srsrc>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_4318ca>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ buffer_atomic_dec_x2 :ref:`vdata<amdgpu_synid_gfx940_vdata_c8a58b>`::ref:`dst<amdgpu_synid_gfx940_dst_4f3f9a>`::ref:`u64<amdgpu_synid_gfx940_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx940_srsrc>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_4318ca>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ buffer_atomic_inc :ref:`vdata<amdgpu_synid_gfx940_vdata_24882b>`::ref:`dst<amdgpu_synid_gfx940_dst_4f3f9a>`::ref:`u32<amdgpu_synid_gfx940_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx940_srsrc>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_4318ca>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ buffer_atomic_inc_x2 :ref:`vdata<amdgpu_synid_gfx940_vdata_c8a58b>`::ref:`dst<amdgpu_synid_gfx940_dst_4f3f9a>`::ref:`u64<amdgpu_synid_gfx940_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx940_srsrc>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_4318ca>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ buffer_atomic_max_f64 :ref:`vdata<amdgpu_synid_gfx940_vdata_c8a58b>`::ref:`dst<amdgpu_synid_gfx940_dst_4f3f9a>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx940_srsrc>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_4318ca>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ buffer_atomic_min_f64 :ref:`vdata<amdgpu_synid_gfx940_vdata_c8a58b>`::ref:`dst<amdgpu_synid_gfx940_dst_4f3f9a>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx940_srsrc>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_4318ca>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ buffer_atomic_or :ref:`vdata<amdgpu_synid_gfx940_vdata_24882b>`::ref:`dst<amdgpu_synid_gfx940_dst_4f3f9a>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx940_srsrc>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_4318ca>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ buffer_atomic_or_x2 :ref:`vdata<amdgpu_synid_gfx940_vdata_c8a58b>`::ref:`dst<amdgpu_synid_gfx940_dst_4f3f9a>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx940_srsrc>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_4318ca>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ buffer_atomic_pk_add_f16 :ref:`vdata<amdgpu_synid_gfx940_vdata_24882b>`::ref:`dst<amdgpu_synid_gfx940_dst_4f3f9a>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx940_srsrc>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_4318ca>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ buffer_atomic_smax :ref:`vdata<amdgpu_synid_gfx940_vdata_24882b>`::ref:`dst<amdgpu_synid_gfx940_dst_4f3f9a>`::ref:`i32<amdgpu_synid_gfx940_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx940_srsrc>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_4318ca>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ buffer_atomic_smax_x2 :ref:`vdata<amdgpu_synid_gfx940_vdata_c8a58b>`::ref:`dst<amdgpu_synid_gfx940_dst_4f3f9a>`::ref:`i64<amdgpu_synid_gfx940_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx940_srsrc>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_4318ca>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ buffer_atomic_smin :ref:`vdata<amdgpu_synid_gfx940_vdata_24882b>`::ref:`dst<amdgpu_synid_gfx940_dst_4f3f9a>`::ref:`i32<amdgpu_synid_gfx940_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx940_srsrc>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_4318ca>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ buffer_atomic_smin_x2 :ref:`vdata<amdgpu_synid_gfx940_vdata_c8a58b>`::ref:`dst<amdgpu_synid_gfx940_dst_4f3f9a>`::ref:`i64<amdgpu_synid_gfx940_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx940_srsrc>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_4318ca>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ buffer_atomic_sub :ref:`vdata<amdgpu_synid_gfx940_vdata_24882b>`::ref:`dst<amdgpu_synid_gfx940_dst_4f3f9a>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx940_srsrc>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_4318ca>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ buffer_atomic_sub_x2 :ref:`vdata<amdgpu_synid_gfx940_vdata_c8a58b>`::ref:`dst<amdgpu_synid_gfx940_dst_4f3f9a>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx940_srsrc>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_4318ca>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ buffer_atomic_swap :ref:`vdata<amdgpu_synid_gfx940_vdata_24882b>`::ref:`dst<amdgpu_synid_gfx940_dst_4f3f9a>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx940_srsrc>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_4318ca>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ buffer_atomic_swap_x2 :ref:`vdata<amdgpu_synid_gfx940_vdata_c8a58b>`::ref:`dst<amdgpu_synid_gfx940_dst_4f3f9a>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx940_srsrc>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_4318ca>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ buffer_atomic_umax :ref:`vdata<amdgpu_synid_gfx940_vdata_24882b>`::ref:`dst<amdgpu_synid_gfx940_dst_4f3f9a>`::ref:`u32<amdgpu_synid_gfx940_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx940_srsrc>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_4318ca>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ buffer_atomic_umax_x2 :ref:`vdata<amdgpu_synid_gfx940_vdata_c8a58b>`::ref:`dst<amdgpu_synid_gfx940_dst_4f3f9a>`::ref:`u64<amdgpu_synid_gfx940_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx940_srsrc>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_4318ca>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ buffer_atomic_umin :ref:`vdata<amdgpu_synid_gfx940_vdata_24882b>`::ref:`dst<amdgpu_synid_gfx940_dst_4f3f9a>`::ref:`u32<amdgpu_synid_gfx940_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx940_srsrc>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_4318ca>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ buffer_atomic_umin_x2 :ref:`vdata<amdgpu_synid_gfx940_vdata_c8a58b>`::ref:`dst<amdgpu_synid_gfx940_dst_4f3f9a>`::ref:`u64<amdgpu_synid_gfx940_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx940_srsrc>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_4318ca>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ buffer_atomic_xor :ref:`vdata<amdgpu_synid_gfx940_vdata_24882b>`::ref:`dst<amdgpu_synid_gfx940_dst_4f3f9a>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx940_srsrc>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_4318ca>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ buffer_atomic_xor_x2 :ref:`vdata<amdgpu_synid_gfx940_vdata_c8a58b>`::ref:`dst<amdgpu_synid_gfx940_dst_4f3f9a>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx940_srsrc>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_4318ca>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ buffer_inv
+ buffer_load_dword :ref:`vdst<amdgpu_synid_gfx940_vdst_5258b4>`::ref:`opt<amdgpu_synid_gfx940_opt_0d447d>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx940_srsrc>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_4318ca>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`lds<amdgpu_synid_lds>`
+ buffer_load_dwordx2 :ref:`vdst<amdgpu_synid_gfx940_vdst_d8236e>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx940_srsrc>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_4318ca>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ buffer_load_dwordx3 :ref:`vdst<amdgpu_synid_gfx940_vdst_e2898f>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx940_srsrc>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_4318ca>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ buffer_load_dwordx4 :ref:`vdst<amdgpu_synid_gfx940_vdst_a32035>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx940_srsrc>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_4318ca>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ buffer_load_format_d16_hi_x :ref:`vdst<amdgpu_synid_gfx940_vdst_d0c0cb>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx940_srsrc>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_4318ca>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ buffer_load_format_d16_x :ref:`vdst<amdgpu_synid_gfx940_vdst_d0c0cb>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx940_srsrc>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_4318ca>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ buffer_load_format_d16_xy :ref:`vdst<amdgpu_synid_gfx940_vdst_d0c0cb>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx940_srsrc>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_4318ca>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ buffer_load_format_d16_xyz :ref:`vdst<amdgpu_synid_gfx940_vdst_d8236e>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx940_srsrc>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_4318ca>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ buffer_load_format_d16_xyzw :ref:`vdst<amdgpu_synid_gfx940_vdst_d8236e>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx940_srsrc>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_4318ca>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ buffer_load_format_x :ref:`vdst<amdgpu_synid_gfx940_vdst_5258b4>`::ref:`opt<amdgpu_synid_gfx940_opt_0d447d>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx940_srsrc>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_4318ca>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`lds<amdgpu_synid_lds>`
+ buffer_load_format_xy :ref:`vdst<amdgpu_synid_gfx940_vdst_d8236e>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx940_srsrc>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_4318ca>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ buffer_load_format_xyz :ref:`vdst<amdgpu_synid_gfx940_vdst_e2898f>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx940_srsrc>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_4318ca>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ buffer_load_format_xyzw :ref:`vdst<amdgpu_synid_gfx940_vdst_a32035>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx940_srsrc>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_4318ca>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ buffer_load_sbyte :ref:`vdst<amdgpu_synid_gfx940_vdst_5258b4>`::ref:`opt<amdgpu_synid_gfx940_opt_0d447d>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx940_srsrc>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_4318ca>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`lds<amdgpu_synid_lds>`
+ buffer_load_sbyte_d16 :ref:`vdst<amdgpu_synid_gfx940_vdst_d0c0cb>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx940_srsrc>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_4318ca>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ buffer_load_sbyte_d16_hi :ref:`vdst<amdgpu_synid_gfx940_vdst_d0c0cb>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx940_srsrc>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_4318ca>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ buffer_load_short_d16 :ref:`vdst<amdgpu_synid_gfx940_vdst_d0c0cb>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx940_srsrc>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_4318ca>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ buffer_load_short_d16_hi :ref:`vdst<amdgpu_synid_gfx940_vdst_d0c0cb>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx940_srsrc>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_4318ca>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ buffer_load_sshort :ref:`vdst<amdgpu_synid_gfx940_vdst_5258b4>`::ref:`opt<amdgpu_synid_gfx940_opt_0d447d>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx940_srsrc>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_4318ca>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`lds<amdgpu_synid_lds>`
+ buffer_load_ubyte :ref:`vdst<amdgpu_synid_gfx940_vdst_5258b4>`::ref:`opt<amdgpu_synid_gfx940_opt_0d447d>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx940_srsrc>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_4318ca>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`lds<amdgpu_synid_lds>`
+ buffer_load_ubyte_d16 :ref:`vdst<amdgpu_synid_gfx940_vdst_d0c0cb>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx940_srsrc>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_4318ca>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ buffer_load_ubyte_d16_hi :ref:`vdst<amdgpu_synid_gfx940_vdst_d0c0cb>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx940_srsrc>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_4318ca>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ buffer_load_ushort :ref:`vdst<amdgpu_synid_gfx940_vdst_5258b4>`::ref:`opt<amdgpu_synid_gfx940_opt_0d447d>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx940_srsrc>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_4318ca>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`lds<amdgpu_synid_lds>`
+ buffer_store_byte :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx940_srsrc>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_4318ca>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ buffer_store_byte_d16_hi :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx940_srsrc>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_4318ca>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ buffer_store_dword :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx940_srsrc>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_4318ca>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ buffer_store_dwordx2 :ref:`vdata<amdgpu_synid_gfx940_vdata_9ad749>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx940_srsrc>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_4318ca>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ buffer_store_dwordx3 :ref:`vdata<amdgpu_synid_gfx940_vdata_cfb402>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx940_srsrc>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_4318ca>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ buffer_store_dwordx4 :ref:`vdata<amdgpu_synid_gfx940_vdata_848ff7>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx940_srsrc>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_4318ca>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ buffer_store_format_d16_hi_x :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx940_srsrc>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_4318ca>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ buffer_store_format_d16_x :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx940_srsrc>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_4318ca>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ buffer_store_format_d16_xy :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx940_srsrc>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_4318ca>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ buffer_store_format_d16_xyz :ref:`vdata<amdgpu_synid_gfx940_vdata_9ad749>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx940_srsrc>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_4318ca>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ buffer_store_format_d16_xyzw :ref:`vdata<amdgpu_synid_gfx940_vdata_9ad749>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx940_srsrc>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_4318ca>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ buffer_store_format_x :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx940_srsrc>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_4318ca>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ buffer_store_format_xy :ref:`vdata<amdgpu_synid_gfx940_vdata_9ad749>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx940_srsrc>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_4318ca>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ buffer_store_format_xyz :ref:`vdata<amdgpu_synid_gfx940_vdata_cfb402>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx940_srsrc>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_4318ca>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ buffer_store_format_xyzw :ref:`vdata<amdgpu_synid_gfx940_vdata_848ff7>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx940_srsrc>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_4318ca>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ buffer_store_short :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx940_srsrc>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_4318ca>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ buffer_store_short_d16_hi :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx940_srsrc>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_4318ca>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`nt<amdgpu_synid_nt>` :ref:`sc1<amdgpu_synid_sc1>`
+ buffer_wbl2
+
+SMEM
+----
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ s_atc_probe :ref:`probe<amdgpu_synid_gfx940_probe>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_7b8c50>`
+ s_atc_probe_buffer :ref:`probe<amdgpu_synid_gfx940_probe>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_f33c5c>`
+ s_atomic_add :ref:`sdata<amdgpu_synid_gfx940_sdata_aefe00>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_7b8c50>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_add_x2 :ref:`sdata<amdgpu_synid_gfx940_sdata_eb6f2a>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_7b8c50>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_and :ref:`sdata<amdgpu_synid_gfx940_sdata_aefe00>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_7b8c50>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_and_x2 :ref:`sdata<amdgpu_synid_gfx940_sdata_eb6f2a>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_7b8c50>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_cmpswap :ref:`sdata<amdgpu_synid_gfx940_sdata_eb6f2a>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`::ref:`b32x2<amdgpu_synid_gfx940_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_7b8c50>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_cmpswap_x2 :ref:`sdata<amdgpu_synid_gfx940_sdata_c6aec1>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`::ref:`b64x2<amdgpu_synid_gfx940_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_7b8c50>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_dec :ref:`sdata<amdgpu_synid_gfx940_sdata_aefe00>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`::ref:`u32<amdgpu_synid_gfx940_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_7b8c50>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_dec_x2 :ref:`sdata<amdgpu_synid_gfx940_sdata_eb6f2a>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`::ref:`u64<amdgpu_synid_gfx940_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_7b8c50>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_inc :ref:`sdata<amdgpu_synid_gfx940_sdata_aefe00>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`::ref:`u32<amdgpu_synid_gfx940_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_7b8c50>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_inc_x2 :ref:`sdata<amdgpu_synid_gfx940_sdata_eb6f2a>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`::ref:`u64<amdgpu_synid_gfx940_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_7b8c50>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_or :ref:`sdata<amdgpu_synid_gfx940_sdata_aefe00>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_7b8c50>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_or_x2 :ref:`sdata<amdgpu_synid_gfx940_sdata_eb6f2a>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_7b8c50>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_smax :ref:`sdata<amdgpu_synid_gfx940_sdata_aefe00>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`::ref:`i32<amdgpu_synid_gfx940_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_7b8c50>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_smax_x2 :ref:`sdata<amdgpu_synid_gfx940_sdata_eb6f2a>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`::ref:`i64<amdgpu_synid_gfx940_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_7b8c50>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_smin :ref:`sdata<amdgpu_synid_gfx940_sdata_aefe00>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`::ref:`i32<amdgpu_synid_gfx940_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_7b8c50>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_smin_x2 :ref:`sdata<amdgpu_synid_gfx940_sdata_eb6f2a>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`::ref:`i64<amdgpu_synid_gfx940_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_7b8c50>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_sub :ref:`sdata<amdgpu_synid_gfx940_sdata_aefe00>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_7b8c50>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_sub_x2 :ref:`sdata<amdgpu_synid_gfx940_sdata_eb6f2a>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_7b8c50>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_swap :ref:`sdata<amdgpu_synid_gfx940_sdata_aefe00>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_7b8c50>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_swap_x2 :ref:`sdata<amdgpu_synid_gfx940_sdata_eb6f2a>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_7b8c50>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_umax :ref:`sdata<amdgpu_synid_gfx940_sdata_aefe00>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`::ref:`u32<amdgpu_synid_gfx940_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_7b8c50>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_umax_x2 :ref:`sdata<amdgpu_synid_gfx940_sdata_eb6f2a>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`::ref:`u64<amdgpu_synid_gfx940_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_7b8c50>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_umin :ref:`sdata<amdgpu_synid_gfx940_sdata_aefe00>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`::ref:`u32<amdgpu_synid_gfx940_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_7b8c50>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_umin_x2 :ref:`sdata<amdgpu_synid_gfx940_sdata_eb6f2a>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`::ref:`u64<amdgpu_synid_gfx940_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_7b8c50>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_xor :ref:`sdata<amdgpu_synid_gfx940_sdata_aefe00>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_7b8c50>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_xor_x2 :ref:`sdata<amdgpu_synid_gfx940_sdata_eb6f2a>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_7b8c50>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_add :ref:`sdata<amdgpu_synid_gfx940_sdata_aefe00>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_f33c5c>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_add_x2 :ref:`sdata<amdgpu_synid_gfx940_sdata_eb6f2a>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_f33c5c>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_and :ref:`sdata<amdgpu_synid_gfx940_sdata_aefe00>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_f33c5c>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_and_x2 :ref:`sdata<amdgpu_synid_gfx940_sdata_eb6f2a>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_f33c5c>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_cmpswap :ref:`sdata<amdgpu_synid_gfx940_sdata_eb6f2a>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`::ref:`b32x2<amdgpu_synid_gfx940_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_f33c5c>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_cmpswap_x2 :ref:`sdata<amdgpu_synid_gfx940_sdata_c6aec1>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`::ref:`b64x2<amdgpu_synid_gfx940_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_f33c5c>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_dec :ref:`sdata<amdgpu_synid_gfx940_sdata_aefe00>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`::ref:`u32<amdgpu_synid_gfx940_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_f33c5c>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_dec_x2 :ref:`sdata<amdgpu_synid_gfx940_sdata_eb6f2a>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`::ref:`u64<amdgpu_synid_gfx940_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_f33c5c>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_inc :ref:`sdata<amdgpu_synid_gfx940_sdata_aefe00>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`::ref:`u32<amdgpu_synid_gfx940_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_f33c5c>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_inc_x2 :ref:`sdata<amdgpu_synid_gfx940_sdata_eb6f2a>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`::ref:`u64<amdgpu_synid_gfx940_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_f33c5c>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_or :ref:`sdata<amdgpu_synid_gfx940_sdata_aefe00>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_f33c5c>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_or_x2 :ref:`sdata<amdgpu_synid_gfx940_sdata_eb6f2a>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_f33c5c>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_smax :ref:`sdata<amdgpu_synid_gfx940_sdata_aefe00>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`::ref:`i32<amdgpu_synid_gfx940_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_f33c5c>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_smax_x2 :ref:`sdata<amdgpu_synid_gfx940_sdata_eb6f2a>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`::ref:`i64<amdgpu_synid_gfx940_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_f33c5c>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_smin :ref:`sdata<amdgpu_synid_gfx940_sdata_aefe00>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`::ref:`i32<amdgpu_synid_gfx940_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_f33c5c>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_smin_x2 :ref:`sdata<amdgpu_synid_gfx940_sdata_eb6f2a>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`::ref:`i64<amdgpu_synid_gfx940_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_f33c5c>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_sub :ref:`sdata<amdgpu_synid_gfx940_sdata_aefe00>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_f33c5c>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_sub_x2 :ref:`sdata<amdgpu_synid_gfx940_sdata_eb6f2a>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_f33c5c>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_swap :ref:`sdata<amdgpu_synid_gfx940_sdata_aefe00>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_f33c5c>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_swap_x2 :ref:`sdata<amdgpu_synid_gfx940_sdata_eb6f2a>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_f33c5c>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_umax :ref:`sdata<amdgpu_synid_gfx940_sdata_aefe00>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`::ref:`u32<amdgpu_synid_gfx940_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_f33c5c>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_umax_x2 :ref:`sdata<amdgpu_synid_gfx940_sdata_eb6f2a>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`::ref:`u64<amdgpu_synid_gfx940_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_f33c5c>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_umin :ref:`sdata<amdgpu_synid_gfx940_sdata_aefe00>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`::ref:`u32<amdgpu_synid_gfx940_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_f33c5c>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_umin_x2 :ref:`sdata<amdgpu_synid_gfx940_sdata_eb6f2a>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`::ref:`u64<amdgpu_synid_gfx940_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_f33c5c>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_xor :ref:`sdata<amdgpu_synid_gfx940_sdata_aefe00>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_f33c5c>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_xor_x2 :ref:`sdata<amdgpu_synid_gfx940_sdata_eb6f2a>`::ref:`dst<amdgpu_synid_gfx940_dst_95761f>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_f33c5c>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_load_dword :ref:`sdst<amdgpu_synid_gfx940_sdst_94342d>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_f33c5c>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_load_dwordx16 :ref:`sdst<amdgpu_synid_gfx940_sdst_3bc700>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_f33c5c>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_load_dwordx2 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_f33c5c>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_load_dwordx4 :ref:`sdst<amdgpu_synid_gfx940_sdst_0804b1>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_f33c5c>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_load_dwordx8 :ref:`sdst<amdgpu_synid_gfx940_sdst_362c37>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_f33c5c>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_store_dword :ref:`sdata<amdgpu_synid_gfx940_sdata_595c25>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_f33c5c>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_store_dwordx2 :ref:`sdata<amdgpu_synid_gfx940_sdata_e9f591>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_f33c5c>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_store_dwordx4 :ref:`sdata<amdgpu_synid_gfx940_sdata_7cbd60>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_f33c5c>` :ref:`glc<amdgpu_synid_glc>`
+ s_dcache_discard :ref:`sbase<amdgpu_synid_gfx940_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_7b8c50>`
+ s_dcache_discard_x2 :ref:`sbase<amdgpu_synid_gfx940_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_7b8c50>`
+ s_dcache_inv
+ s_dcache_inv_vol
+ s_dcache_wb
+ s_dcache_wb_vol
+ s_load_dword :ref:`sdst<amdgpu_synid_gfx940_sdst_94342d>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_7b8c50>` :ref:`glc<amdgpu_synid_glc>`
+ s_load_dwordx16 :ref:`sdst<amdgpu_synid_gfx940_sdst_3bc700>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_7b8c50>` :ref:`glc<amdgpu_synid_glc>`
+ s_load_dwordx2 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_7b8c50>` :ref:`glc<amdgpu_synid_glc>`
+ s_load_dwordx4 :ref:`sdst<amdgpu_synid_gfx940_sdst_0804b1>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_7b8c50>` :ref:`glc<amdgpu_synid_glc>`
+ s_load_dwordx8 :ref:`sdst<amdgpu_synid_gfx940_sdst_362c37>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_7b8c50>` :ref:`glc<amdgpu_synid_glc>`
+ s_memrealtime :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`::ref:`b64<amdgpu_synid_gfx940_type_deviation>`
+ s_memtime :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`::ref:`b64<amdgpu_synid_gfx940_type_deviation>`
+ s_scratch_load_dword :ref:`sdst<amdgpu_synid_gfx940_sdst_94342d>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_0cd545>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_7b8c50>` :ref:`glc<amdgpu_synid_glc>`
+ s_scratch_load_dwordx2 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_0cd545>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_7b8c50>` :ref:`glc<amdgpu_synid_glc>`
+ s_scratch_load_dwordx4 :ref:`sdst<amdgpu_synid_gfx940_sdst_0804b1>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_0cd545>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_7b8c50>` :ref:`glc<amdgpu_synid_glc>`
+ s_scratch_store_dword :ref:`sdata<amdgpu_synid_gfx940_sdata_595c25>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_0cd545>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_7b8c50>` :ref:`glc<amdgpu_synid_glc>`
+ s_scratch_store_dwordx2 :ref:`sdata<amdgpu_synid_gfx940_sdata_e9f591>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_0cd545>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_7b8c50>` :ref:`glc<amdgpu_synid_glc>`
+ s_scratch_store_dwordx4 :ref:`sdata<amdgpu_synid_gfx940_sdata_7cbd60>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_0cd545>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_7b8c50>` :ref:`glc<amdgpu_synid_glc>`
+ s_store_dword :ref:`sdata<amdgpu_synid_gfx940_sdata_595c25>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_7b8c50>` :ref:`glc<amdgpu_synid_glc>`
+ s_store_dwordx2 :ref:`sdata<amdgpu_synid_gfx940_sdata_e9f591>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_7b8c50>` :ref:`glc<amdgpu_synid_glc>`
+ s_store_dwordx4 :ref:`sdata<amdgpu_synid_gfx940_sdata_7cbd60>`, :ref:`sbase<amdgpu_synid_gfx940_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx940_soffset_7b8c50>` :ref:`glc<amdgpu_synid_glc>`
+
+SOP1
+----
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST** **SRC**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ s_abs_i32 :ref:`sdst<amdgpu_synid_gfx940_sdst_06b266>`, :ref:`ssrc<amdgpu_synid_gfx940_ssrc_c5d631>`
+ s_and_saveexec_b64 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`ssrc<amdgpu_synid_gfx940_ssrc_aee59c>`
+ s_andn1_saveexec_b64 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`ssrc<amdgpu_synid_gfx940_ssrc_aee59c>`
+ s_andn1_wrexec_b64 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`ssrc<amdgpu_synid_gfx940_ssrc_aee59c>`
+ s_andn2_saveexec_b64 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`ssrc<amdgpu_synid_gfx940_ssrc_aee59c>`
+ s_andn2_wrexec_b64 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`ssrc<amdgpu_synid_gfx940_ssrc_aee59c>`
+ s_bcnt0_i32_b32 :ref:`sdst<amdgpu_synid_gfx940_sdst_06b266>`, :ref:`ssrc<amdgpu_synid_gfx940_ssrc_c5d631>`
+ s_bcnt0_i32_b64 :ref:`sdst<amdgpu_synid_gfx940_sdst_06b266>`, :ref:`ssrc<amdgpu_synid_gfx940_ssrc_aee59c>`
+ s_bcnt1_i32_b32 :ref:`sdst<amdgpu_synid_gfx940_sdst_06b266>`, :ref:`ssrc<amdgpu_synid_gfx940_ssrc_c5d631>`
+ s_bcnt1_i32_b64 :ref:`sdst<amdgpu_synid_gfx940_sdst_06b266>`, :ref:`ssrc<amdgpu_synid_gfx940_ssrc_aee59c>`
+ s_bitreplicate_b64_b32 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`ssrc<amdgpu_synid_gfx940_ssrc_c5d631>`
+ s_bitset0_b32 :ref:`sdst<amdgpu_synid_gfx940_sdst_06b266>`, :ref:`ssrc<amdgpu_synid_gfx940_ssrc_c5d631>`
+ s_bitset0_b64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`ssrc<amdgpu_synid_gfx940_ssrc_c5d631>`::ref:`b32<amdgpu_synid_gfx940_type_deviation>`
+ s_bitset1_b32 :ref:`sdst<amdgpu_synid_gfx940_sdst_06b266>`, :ref:`ssrc<amdgpu_synid_gfx940_ssrc_c5d631>`
+ s_bitset1_b64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`ssrc<amdgpu_synid_gfx940_ssrc_c5d631>`::ref:`b32<amdgpu_synid_gfx940_type_deviation>`
+ s_brev_b32 :ref:`sdst<amdgpu_synid_gfx940_sdst_06b266>`, :ref:`ssrc<amdgpu_synid_gfx940_ssrc_c5d631>`
+ s_brev_b64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`ssrc<amdgpu_synid_gfx940_ssrc_aee59c>`
+ s_cbranch_join :ref:`ssrc<amdgpu_synid_gfx940_ssrc_595c25>`
+ s_cmov_b32 :ref:`sdst<amdgpu_synid_gfx940_sdst_06b266>`, :ref:`ssrc<amdgpu_synid_gfx940_ssrc_c5d631>`
+ s_cmov_b64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`ssrc<amdgpu_synid_gfx940_ssrc_aee59c>`
+ s_ff0_i32_b32 :ref:`sdst<amdgpu_synid_gfx940_sdst_06b266>`, :ref:`ssrc<amdgpu_synid_gfx940_ssrc_c5d631>`
+ s_ff0_i32_b64 :ref:`sdst<amdgpu_synid_gfx940_sdst_06b266>`, :ref:`ssrc<amdgpu_synid_gfx940_ssrc_aee59c>`
+ s_ff1_i32_b32 :ref:`sdst<amdgpu_synid_gfx940_sdst_06b266>`, :ref:`ssrc<amdgpu_synid_gfx940_ssrc_c5d631>`
+ s_ff1_i32_b64 :ref:`sdst<amdgpu_synid_gfx940_sdst_06b266>`, :ref:`ssrc<amdgpu_synid_gfx940_ssrc_aee59c>`
+ s_flbit_i32 :ref:`sdst<amdgpu_synid_gfx940_sdst_06b266>`, :ref:`ssrc<amdgpu_synid_gfx940_ssrc_c5d631>`
+ s_flbit_i32_b32 :ref:`sdst<amdgpu_synid_gfx940_sdst_06b266>`, :ref:`ssrc<amdgpu_synid_gfx940_ssrc_c5d631>`
+ s_flbit_i32_b64 :ref:`sdst<amdgpu_synid_gfx940_sdst_06b266>`, :ref:`ssrc<amdgpu_synid_gfx940_ssrc_aee59c>`
+ s_flbit_i32_i64 :ref:`sdst<amdgpu_synid_gfx940_sdst_06b266>`, :ref:`ssrc<amdgpu_synid_gfx940_ssrc_aee59c>`
+ s_getpc_b64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`
+ s_mov_b32 :ref:`sdst<amdgpu_synid_gfx940_sdst_06b266>`, :ref:`ssrc<amdgpu_synid_gfx940_ssrc_c5d631>`
+ s_mov_b64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`ssrc<amdgpu_synid_gfx940_ssrc_aee59c>`
+ s_movreld_b32 :ref:`sdst<amdgpu_synid_gfx940_sdst_94342d>`, :ref:`ssrc<amdgpu_synid_gfx940_ssrc_c5d631>`
+ s_movreld_b64 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`ssrc<amdgpu_synid_gfx940_ssrc_aee59c>`
+ s_movrels_b32 :ref:`sdst<amdgpu_synid_gfx940_sdst_06b266>`, :ref:`ssrc<amdgpu_synid_gfx940_ssrc_595c25>`
+ s_movrels_b64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`ssrc<amdgpu_synid_gfx940_ssrc_e9f591>`
+ s_nand_saveexec_b64 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`ssrc<amdgpu_synid_gfx940_ssrc_aee59c>`
+ s_nor_saveexec_b64 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`ssrc<amdgpu_synid_gfx940_ssrc_aee59c>`
+ s_not_b32 :ref:`sdst<amdgpu_synid_gfx940_sdst_06b266>`, :ref:`ssrc<amdgpu_synid_gfx940_ssrc_c5d631>`
+ s_not_b64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`ssrc<amdgpu_synid_gfx940_ssrc_aee59c>`
+ s_or_saveexec_b64 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`ssrc<amdgpu_synid_gfx940_ssrc_aee59c>`
+ s_orn1_saveexec_b64 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`ssrc<amdgpu_synid_gfx940_ssrc_aee59c>`
+ s_orn2_saveexec_b64 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`ssrc<amdgpu_synid_gfx940_ssrc_aee59c>`
+ s_quadmask_b32 :ref:`sdst<amdgpu_synid_gfx940_sdst_06b266>`, :ref:`ssrc<amdgpu_synid_gfx940_ssrc_c5d631>`
+ s_quadmask_b64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`ssrc<amdgpu_synid_gfx940_ssrc_aee59c>`
+ s_rfe_b64 :ref:`ssrc<amdgpu_synid_gfx940_ssrc_e9f591>`
+ s_set_gpr_idx_idx :ref:`ssrc<amdgpu_synid_gfx940_ssrc_c5d631>`
+ s_setpc_b64 :ref:`ssrc<amdgpu_synid_gfx940_ssrc_e9f591>`
+ s_sext_i32_i16 :ref:`sdst<amdgpu_synid_gfx940_sdst_06b266>`, :ref:`ssrc<amdgpu_synid_gfx940_ssrc_c5d631>`
+ s_sext_i32_i8 :ref:`sdst<amdgpu_synid_gfx940_sdst_06b266>`, :ref:`ssrc<amdgpu_synid_gfx940_ssrc_c5d631>`
+ s_swappc_b64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`ssrc<amdgpu_synid_gfx940_ssrc_e9f591>`
+ s_wqm_b32 :ref:`sdst<amdgpu_synid_gfx940_sdst_06b266>`, :ref:`ssrc<amdgpu_synid_gfx940_ssrc_c5d631>`
+ s_wqm_b64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`ssrc<amdgpu_synid_gfx940_ssrc_aee59c>`
+ s_xnor_saveexec_b64 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`ssrc<amdgpu_synid_gfx940_ssrc_aee59c>`
+ s_xor_saveexec_b64 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`ssrc<amdgpu_synid_gfx940_ssrc_aee59c>`
+
+SOP2
+----
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST** **SRC0** **SRC1**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ s_abs
diff _i32 :ref:`sdst<amdgpu_synid_gfx940_sdst_06b266>`, :ref:`ssrc0<amdgpu_synid_gfx940_ssrc_c5d631>`, :ref:`ssrc1<amdgpu_synid_gfx940_ssrc_c5d631>`
+ s_add_i32 :ref:`sdst<amdgpu_synid_gfx940_sdst_06b266>`, :ref:`ssrc0<amdgpu_synid_gfx940_ssrc_c5d631>`, :ref:`ssrc1<amdgpu_synid_gfx940_ssrc_c5d631>`
+ s_add_u32 :ref:`sdst<amdgpu_synid_gfx940_sdst_06b266>`, :ref:`ssrc0<amdgpu_synid_gfx940_ssrc_c5d631>`, :ref:`ssrc1<amdgpu_synid_gfx940_ssrc_c5d631>`
+ s_addc_u32 :ref:`sdst<amdgpu_synid_gfx940_sdst_06b266>`, :ref:`ssrc0<amdgpu_synid_gfx940_ssrc_c5d631>`, :ref:`ssrc1<amdgpu_synid_gfx940_ssrc_c5d631>`
+ s_and_b32 :ref:`sdst<amdgpu_synid_gfx940_sdst_06b266>`, :ref:`ssrc0<amdgpu_synid_gfx940_ssrc_c5d631>`, :ref:`ssrc1<amdgpu_synid_gfx940_ssrc_c5d631>`
+ s_and_b64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`ssrc0<amdgpu_synid_gfx940_ssrc_aee59c>`, :ref:`ssrc1<amdgpu_synid_gfx940_ssrc_aee59c>`
+ s_andn2_b32 :ref:`sdst<amdgpu_synid_gfx940_sdst_06b266>`, :ref:`ssrc0<amdgpu_synid_gfx940_ssrc_c5d631>`, :ref:`ssrc1<amdgpu_synid_gfx940_ssrc_c5d631>`
+ s_andn2_b64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`ssrc0<amdgpu_synid_gfx940_ssrc_aee59c>`, :ref:`ssrc1<amdgpu_synid_gfx940_ssrc_aee59c>`
+ s_ashr_i32 :ref:`sdst<amdgpu_synid_gfx940_sdst_06b266>`, :ref:`ssrc0<amdgpu_synid_gfx940_ssrc_c5d631>`, :ref:`ssrc1<amdgpu_synid_gfx940_ssrc_c5d631>`::ref:`u32<amdgpu_synid_gfx940_type_deviation>`
+ s_ashr_i64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`ssrc0<amdgpu_synid_gfx940_ssrc_aee59c>`, :ref:`ssrc1<amdgpu_synid_gfx940_ssrc_c5d631>`::ref:`u32<amdgpu_synid_gfx940_type_deviation>`
+ s_bfe_i32 :ref:`sdst<amdgpu_synid_gfx940_sdst_06b266>`, :ref:`ssrc0<amdgpu_synid_gfx940_ssrc_c5d631>`, :ref:`ssrc1<amdgpu_synid_gfx940_ssrc_c5d631>`::ref:`u32<amdgpu_synid_gfx940_type_deviation>`
+ s_bfe_i64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`ssrc0<amdgpu_synid_gfx940_ssrc_aee59c>`, :ref:`ssrc1<amdgpu_synid_gfx940_ssrc_c5d631>`::ref:`u32<amdgpu_synid_gfx940_type_deviation>`
+ s_bfe_u32 :ref:`sdst<amdgpu_synid_gfx940_sdst_06b266>`, :ref:`ssrc0<amdgpu_synid_gfx940_ssrc_c5d631>`, :ref:`ssrc1<amdgpu_synid_gfx940_ssrc_c5d631>`
+ s_bfe_u64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`ssrc0<amdgpu_synid_gfx940_ssrc_aee59c>`, :ref:`ssrc1<amdgpu_synid_gfx940_ssrc_c5d631>`::ref:`u32<amdgpu_synid_gfx940_type_deviation>`
+ s_bfm_b32 :ref:`sdst<amdgpu_synid_gfx940_sdst_06b266>`, :ref:`ssrc0<amdgpu_synid_gfx940_ssrc_c5d631>`, :ref:`ssrc1<amdgpu_synid_gfx940_ssrc_c5d631>`
+ s_bfm_b64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`ssrc0<amdgpu_synid_gfx940_ssrc_c5d631>`::ref:`b32<amdgpu_synid_gfx940_type_deviation>`, :ref:`ssrc1<amdgpu_synid_gfx940_ssrc_c5d631>`::ref:`b32<amdgpu_synid_gfx940_type_deviation>`
+ s_cbranch_g_fork :ref:`ssrc0<amdgpu_synid_gfx940_ssrc_c31902>`, :ref:`ssrc1<amdgpu_synid_gfx940_ssrc_c31902>`
+ s_cselect_b32 :ref:`sdst<amdgpu_synid_gfx940_sdst_06b266>`, :ref:`ssrc0<amdgpu_synid_gfx940_ssrc_c5d631>`, :ref:`ssrc1<amdgpu_synid_gfx940_ssrc_c5d631>`
+ s_cselect_b64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`ssrc0<amdgpu_synid_gfx940_ssrc_aee59c>`, :ref:`ssrc1<amdgpu_synid_gfx940_ssrc_aee59c>`
+ s_lshl1_add_u32 :ref:`sdst<amdgpu_synid_gfx940_sdst_06b266>`, :ref:`ssrc0<amdgpu_synid_gfx940_ssrc_c5d631>`, :ref:`ssrc1<amdgpu_synid_gfx940_ssrc_c5d631>`
+ s_lshl2_add_u32 :ref:`sdst<amdgpu_synid_gfx940_sdst_06b266>`, :ref:`ssrc0<amdgpu_synid_gfx940_ssrc_c5d631>`, :ref:`ssrc1<amdgpu_synid_gfx940_ssrc_c5d631>`
+ s_lshl3_add_u32 :ref:`sdst<amdgpu_synid_gfx940_sdst_06b266>`, :ref:`ssrc0<amdgpu_synid_gfx940_ssrc_c5d631>`, :ref:`ssrc1<amdgpu_synid_gfx940_ssrc_c5d631>`
+ s_lshl4_add_u32 :ref:`sdst<amdgpu_synid_gfx940_sdst_06b266>`, :ref:`ssrc0<amdgpu_synid_gfx940_ssrc_c5d631>`, :ref:`ssrc1<amdgpu_synid_gfx940_ssrc_c5d631>`
+ s_lshl_b32 :ref:`sdst<amdgpu_synid_gfx940_sdst_06b266>`, :ref:`ssrc0<amdgpu_synid_gfx940_ssrc_c5d631>`, :ref:`ssrc1<amdgpu_synid_gfx940_ssrc_c5d631>`::ref:`u32<amdgpu_synid_gfx940_type_deviation>`
+ s_lshl_b64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`ssrc0<amdgpu_synid_gfx940_ssrc_aee59c>`, :ref:`ssrc1<amdgpu_synid_gfx940_ssrc_c5d631>`::ref:`u32<amdgpu_synid_gfx940_type_deviation>`
+ s_lshr_b32 :ref:`sdst<amdgpu_synid_gfx940_sdst_06b266>`, :ref:`ssrc0<amdgpu_synid_gfx940_ssrc_c5d631>`, :ref:`ssrc1<amdgpu_synid_gfx940_ssrc_c5d631>`::ref:`u32<amdgpu_synid_gfx940_type_deviation>`
+ s_lshr_b64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`ssrc0<amdgpu_synid_gfx940_ssrc_aee59c>`, :ref:`ssrc1<amdgpu_synid_gfx940_ssrc_c5d631>`::ref:`u32<amdgpu_synid_gfx940_type_deviation>`
+ s_max_i32 :ref:`sdst<amdgpu_synid_gfx940_sdst_06b266>`, :ref:`ssrc0<amdgpu_synid_gfx940_ssrc_c5d631>`, :ref:`ssrc1<amdgpu_synid_gfx940_ssrc_c5d631>`
+ s_max_u32 :ref:`sdst<amdgpu_synid_gfx940_sdst_06b266>`, :ref:`ssrc0<amdgpu_synid_gfx940_ssrc_c5d631>`, :ref:`ssrc1<amdgpu_synid_gfx940_ssrc_c5d631>`
+ s_min_i32 :ref:`sdst<amdgpu_synid_gfx940_sdst_06b266>`, :ref:`ssrc0<amdgpu_synid_gfx940_ssrc_c5d631>`, :ref:`ssrc1<amdgpu_synid_gfx940_ssrc_c5d631>`
+ s_min_u32 :ref:`sdst<amdgpu_synid_gfx940_sdst_06b266>`, :ref:`ssrc0<amdgpu_synid_gfx940_ssrc_c5d631>`, :ref:`ssrc1<amdgpu_synid_gfx940_ssrc_c5d631>`
+ s_mul_hi_i32 :ref:`sdst<amdgpu_synid_gfx940_sdst_06b266>`, :ref:`ssrc0<amdgpu_synid_gfx940_ssrc_c5d631>`, :ref:`ssrc1<amdgpu_synid_gfx940_ssrc_c5d631>`
+ s_mul_hi_u32 :ref:`sdst<amdgpu_synid_gfx940_sdst_06b266>`, :ref:`ssrc0<amdgpu_synid_gfx940_ssrc_c5d631>`, :ref:`ssrc1<amdgpu_synid_gfx940_ssrc_c5d631>`
+ s_mul_i32 :ref:`sdst<amdgpu_synid_gfx940_sdst_06b266>`, :ref:`ssrc0<amdgpu_synid_gfx940_ssrc_c5d631>`, :ref:`ssrc1<amdgpu_synid_gfx940_ssrc_c5d631>`
+ s_nand_b32 :ref:`sdst<amdgpu_synid_gfx940_sdst_06b266>`, :ref:`ssrc0<amdgpu_synid_gfx940_ssrc_c5d631>`, :ref:`ssrc1<amdgpu_synid_gfx940_ssrc_c5d631>`
+ s_nand_b64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`ssrc0<amdgpu_synid_gfx940_ssrc_aee59c>`, :ref:`ssrc1<amdgpu_synid_gfx940_ssrc_aee59c>`
+ s_nor_b32 :ref:`sdst<amdgpu_synid_gfx940_sdst_06b266>`, :ref:`ssrc0<amdgpu_synid_gfx940_ssrc_c5d631>`, :ref:`ssrc1<amdgpu_synid_gfx940_ssrc_c5d631>`
+ s_nor_b64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`ssrc0<amdgpu_synid_gfx940_ssrc_aee59c>`, :ref:`ssrc1<amdgpu_synid_gfx940_ssrc_aee59c>`
+ s_or_b32 :ref:`sdst<amdgpu_synid_gfx940_sdst_06b266>`, :ref:`ssrc0<amdgpu_synid_gfx940_ssrc_c5d631>`, :ref:`ssrc1<amdgpu_synid_gfx940_ssrc_c5d631>`
+ s_or_b64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`ssrc0<amdgpu_synid_gfx940_ssrc_aee59c>`, :ref:`ssrc1<amdgpu_synid_gfx940_ssrc_aee59c>`
+ s_orn2_b32 :ref:`sdst<amdgpu_synid_gfx940_sdst_06b266>`, :ref:`ssrc0<amdgpu_synid_gfx940_ssrc_c5d631>`, :ref:`ssrc1<amdgpu_synid_gfx940_ssrc_c5d631>`
+ s_orn2_b64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`ssrc0<amdgpu_synid_gfx940_ssrc_aee59c>`, :ref:`ssrc1<amdgpu_synid_gfx940_ssrc_aee59c>`
+ s_pack_hh_b32_b16 :ref:`sdst<amdgpu_synid_gfx940_sdst_06b266>`, :ref:`ssrc0<amdgpu_synid_gfx940_ssrc_c5d631>`::ref:`b32<amdgpu_synid_gfx940_type_deviation>`, :ref:`ssrc1<amdgpu_synid_gfx940_ssrc_c5d631>`::ref:`b32<amdgpu_synid_gfx940_type_deviation>`
+ s_pack_lh_b32_b16 :ref:`sdst<amdgpu_synid_gfx940_sdst_06b266>`, :ref:`ssrc0<amdgpu_synid_gfx940_ssrc_c5d631>`, :ref:`ssrc1<amdgpu_synid_gfx940_ssrc_c5d631>`::ref:`b32<amdgpu_synid_gfx940_type_deviation>`
+ s_pack_ll_b32_b16 :ref:`sdst<amdgpu_synid_gfx940_sdst_06b266>`, :ref:`ssrc0<amdgpu_synid_gfx940_ssrc_c5d631>`, :ref:`ssrc1<amdgpu_synid_gfx940_ssrc_c5d631>`
+ s_rfe_restore_b64 :ref:`ssrc0<amdgpu_synid_gfx940_ssrc_aee59c>`, :ref:`ssrc1<amdgpu_synid_gfx940_ssrc_c5d631>`::ref:`b32<amdgpu_synid_gfx940_type_deviation>`
+ s_sub_i32 :ref:`sdst<amdgpu_synid_gfx940_sdst_06b266>`, :ref:`ssrc0<amdgpu_synid_gfx940_ssrc_c5d631>`, :ref:`ssrc1<amdgpu_synid_gfx940_ssrc_c5d631>`
+ s_sub_u32 :ref:`sdst<amdgpu_synid_gfx940_sdst_06b266>`, :ref:`ssrc0<amdgpu_synid_gfx940_ssrc_c5d631>`, :ref:`ssrc1<amdgpu_synid_gfx940_ssrc_c5d631>`
+ s_subb_u32 :ref:`sdst<amdgpu_synid_gfx940_sdst_06b266>`, :ref:`ssrc0<amdgpu_synid_gfx940_ssrc_c5d631>`, :ref:`ssrc1<amdgpu_synid_gfx940_ssrc_c5d631>`
+ s_xnor_b32 :ref:`sdst<amdgpu_synid_gfx940_sdst_06b266>`, :ref:`ssrc0<amdgpu_synid_gfx940_ssrc_c5d631>`, :ref:`ssrc1<amdgpu_synid_gfx940_ssrc_c5d631>`
+ s_xnor_b64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`ssrc0<amdgpu_synid_gfx940_ssrc_aee59c>`, :ref:`ssrc1<amdgpu_synid_gfx940_ssrc_aee59c>`
+ s_xor_b32 :ref:`sdst<amdgpu_synid_gfx940_sdst_06b266>`, :ref:`ssrc0<amdgpu_synid_gfx940_ssrc_c5d631>`, :ref:`ssrc1<amdgpu_synid_gfx940_ssrc_c5d631>`
+ s_xor_b64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`ssrc0<amdgpu_synid_gfx940_ssrc_aee59c>`, :ref:`ssrc1<amdgpu_synid_gfx940_ssrc_aee59c>`
+
+SOPC
+----
+
+.. parsed-literal::
+
+ **INSTRUCTION** **SRC0** **SRC1**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ s_bitcmp0_b32 :ref:`ssrc0<amdgpu_synid_gfx940_ssrc_c5d631>`, :ref:`ssrc1<amdgpu_synid_gfx940_ssrc_c5d631>`
+ s_bitcmp0_b64 :ref:`ssrc0<amdgpu_synid_gfx940_ssrc_aee59c>`, :ref:`ssrc1<amdgpu_synid_gfx940_ssrc_c5d631>`::ref:`u32<amdgpu_synid_gfx940_type_deviation>`
+ s_bitcmp1_b32 :ref:`ssrc0<amdgpu_synid_gfx940_ssrc_c5d631>`, :ref:`ssrc1<amdgpu_synid_gfx940_ssrc_c5d631>`
+ s_bitcmp1_b64 :ref:`ssrc0<amdgpu_synid_gfx940_ssrc_aee59c>`, :ref:`ssrc1<amdgpu_synid_gfx940_ssrc_c5d631>`::ref:`u32<amdgpu_synid_gfx940_type_deviation>`
+ s_cmp_eq_i32 :ref:`ssrc0<amdgpu_synid_gfx940_ssrc_c5d631>`, :ref:`ssrc1<amdgpu_synid_gfx940_ssrc_c5d631>`
+ s_cmp_eq_u32 :ref:`ssrc0<amdgpu_synid_gfx940_ssrc_c5d631>`, :ref:`ssrc1<amdgpu_synid_gfx940_ssrc_c5d631>`
+ s_cmp_eq_u64 :ref:`ssrc0<amdgpu_synid_gfx940_ssrc_aee59c>`, :ref:`ssrc1<amdgpu_synid_gfx940_ssrc_aee59c>`
+ s_cmp_ge_i32 :ref:`ssrc0<amdgpu_synid_gfx940_ssrc_c5d631>`, :ref:`ssrc1<amdgpu_synid_gfx940_ssrc_c5d631>`
+ s_cmp_ge_u32 :ref:`ssrc0<amdgpu_synid_gfx940_ssrc_c5d631>`, :ref:`ssrc1<amdgpu_synid_gfx940_ssrc_c5d631>`
+ s_cmp_gt_i32 :ref:`ssrc0<amdgpu_synid_gfx940_ssrc_c5d631>`, :ref:`ssrc1<amdgpu_synid_gfx940_ssrc_c5d631>`
+ s_cmp_gt_u32 :ref:`ssrc0<amdgpu_synid_gfx940_ssrc_c5d631>`, :ref:`ssrc1<amdgpu_synid_gfx940_ssrc_c5d631>`
+ s_cmp_le_i32 :ref:`ssrc0<amdgpu_synid_gfx940_ssrc_c5d631>`, :ref:`ssrc1<amdgpu_synid_gfx940_ssrc_c5d631>`
+ s_cmp_le_u32 :ref:`ssrc0<amdgpu_synid_gfx940_ssrc_c5d631>`, :ref:`ssrc1<amdgpu_synid_gfx940_ssrc_c5d631>`
+ s_cmp_lg_i32 :ref:`ssrc0<amdgpu_synid_gfx940_ssrc_c5d631>`, :ref:`ssrc1<amdgpu_synid_gfx940_ssrc_c5d631>`
+ s_cmp_lg_u32 :ref:`ssrc0<amdgpu_synid_gfx940_ssrc_c5d631>`, :ref:`ssrc1<amdgpu_synid_gfx940_ssrc_c5d631>`
+ s_cmp_lg_u64 :ref:`ssrc0<amdgpu_synid_gfx940_ssrc_aee59c>`, :ref:`ssrc1<amdgpu_synid_gfx940_ssrc_aee59c>`
+ s_cmp_lt_i32 :ref:`ssrc0<amdgpu_synid_gfx940_ssrc_c5d631>`, :ref:`ssrc1<amdgpu_synid_gfx940_ssrc_c5d631>`
+ s_cmp_lt_u32 :ref:`ssrc0<amdgpu_synid_gfx940_ssrc_c5d631>`, :ref:`ssrc1<amdgpu_synid_gfx940_ssrc_c5d631>`
+ s_set_gpr_idx_on :ref:`ssrc<amdgpu_synid_gfx940_ssrc_c5d631>`, :ref:`imask<amdgpu_synid_gfx940_imask>`
+ s_setvskip :ref:`ssrc0<amdgpu_synid_gfx940_ssrc_c5d631>`, :ref:`ssrc1<amdgpu_synid_gfx940_ssrc_c5d631>`
+
+SOPK
+----
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST** **SRC0** **SRC1**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ s_addk_i32 :ref:`sdst<amdgpu_synid_gfx940_sdst_06b266>`, :ref:`imm16<amdgpu_synid_gfx940_imm16_73139a>`
+ s_call_b64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`label<amdgpu_synid_gfx940_label>`
+ s_cbranch_i_fork :ref:`ssrc<amdgpu_synid_gfx940_ssrc_65f041>`, :ref:`label<amdgpu_synid_gfx940_label>`
+ s_cmovk_i32 :ref:`sdst<amdgpu_synid_gfx940_sdst_06b266>`, :ref:`imm16<amdgpu_synid_gfx940_imm16_73139a>`
+ s_cmpk_eq_i32 :ref:`ssrc<amdgpu_synid_gfx940_ssrc_c8a322>`, :ref:`imm16<amdgpu_synid_gfx940_imm16_73139a>`
+ s_cmpk_eq_u32 :ref:`ssrc<amdgpu_synid_gfx940_ssrc_c8a322>`, :ref:`imm16<amdgpu_synid_gfx940_imm16_a04fb3>`
+ s_cmpk_ge_i32 :ref:`ssrc<amdgpu_synid_gfx940_ssrc_c8a322>`, :ref:`imm16<amdgpu_synid_gfx940_imm16_73139a>`
+ s_cmpk_ge_u32 :ref:`ssrc<amdgpu_synid_gfx940_ssrc_c8a322>`, :ref:`imm16<amdgpu_synid_gfx940_imm16_a04fb3>`
+ s_cmpk_gt_i32 :ref:`ssrc<amdgpu_synid_gfx940_ssrc_c8a322>`, :ref:`imm16<amdgpu_synid_gfx940_imm16_73139a>`
+ s_cmpk_gt_u32 :ref:`ssrc<amdgpu_synid_gfx940_ssrc_c8a322>`, :ref:`imm16<amdgpu_synid_gfx940_imm16_a04fb3>`
+ s_cmpk_le_i32 :ref:`ssrc<amdgpu_synid_gfx940_ssrc_c8a322>`, :ref:`imm16<amdgpu_synid_gfx940_imm16_73139a>`
+ s_cmpk_le_u32 :ref:`ssrc<amdgpu_synid_gfx940_ssrc_c8a322>`, :ref:`imm16<amdgpu_synid_gfx940_imm16_a04fb3>`
+ s_cmpk_lg_i32 :ref:`ssrc<amdgpu_synid_gfx940_ssrc_c8a322>`, :ref:`imm16<amdgpu_synid_gfx940_imm16_73139a>`
+ s_cmpk_lg_u32 :ref:`ssrc<amdgpu_synid_gfx940_ssrc_c8a322>`, :ref:`imm16<amdgpu_synid_gfx940_imm16_a04fb3>`
+ s_cmpk_lt_i32 :ref:`ssrc<amdgpu_synid_gfx940_ssrc_c8a322>`, :ref:`imm16<amdgpu_synid_gfx940_imm16_73139a>`
+ s_cmpk_lt_u32 :ref:`ssrc<amdgpu_synid_gfx940_ssrc_c8a322>`, :ref:`imm16<amdgpu_synid_gfx940_imm16_a04fb3>`
+ s_getreg_b32 :ref:`sdst<amdgpu_synid_gfx940_sdst_06b266>`, :ref:`hwreg<amdgpu_synid_gfx940_hwreg>`
+ s_movk_i32 :ref:`sdst<amdgpu_synid_gfx940_sdst_06b266>`, :ref:`imm16<amdgpu_synid_gfx940_imm16_73139a>`
+ s_mulk_i32 :ref:`sdst<amdgpu_synid_gfx940_sdst_06b266>`, :ref:`imm16<amdgpu_synid_gfx940_imm16_73139a>`
+ s_setreg_b32 :ref:`hwreg<amdgpu_synid_gfx940_hwreg>`, :ref:`ssrc<amdgpu_synid_gfx940_ssrc_c8a322>`
+ s_setreg_imm32_b32 :ref:`hwreg<amdgpu_synid_gfx940_hwreg>`, :ref:`simm32<amdgpu_synid_gfx940_simm32_a3e80c>`
+
+SOPP
+----
+
+.. parsed-literal::
+
+ **INSTRUCTION** **SRC**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ s_barrier
+ s_branch :ref:`label<amdgpu_synid_gfx940_label>`
+ s_cbranch_cdbgsys :ref:`label<amdgpu_synid_gfx940_label>`
+ s_cbranch_cdbgsys_and_user :ref:`label<amdgpu_synid_gfx940_label>`
+ s_cbranch_cdbgsys_or_user :ref:`label<amdgpu_synid_gfx940_label>`
+ s_cbranch_cdbguser :ref:`label<amdgpu_synid_gfx940_label>`
+ s_cbranch_execnz :ref:`label<amdgpu_synid_gfx940_label>`
+ s_cbranch_execz :ref:`label<amdgpu_synid_gfx940_label>`
+ s_cbranch_scc0 :ref:`label<amdgpu_synid_gfx940_label>`
+ s_cbranch_scc1 :ref:`label<amdgpu_synid_gfx940_label>`
+ s_cbranch_vccnz :ref:`label<amdgpu_synid_gfx940_label>`
+ s_cbranch_vccz :ref:`label<amdgpu_synid_gfx940_label>`
+ s_decperflevel :ref:`imm16<amdgpu_synid_gfx940_imm16_73139a>`
+ s_endpgm
+ s_endpgm_ordered_ps_done
+ s_endpgm_saved
+ s_icache_inv
+ s_incperflevel :ref:`imm16<amdgpu_synid_gfx940_imm16_73139a>`
+ s_nop :ref:`imm16<amdgpu_synid_gfx940_imm16_73139a>`
+ s_sendmsg :ref:`msg<amdgpu_synid_gfx940_msg>`
+ s_sendmsghalt :ref:`msg<amdgpu_synid_gfx940_msg>`
+ s_set_gpr_idx_mode :ref:`imask<amdgpu_synid_gfx940_imask>`
+ s_set_gpr_idx_off
+ s_sethalt :ref:`imm16<amdgpu_synid_gfx940_imm16_73139a>`
+ s_setkill :ref:`imm16<amdgpu_synid_gfx940_imm16_73139a>`
+ s_setprio :ref:`imm16<amdgpu_synid_gfx940_imm16_73139a>`
+ s_sleep :ref:`imm16<amdgpu_synid_gfx940_imm16_73139a>`
+ s_trap :ref:`imm16<amdgpu_synid_gfx940_imm16_73139a>`
+ s_ttracedata
+ s_waitcnt :ref:`waitcnt<amdgpu_synid_gfx940_waitcnt>`
+ s_wakeup
+
+VOP1
+----
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST** **SRC** **MODIFIERS**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ v_accvgpr_mov_b32 :ref:`vdst<amdgpu_synid_gfx940_vdst_78dd0a>`, :ref:`vsrc<amdgpu_synid_gfx940_vsrc_1027ca>`
+ v_bfrev_b32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_e1561c>`
+ v_bfrev_b32_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx940_vsrc_6802ce>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_bfrev_b32_sdwa :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_ceil_f16 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_e1561c>`
+ v_ceil_f16_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx940_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_ceil_f16_sdwa :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_ceil_f32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_e1561c>`
+ v_ceil_f32_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx940_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_ceil_f32_sdwa :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_ceil_f64 :ref:`vdst<amdgpu_synid_gfx940_vdst_bdb32f>`, :ref:`src<amdgpu_synid_gfx940_src_56ed80>`
+ v_ceil_f64_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_bdb32f>`, :ref:`vsrc<amdgpu_synid_gfx940_vsrc_fd235e>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`dpp64_ctrl<amdgpu_synid_dpp64_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_clrexcp
+ v_cos_f16 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_e1561c>`
+ v_cos_f16_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx940_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_cos_f16_sdwa :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cos_f32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_e1561c>`
+ v_cos_f32_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx940_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_cos_f32_sdwa :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_f16_f32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_e1561c>`
+ v_cvt_f16_f32_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx940_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_cvt_f16_f32_sdwa :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_f16_i16 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_4de5c6>`
+ v_cvt_f16_i16_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx940_vsrc_6802ce>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_cvt_f16_i16_sdwa :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d95796>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_f16_u16 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_4de5c6>`
+ v_cvt_f16_u16_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx940_vsrc_6802ce>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_cvt_f16_u16_sdwa :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d95796>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_f32_f16 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_e1561c>`
+ v_cvt_f32_f16_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx940_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_cvt_f32_f16_sdwa :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_f32_f64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_56ed80>`
+ v_cvt_f32_f64_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx940_vsrc_fd235e>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`dpp64_ctrl<amdgpu_synid_dpp64_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_cvt_f32_i32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_e1561c>`
+ v_cvt_f32_i32_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx940_vsrc_6802ce>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_cvt_f32_i32_sdwa :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_f32_u32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_e1561c>`
+ v_cvt_f32_u32_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx940_vsrc_6802ce>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_cvt_f32_u32_sdwa :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_f32_ubyte0 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_e1561c>`
+ v_cvt_f32_ubyte0_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx940_vsrc_6802ce>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_cvt_f32_ubyte0_sdwa :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_f32_ubyte1 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_e1561c>`
+ v_cvt_f32_ubyte1_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx940_vsrc_6802ce>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_cvt_f32_ubyte1_sdwa :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_f32_ubyte2 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_e1561c>`
+ v_cvt_f32_ubyte2_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx940_vsrc_6802ce>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_cvt_f32_ubyte2_sdwa :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_f32_ubyte3 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_e1561c>`
+ v_cvt_f32_ubyte3_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx940_vsrc_6802ce>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_cvt_f32_ubyte3_sdwa :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_f64_f32 :ref:`vdst<amdgpu_synid_gfx940_vdst_bdb32f>`, :ref:`src<amdgpu_synid_gfx940_src_e1561c>`
+ v_cvt_f64_i32 :ref:`vdst<amdgpu_synid_gfx940_vdst_bdb32f>`, :ref:`src<amdgpu_synid_gfx940_src_e1561c>`
+ v_cvt_f64_u32 :ref:`vdst<amdgpu_synid_gfx940_vdst_bdb32f>`, :ref:`src<amdgpu_synid_gfx940_src_e1561c>`
+ v_cvt_flr_i32_f32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_e1561c>`
+ v_cvt_flr_i32_f32_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx940_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_cvt_flr_i32_f32_sdwa :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_i16_f16 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_e1561c>`
+ v_cvt_i16_f16_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx940_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_cvt_i16_f16_sdwa :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_i32_f32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_e1561c>`
+ v_cvt_i32_f32_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx940_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_cvt_i32_f32_sdwa :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_i32_f64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_56ed80>`
+ v_cvt_i32_f64_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx940_vsrc_fd235e>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`dpp64_ctrl<amdgpu_synid_dpp64_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_cvt_norm_i16_f16 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_e1561c>`
+ v_cvt_norm_i16_f16_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx940_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_cvt_norm_i16_f16_sdwa :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_norm_u16_f16 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_e1561c>`
+ v_cvt_norm_u16_f16_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx940_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_cvt_norm_u16_f16_sdwa :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_off_f32_i4 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_e1561c>`
+ v_cvt_off_f32_i4_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx940_vsrc_6802ce>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_cvt_off_f32_i4_sdwa :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_rpi_i32_f32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_e1561c>`
+ v_cvt_rpi_i32_f32_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx940_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_cvt_rpi_i32_f32_sdwa :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_u16_f16 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_e1561c>`
+ v_cvt_u16_f16_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx940_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_cvt_u16_f16_sdwa :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_u32_f32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_e1561c>`
+ v_cvt_u32_f32_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx940_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_cvt_u32_f32_sdwa :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_u32_f64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_56ed80>`
+ v_cvt_u32_f64_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx940_vsrc_fd235e>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`dpp64_ctrl<amdgpu_synid_dpp64_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_exp_f16 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_e1561c>`
+ v_exp_f16_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx940_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_exp_f16_sdwa :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_exp_f32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_e1561c>`
+ v_exp_f32_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx940_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_exp_f32_sdwa :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_exp_legacy_f32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_e1561c>`
+ v_exp_legacy_f32_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx940_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_exp_legacy_f32_sdwa :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_ffbh_i32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_e1561c>`
+ v_ffbh_i32_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx940_vsrc_6802ce>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_ffbh_i32_sdwa :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_ffbh_u32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_e1561c>`
+ v_ffbh_u32_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx940_vsrc_6802ce>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_ffbh_u32_sdwa :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_ffbl_b32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_e1561c>`
+ v_ffbl_b32_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx940_vsrc_6802ce>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_ffbl_b32_sdwa :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_floor_f16 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_e1561c>`
+ v_floor_f16_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx940_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_floor_f16_sdwa :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_floor_f32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_e1561c>`
+ v_floor_f32_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx940_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_floor_f32_sdwa :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_floor_f64 :ref:`vdst<amdgpu_synid_gfx940_vdst_bdb32f>`, :ref:`src<amdgpu_synid_gfx940_src_56ed80>`
+ v_floor_f64_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_bdb32f>`, :ref:`vsrc<amdgpu_synid_gfx940_vsrc_fd235e>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`dpp64_ctrl<amdgpu_synid_dpp64_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_fract_f16 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_e1561c>`
+ v_fract_f16_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx940_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_fract_f16_sdwa :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_fract_f32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_e1561c>`
+ v_fract_f32_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx940_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_fract_f32_sdwa :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_fract_f64 :ref:`vdst<amdgpu_synid_gfx940_vdst_bdb32f>`, :ref:`src<amdgpu_synid_gfx940_src_56ed80>`
+ v_fract_f64_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_bdb32f>`, :ref:`vsrc<amdgpu_synid_gfx940_vsrc_fd235e>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`dpp64_ctrl<amdgpu_synid_dpp64_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_frexp_exp_i16_f16 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_e1561c>`
+ v_frexp_exp_i16_f16_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx940_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_frexp_exp_i16_f16_sdwa :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_frexp_exp_i32_f32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_e1561c>`
+ v_frexp_exp_i32_f32_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx940_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_frexp_exp_i32_f32_sdwa :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_frexp_exp_i32_f64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_56ed80>`
+ v_frexp_exp_i32_f64_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx940_vsrc_fd235e>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`dpp64_ctrl<amdgpu_synid_dpp64_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_frexp_mant_f16 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_e1561c>`
+ v_frexp_mant_f16_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx940_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_frexp_mant_f16_sdwa :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_frexp_mant_f32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_e1561c>`
+ v_frexp_mant_f32_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx940_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_frexp_mant_f32_sdwa :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_frexp_mant_f64 :ref:`vdst<amdgpu_synid_gfx940_vdst_bdb32f>`, :ref:`src<amdgpu_synid_gfx940_src_56ed80>`
+ v_frexp_mant_f64_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_bdb32f>`, :ref:`vsrc<amdgpu_synid_gfx940_vsrc_fd235e>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`dpp64_ctrl<amdgpu_synid_dpp64_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_log_f16 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_e1561c>`
+ v_log_f16_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx940_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_log_f16_sdwa :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_log_f32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_e1561c>`
+ v_log_f32_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx940_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_log_f32_sdwa :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_log_legacy_f32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_e1561c>`
+ v_log_legacy_f32_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx940_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_log_legacy_f32_sdwa :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_mov_b32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_e1561c>`
+ v_mov_b32_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx940_vsrc_6802ce>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_mov_b32_sdwa :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_mov_b64 :ref:`vdst<amdgpu_synid_gfx940_vdst_bdb32f>`, :ref:`src<amdgpu_synid_gfx940_src_56ed80>`
+ v_mov_b64_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_bdb32f>`, :ref:`vsrc<amdgpu_synid_gfx940_vsrc_fd235e>` :ref:`dpp64_ctrl<amdgpu_synid_dpp64_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_nop
+ v_not_b32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_e1561c>`
+ v_not_b32_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx940_vsrc_6802ce>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_not_b32_sdwa :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_rcp_f16 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_e1561c>`
+ v_rcp_f16_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx940_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_rcp_f16_sdwa :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_rcp_f32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_e1561c>`
+ v_rcp_f32_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx940_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_rcp_f32_sdwa :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_rcp_f64 :ref:`vdst<amdgpu_synid_gfx940_vdst_bdb32f>`, :ref:`src<amdgpu_synid_gfx940_src_56ed80>`
+ v_rcp_iflag_f32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_e1561c>`
+ v_rcp_iflag_f32_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx940_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_rcp_iflag_f32_sdwa :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_readfirstlane_b32 :ref:`sdst<amdgpu_synid_gfx940_sdst_59204c>`, :ref:`vsrc<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_rndne_f16 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_e1561c>`
+ v_rndne_f16_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx940_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_rndne_f16_sdwa :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_rndne_f32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_e1561c>`
+ v_rndne_f32_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx940_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_rndne_f32_sdwa :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_rndne_f64 :ref:`vdst<amdgpu_synid_gfx940_vdst_bdb32f>`, :ref:`src<amdgpu_synid_gfx940_src_56ed80>`
+ v_rsq_f16 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_e1561c>`
+ v_rsq_f16_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx940_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_rsq_f16_sdwa :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_rsq_f32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_e1561c>`
+ v_rsq_f32_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx940_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_rsq_f32_sdwa :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_rsq_f64 :ref:`vdst<amdgpu_synid_gfx940_vdst_bdb32f>`, :ref:`src<amdgpu_synid_gfx940_src_56ed80>`
+ v_sat_pk_u8_i16 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`::ref:`u8x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`src<amdgpu_synid_gfx940_src_e1561c>`
+ v_sat_pk_u8_i16_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`::ref:`u8x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc<amdgpu_synid_gfx940_vsrc_6802ce>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_sat_pk_u8_i16_sdwa :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`::ref:`u8x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_screen_partition_4se_b32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_e1561c>`
+ v_screen_partition_4se_b32_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx940_vsrc_6802ce>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_screen_partition_4se_b32_sdwa :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_sin_f16 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_e1561c>`
+ v_sin_f16_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx940_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_sin_f16_sdwa :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_sin_f32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_e1561c>`
+ v_sin_f32_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx940_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_sin_f32_sdwa :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_sqrt_f16 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_e1561c>`
+ v_sqrt_f16_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx940_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_sqrt_f16_sdwa :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_sqrt_f32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_e1561c>`
+ v_sqrt_f32_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx940_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_sqrt_f32_sdwa :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_sqrt_f64 :ref:`vdst<amdgpu_synid_gfx940_vdst_bdb32f>`, :ref:`src<amdgpu_synid_gfx940_src_56ed80>`
+ v_swap_b32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_trunc_f16 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_e1561c>`
+ v_trunc_f16_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx940_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_trunc_f16_sdwa :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_trunc_f32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_e1561c>`
+ v_trunc_f32_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx940_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_trunc_f32_sdwa :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_trunc_f64 :ref:`vdst<amdgpu_synid_gfx940_vdst_bdb32f>`, :ref:`src<amdgpu_synid_gfx940_src_56ed80>`
+ v_trunc_f64_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_bdb32f>`, :ref:`vsrc<amdgpu_synid_gfx940_vsrc_fd235e>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`dpp64_ctrl<amdgpu_synid_dpp64_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+
+VOP2
+----
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST0** **DST1** **SRC0** **SRC1** **SRC2** **MODIFIERS**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ v_add_co_u32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_add_co_u32_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_add_co_u32_sdwa :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_add_f16 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_add_f16_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_add_f16_sdwa :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_add_f32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_add_f32_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_add_f32_sdwa :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_add_u16 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_4de5c6>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_add_u16_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_add_u16_sdwa :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_add_u32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_add_u32_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_add_u32_sdwa :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_addc_co_u32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`, :ref:`vcc<amdgpu_synid_gfx940_vcc>`
+ v_addc_co_u32_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`, :ref:`vcc<amdgpu_synid_gfx940_vcc>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_addc_co_u32_sdwa :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>`, :ref:`vcc<amdgpu_synid_gfx940_vcc>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_and_b32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_and_b32_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_and_b32_sdwa :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_ashrrev_i16 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_4de5c6>`::ref:`u16<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_ashrrev_i16_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_6802ce>`::ref:`u16<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_ashrrev_i16_sdwa :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>`::ref:`u16<amdgpu_synid_gfx940_type_deviation>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_ashrrev_i32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`::ref:`u32<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_ashrrev_i32_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_6802ce>`::ref:`u32<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_ashrrev_i32_sdwa :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>`::ref:`u32<amdgpu_synid_gfx940_type_deviation>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cndmask_b32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`, :ref:`vcc<amdgpu_synid_gfx940_vcc>`
+ v_cndmask_b32_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`, :ref:`vcc<amdgpu_synid_gfx940_vcc>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_cndmask_b32_sdwa :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>`, :ref:`vcc<amdgpu_synid_gfx940_vcc>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_dot2c_f32_f16 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`::ref:`f16x2<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`::ref:`f16x2<amdgpu_synid_gfx940_type_deviation>`
+ v_dot2c_f32_f16_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_6802ce>`::ref:`f16x2<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`::ref:`f16x2<amdgpu_synid_gfx940_type_deviation>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_dot2c_i32_i16 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`::ref:`i16x2<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`::ref:`i16x2<amdgpu_synid_gfx940_type_deviation>`
+ v_dot2c_i32_i16_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_6802ce>`::ref:`i16x2<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`::ref:`i16x2<amdgpu_synid_gfx940_type_deviation>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_dot4c_i32_i8 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`::ref:`i8x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`::ref:`i8x4<amdgpu_synid_gfx940_type_deviation>`
+ v_dot4c_i32_i8_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_6802ce>`::ref:`i8x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`::ref:`i8x4<amdgpu_synid_gfx940_type_deviation>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_dot8c_i32_i4 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`::ref:`i4x8<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`::ref:`i4x8<amdgpu_synid_gfx940_type_deviation>`
+ v_dot8c_i32_i4_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_6802ce>`::ref:`i4x8<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`::ref:`i4x8<amdgpu_synid_gfx940_type_deviation>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_fmaak_f32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`, :ref:`simm32<amdgpu_synid_gfx940_simm32_6f0844>`
+ v_fmac_f32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_fmac_f32_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_fmac_f64 :ref:`vdst<amdgpu_synid_gfx940_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx940_src_56ed80>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_fd235e>`
+ v_fmac_f64_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_bdb32f>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_fd235e>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_fd235e>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`dpp64_ctrl<amdgpu_synid_dpp64_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_fmamk_f32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`simm32<amdgpu_synid_gfx940_simm32_6f0844>`, :ref:`vsrc2<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_ldexp_f16 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`::ref:`i16<amdgpu_synid_gfx940_type_deviation>`
+ v_ldexp_f16_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`::ref:`i16<amdgpu_synid_gfx940_type_deviation>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_ldexp_f16_sdwa :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>`::ref:`i16<amdgpu_synid_gfx940_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_lshlrev_b16 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_4de5c6>`::ref:`u16<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_lshlrev_b16_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_6802ce>`::ref:`u16<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_lshlrev_b16_sdwa :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>`::ref:`u16<amdgpu_synid_gfx940_type_deviation>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_lshlrev_b32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`::ref:`u32<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_lshlrev_b32_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_6802ce>`::ref:`u32<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_lshlrev_b32_sdwa :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>`::ref:`u32<amdgpu_synid_gfx940_type_deviation>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_lshrrev_b16 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_4de5c6>`::ref:`u16<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_lshrrev_b16_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_6802ce>`::ref:`u16<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_lshrrev_b16_sdwa :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>`::ref:`u16<amdgpu_synid_gfx940_type_deviation>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_lshrrev_b32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`::ref:`u32<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_lshrrev_b32_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_6802ce>`::ref:`u32<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_lshrrev_b32_sdwa :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>`::ref:`u32<amdgpu_synid_gfx940_type_deviation>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_mac_f16 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_mac_f16_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_madak_f16 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`, :ref:`simm32<amdgpu_synid_gfx940_simm32_be0c1c>`
+ v_madmk_f16 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`simm32<amdgpu_synid_gfx940_simm32_be0c1c>`, :ref:`vsrc2<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_max_f16 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_max_f16_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_max_f16_sdwa :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_max_f32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_max_f32_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_max_f32_sdwa :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_max_i16 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_4de5c6>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_max_i16_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_max_i16_sdwa :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_max_i32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_max_i32_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_max_i32_sdwa :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_max_u16 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_4de5c6>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_max_u16_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_max_u16_sdwa :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_max_u32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_max_u32_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_max_u32_sdwa :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_min_f16 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_min_f16_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_min_f16_sdwa :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_min_f32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_min_f32_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_min_f32_sdwa :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_min_i16 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_4de5c6>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_min_i16_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_min_i16_sdwa :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_min_i32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_min_i32_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_min_i32_sdwa :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_min_u16 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_4de5c6>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_min_u16_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_min_u16_sdwa :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_min_u32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_min_u32_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_min_u32_sdwa :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_mul_f16 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_mul_f16_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_mul_f16_sdwa :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_mul_f32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_mul_f32_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_mul_f32_sdwa :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_mul_hi_i32_i24 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_mul_hi_i32_i24_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_mul_hi_i32_i24_sdwa :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_mul_hi_u32_u24 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_mul_hi_u32_u24_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_mul_hi_u32_u24_sdwa :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_mul_i32_i24 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_mul_i32_i24_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_mul_i32_i24_sdwa :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_mul_lo_u16 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_4de5c6>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_mul_lo_u16_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_mul_lo_u16_sdwa :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_mul_u32_u24 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_mul_u32_u24_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_mul_u32_u24_sdwa :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_or_b32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_or_b32_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_or_b32_sdwa :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_pk_fmac_f16 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_sub_co_u32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_sub_co_u32_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_sub_co_u32_sdwa :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_sub_f16 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_sub_f16_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_sub_f16_sdwa :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_sub_f32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_sub_f32_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_sub_f32_sdwa :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_sub_u16 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_4de5c6>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_sub_u16_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_sub_u16_sdwa :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_sub_u32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_sub_u32_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_sub_u32_sdwa :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_subb_co_u32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`, :ref:`vcc<amdgpu_synid_gfx940_vcc>`
+ v_subb_co_u32_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`, :ref:`vcc<amdgpu_synid_gfx940_vcc>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_subb_co_u32_sdwa :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>`, :ref:`vcc<amdgpu_synid_gfx940_vcc>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_subbrev_co_u32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`, :ref:`vcc<amdgpu_synid_gfx940_vcc>`
+ v_subbrev_co_u32_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`, :ref:`vcc<amdgpu_synid_gfx940_vcc>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_subbrev_co_u32_sdwa :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>`, :ref:`vcc<amdgpu_synid_gfx940_vcc>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_subrev_co_u32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_subrev_co_u32_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_subrev_co_u32_sdwa :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_subrev_f16 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_subrev_f16_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_subrev_f16_sdwa :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_subrev_f32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_subrev_f32_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_subrev_f32_sdwa :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_subrev_u16 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_4de5c6>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_subrev_u16_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_subrev_u16_sdwa :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_subrev_u32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_subrev_u32_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_subrev_u32_sdwa :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_xnor_b32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_xnor_b32_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_xnor_b32_sdwa :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_xor_b32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_xor_b32_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_xor_b32_sdwa :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+
+VOP3
+----
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST0** **DST1** **SRC0** **SRC1** **SRC2** **MODIFIERS**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ v_add3_u32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src2<amdgpu_synid_gfx940_src_d578c4>`
+ v_add_co_u32_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_add_f16_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_add_f32_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_add_f64 :ref:`vdst<amdgpu_synid_gfx940_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx940_src_f73668>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_f73668>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_add_i16 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_add_i32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_add_lshl_u32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src2<amdgpu_synid_gfx940_src_d578c4>`
+ v_add_u16_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_add_u32_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_addc_co_u32_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`, :ref:`ssrc2<amdgpu_synid_gfx940_ssrc_e9f591>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_alignbit_b32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src2<amdgpu_synid_gfx940_src_d95796>`::ref:`b16<amdgpu_synid_gfx940_type_deviation>`
+ v_alignbyte_b32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src2<amdgpu_synid_gfx940_src_d95796>`::ref:`b16<amdgpu_synid_gfx940_type_deviation>`
+ v_and_b32_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`
+ v_and_or_b32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src2<amdgpu_synid_gfx940_src_d578c4>`
+ v_ashrrev_i16_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`::ref:`u16<amdgpu_synid_gfx940_type_deviation>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>`
+ v_ashrrev_i32_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`u32<amdgpu_synid_gfx940_type_deviation>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`
+ v_ashrrev_i64 :ref:`vdst<amdgpu_synid_gfx940_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`u32<amdgpu_synid_gfx940_type_deviation>`, :ref:`src1<amdgpu_synid_gfx940_src_f73668>`
+ v_bcnt_u32_b32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`
+ v_bfe_i32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`u32<amdgpu_synid_gfx940_type_deviation>`, :ref:`src2<amdgpu_synid_gfx940_src_d578c4>`::ref:`u32<amdgpu_synid_gfx940_type_deviation>`
+ v_bfe_u32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src2<amdgpu_synid_gfx940_src_d578c4>`
+ v_bfi_b32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src2<amdgpu_synid_gfx940_src_d578c4>`
+ v_bfm_b32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`
+ v_bfrev_b32_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>`
+ v_ceil_f16_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_ceil_f32_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_ceil_f64_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_bdb32f>`, :ref:`src<amdgpu_synid_gfx940_src_f73668>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_clrexcp_e64
+ v_cmp_class_f16_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`b32<amdgpu_synid_gfx940_type_deviation>`
+ v_cmp_class_f32_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`b32<amdgpu_synid_gfx940_type_deviation>`
+ v_cmp_class_f64_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_f73668>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`b32<amdgpu_synid_gfx940_type_deviation>`
+ v_cmp_eq_f16_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_eq_f32_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_eq_f64_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_f73668>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_f73668>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_eq_i16_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>`
+ v_cmp_eq_i32_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`
+ v_cmp_eq_i64_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_f73668>`, :ref:`src1<amdgpu_synid_gfx940_src_f73668>`
+ v_cmp_eq_u16_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>`
+ v_cmp_eq_u32_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`
+ v_cmp_eq_u64_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_f73668>`, :ref:`src1<amdgpu_synid_gfx940_src_f73668>`
+ v_cmp_f_f16_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_f_f32_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_f_f64_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_f73668>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_f73668>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_f_i16_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>`
+ v_cmp_f_i32_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`
+ v_cmp_f_i64_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_f73668>`, :ref:`src1<amdgpu_synid_gfx940_src_f73668>`
+ v_cmp_f_u16_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>`
+ v_cmp_f_u32_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`
+ v_cmp_f_u64_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_f73668>`, :ref:`src1<amdgpu_synid_gfx940_src_f73668>`
+ v_cmp_ge_f16_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_ge_f32_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_ge_f64_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_f73668>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_f73668>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_ge_i16_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>`
+ v_cmp_ge_i32_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`
+ v_cmp_ge_i64_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_f73668>`, :ref:`src1<amdgpu_synid_gfx940_src_f73668>`
+ v_cmp_ge_u16_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>`
+ v_cmp_ge_u32_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`
+ v_cmp_ge_u64_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_f73668>`, :ref:`src1<amdgpu_synid_gfx940_src_f73668>`
+ v_cmp_gt_f16_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_gt_f32_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_gt_f64_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_f73668>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_f73668>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_gt_i16_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>`
+ v_cmp_gt_i32_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`
+ v_cmp_gt_i64_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_f73668>`, :ref:`src1<amdgpu_synid_gfx940_src_f73668>`
+ v_cmp_gt_u16_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>`
+ v_cmp_gt_u32_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`
+ v_cmp_gt_u64_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_f73668>`, :ref:`src1<amdgpu_synid_gfx940_src_f73668>`
+ v_cmp_le_f16_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_le_f32_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_le_f64_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_f73668>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_f73668>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_le_i16_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>`
+ v_cmp_le_i32_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`
+ v_cmp_le_i64_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_f73668>`, :ref:`src1<amdgpu_synid_gfx940_src_f73668>`
+ v_cmp_le_u16_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>`
+ v_cmp_le_u32_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`
+ v_cmp_le_u64_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_f73668>`, :ref:`src1<amdgpu_synid_gfx940_src_f73668>`
+ v_cmp_lg_f16_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_lg_f32_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_lg_f64_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_f73668>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_f73668>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_lt_f16_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_lt_f32_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_lt_f64_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_f73668>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_f73668>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_lt_i16_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>`
+ v_cmp_lt_i32_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`
+ v_cmp_lt_i64_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_f73668>`, :ref:`src1<amdgpu_synid_gfx940_src_f73668>`
+ v_cmp_lt_u16_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>`
+ v_cmp_lt_u32_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`
+ v_cmp_lt_u64_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_f73668>`, :ref:`src1<amdgpu_synid_gfx940_src_f73668>`
+ v_cmp_ne_i16_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>`
+ v_cmp_ne_i32_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`
+ v_cmp_ne_i64_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_f73668>`, :ref:`src1<amdgpu_synid_gfx940_src_f73668>`
+ v_cmp_ne_u16_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>`
+ v_cmp_ne_u32_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`
+ v_cmp_ne_u64_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_f73668>`, :ref:`src1<amdgpu_synid_gfx940_src_f73668>`
+ v_cmp_neq_f16_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_neq_f32_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_neq_f64_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_f73668>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_f73668>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_nge_f16_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_nge_f32_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_nge_f64_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_f73668>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_f73668>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_ngt_f16_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_ngt_f32_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_ngt_f64_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_f73668>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_f73668>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_nle_f16_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_nle_f32_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_nle_f64_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_f73668>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_f73668>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_nlg_f16_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_nlg_f32_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_nlg_f64_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_f73668>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_f73668>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_nlt_f16_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_nlt_f32_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_nlt_f64_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_f73668>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_f73668>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_o_f16_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_o_f32_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_o_f64_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_f73668>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_f73668>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_t_i16_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>`
+ v_cmp_t_i32_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`
+ v_cmp_t_i64_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_f73668>`, :ref:`src1<amdgpu_synid_gfx940_src_f73668>`
+ v_cmp_t_u16_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>`
+ v_cmp_t_u32_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`
+ v_cmp_t_u64_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_f73668>`, :ref:`src1<amdgpu_synid_gfx940_src_f73668>`
+ v_cmp_tru_f16_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_tru_f32_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_tru_f64_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_f73668>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_f73668>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_u_f16_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_u_f32_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_u_f64_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_f73668>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_f73668>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_class_f16_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`b32<amdgpu_synid_gfx940_type_deviation>`
+ v_cmpx_class_f32_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`b32<amdgpu_synid_gfx940_type_deviation>`
+ v_cmpx_class_f64_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_f73668>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`b32<amdgpu_synid_gfx940_type_deviation>`
+ v_cmpx_eq_f16_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_eq_f32_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_eq_f64_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_f73668>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_f73668>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_eq_i16_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>`
+ v_cmpx_eq_i32_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`
+ v_cmpx_eq_i64_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_f73668>`, :ref:`src1<amdgpu_synid_gfx940_src_f73668>`
+ v_cmpx_eq_u16_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>`
+ v_cmpx_eq_u32_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`
+ v_cmpx_eq_u64_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_f73668>`, :ref:`src1<amdgpu_synid_gfx940_src_f73668>`
+ v_cmpx_f_f16_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_f_f32_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_f_f64_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_f73668>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_f73668>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_f_i16_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>`
+ v_cmpx_f_i32_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`
+ v_cmpx_f_i64_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_f73668>`, :ref:`src1<amdgpu_synid_gfx940_src_f73668>`
+ v_cmpx_f_u16_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>`
+ v_cmpx_f_u32_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`
+ v_cmpx_f_u64_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_f73668>`, :ref:`src1<amdgpu_synid_gfx940_src_f73668>`
+ v_cmpx_ge_f16_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_ge_f32_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_ge_f64_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_f73668>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_f73668>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_ge_i16_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>`
+ v_cmpx_ge_i32_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`
+ v_cmpx_ge_i64_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_f73668>`, :ref:`src1<amdgpu_synid_gfx940_src_f73668>`
+ v_cmpx_ge_u16_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>`
+ v_cmpx_ge_u32_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`
+ v_cmpx_ge_u64_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_f73668>`, :ref:`src1<amdgpu_synid_gfx940_src_f73668>`
+ v_cmpx_gt_f16_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_gt_f32_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_gt_f64_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_f73668>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_f73668>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_gt_i16_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>`
+ v_cmpx_gt_i32_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`
+ v_cmpx_gt_i64_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_f73668>`, :ref:`src1<amdgpu_synid_gfx940_src_f73668>`
+ v_cmpx_gt_u16_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>`
+ v_cmpx_gt_u32_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`
+ v_cmpx_gt_u64_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_f73668>`, :ref:`src1<amdgpu_synid_gfx940_src_f73668>`
+ v_cmpx_le_f16_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_le_f32_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_le_f64_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_f73668>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_f73668>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_le_i16_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>`
+ v_cmpx_le_i32_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`
+ v_cmpx_le_i64_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_f73668>`, :ref:`src1<amdgpu_synid_gfx940_src_f73668>`
+ v_cmpx_le_u16_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>`
+ v_cmpx_le_u32_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`
+ v_cmpx_le_u64_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_f73668>`, :ref:`src1<amdgpu_synid_gfx940_src_f73668>`
+ v_cmpx_lg_f16_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_lg_f32_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_lg_f64_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_f73668>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_f73668>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_lt_f16_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_lt_f32_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_lt_f64_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_f73668>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_f73668>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_lt_i16_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>`
+ v_cmpx_lt_i32_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`
+ v_cmpx_lt_i64_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_f73668>`, :ref:`src1<amdgpu_synid_gfx940_src_f73668>`
+ v_cmpx_lt_u16_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>`
+ v_cmpx_lt_u32_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`
+ v_cmpx_lt_u64_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_f73668>`, :ref:`src1<amdgpu_synid_gfx940_src_f73668>`
+ v_cmpx_ne_i16_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>`
+ v_cmpx_ne_i32_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`
+ v_cmpx_ne_i64_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_f73668>`, :ref:`src1<amdgpu_synid_gfx940_src_f73668>`
+ v_cmpx_ne_u16_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>`
+ v_cmpx_ne_u32_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`
+ v_cmpx_ne_u64_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_f73668>`, :ref:`src1<amdgpu_synid_gfx940_src_f73668>`
+ v_cmpx_neq_f16_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_neq_f32_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_neq_f64_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_f73668>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_f73668>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_nge_f16_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_nge_f32_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_nge_f64_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_f73668>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_f73668>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_ngt_f16_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_ngt_f32_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_ngt_f64_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_f73668>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_f73668>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_nle_f16_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_nle_f32_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_nle_f64_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_f73668>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_f73668>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_nlg_f16_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_nlg_f32_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_nlg_f64_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_f73668>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_f73668>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_nlt_f16_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_nlt_f32_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_nlt_f64_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_f73668>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_f73668>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_o_f16_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_o_f32_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_o_f64_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_f73668>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_f73668>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_t_i16_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>`
+ v_cmpx_t_i32_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`
+ v_cmpx_t_i64_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_f73668>`, :ref:`src1<amdgpu_synid_gfx940_src_f73668>`
+ v_cmpx_t_u16_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>`
+ v_cmpx_t_u32_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`
+ v_cmpx_t_u64_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_f73668>`, :ref:`src1<amdgpu_synid_gfx940_src_f73668>`
+ v_cmpx_tru_f16_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_tru_f32_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_tru_f64_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_f73668>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_f73668>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_u_f16_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_u_f32_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_u_f64_e64 :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_f73668>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_f73668>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cndmask_b32_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`ssrc2<amdgpu_synid_gfx940_ssrc_e9f591>`
+ v_cos_f16_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cos_f32_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cubeid_f32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src2<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cubema_f32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src2<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cubesc_f32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src2<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cubetc_f32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src2<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f16_f32_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f16_i16_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d95796>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f16_u16_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d95796>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f32_f16_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f32_f64_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_f73668>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f32_i32_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f32_u32_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f32_ubyte0_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f32_ubyte1_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f32_ubyte2_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f32_ubyte3_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f64_f32_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_bdb32f>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f64_i32_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_bdb32f>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f64_u32_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_bdb32f>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_flr_i32_f32_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`
+ v_cvt_i16_f16_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cvt_i32_f32_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cvt_i32_f64_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_f73668>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cvt_norm_i16_f16_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cvt_norm_u16_f16_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cvt_off_f32_i4_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_pk_i16_i32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`i32<amdgpu_synid_gfx940_type_deviation>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`i32<amdgpu_synid_gfx940_type_deviation>`
+ v_cvt_pk_u16_u32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`u32<amdgpu_synid_gfx940_type_deviation>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`u32<amdgpu_synid_gfx940_type_deviation>`
+ v_cvt_pk_u8_f32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`::ref:`b32<amdgpu_synid_gfx940_type_deviation>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`::ref:`f32<amdgpu_synid_gfx940_type_deviation>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`u32<amdgpu_synid_gfx940_type_deviation>`, :ref:`src2<amdgpu_synid_gfx940_src_d578c4>`::ref:`u32<amdgpu_synid_gfx940_type_deviation>`
+ v_cvt_pkaccum_u8_f32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`::ref:`b32<amdgpu_synid_gfx940_type_deviation>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`::ref:`f32<amdgpu_synid_gfx940_type_deviation>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`u32<amdgpu_synid_gfx940_type_deviation>`
+ v_cvt_pknorm_i16_f16 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`::ref:`f16<amdgpu_synid_gfx940_type_deviation>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`::ref:`f16<amdgpu_synid_gfx940_type_deviation>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+ v_cvt_pknorm_i16_f32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`::ref:`f32<amdgpu_synid_gfx940_type_deviation>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`::ref:`f32<amdgpu_synid_gfx940_type_deviation>`
+ v_cvt_pknorm_u16_f16 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`::ref:`f16<amdgpu_synid_gfx940_type_deviation>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`::ref:`f16<amdgpu_synid_gfx940_type_deviation>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+ v_cvt_pknorm_u16_f32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`::ref:`f32<amdgpu_synid_gfx940_type_deviation>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`::ref:`f32<amdgpu_synid_gfx940_type_deviation>`
+ v_cvt_pkrtz_f16_f32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`::ref:`f32<amdgpu_synid_gfx940_type_deviation>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`::ref:`f32<amdgpu_synid_gfx940_type_deviation>`
+ v_cvt_rpi_i32_f32_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`
+ v_cvt_u16_f16_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cvt_u32_f32_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cvt_u32_f64_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_f73668>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_div_fixup_f16 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src2<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_div_fixup_f32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src2<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_div_fixup_f64 :ref:`vdst<amdgpu_synid_gfx940_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx940_src_f73668>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_f73668>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src2<amdgpu_synid_gfx940_src_f73668>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_div_fixup_legacy_f16 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src2<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_div_fmas_f32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src2<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_div_fmas_f64 :ref:`vdst<amdgpu_synid_gfx940_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx940_src_f73668>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_f73668>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src2<amdgpu_synid_gfx940_src_f73668>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_div_scale_f32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src2<amdgpu_synid_gfx940_src_d578c4>`
+ v_div_scale_f64 :ref:`vdst<amdgpu_synid_gfx940_vdst_bdb32f>`, :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_f73668>`, :ref:`src1<amdgpu_synid_gfx940_src_f73668>`, :ref:`src2<amdgpu_synid_gfx940_src_f73668>`
+ v_exp_f16_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_exp_f32_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_exp_legacy_f32_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_ffbh_i32_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>`
+ v_ffbh_u32_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>`
+ v_ffbl_b32_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>`
+ v_floor_f16_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_floor_f32_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_floor_f64_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_bdb32f>`, :ref:`src<amdgpu_synid_gfx940_src_f73668>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_fma_f16 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src2<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_fma_f32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src2<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_fma_f64 :ref:`vdst<amdgpu_synid_gfx940_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx940_src_f73668>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_f73668>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src2<amdgpu_synid_gfx940_src_f73668>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_fma_legacy_f16 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src2<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_fmac_f32_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_fmac_f64_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx940_src_f73668>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_f73668>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_fract_f16_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_fract_f32_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_fract_f64_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_bdb32f>`, :ref:`src<amdgpu_synid_gfx940_src_f73668>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_frexp_exp_i16_f16_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`
+ v_frexp_exp_i32_f32_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`
+ v_frexp_exp_i32_f64_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_f73668>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`
+ v_frexp_mant_f16_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_frexp_mant_f32_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_frexp_mant_f64_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_bdb32f>`, :ref:`src<amdgpu_synid_gfx940_src_f73668>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_ldexp_f16_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`i16<amdgpu_synid_gfx940_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_ldexp_f32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`i32<amdgpu_synid_gfx940_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_ldexp_f64 :ref:`vdst<amdgpu_synid_gfx940_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx940_src_f73668>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`i32<amdgpu_synid_gfx940_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_lerp_u8 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`::ref:`u32<amdgpu_synid_gfx940_type_deviation>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`b32<amdgpu_synid_gfx940_type_deviation>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`b32<amdgpu_synid_gfx940_type_deviation>`, :ref:`src2<amdgpu_synid_gfx940_src_d578c4>`::ref:`b32<amdgpu_synid_gfx940_type_deviation>`
+ v_log_f16_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_log_f32_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_log_legacy_f32_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_lshl_add_u32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src2<amdgpu_synid_gfx940_src_d578c4>`
+ v_lshl_add_u64 :ref:`vdst<amdgpu_synid_gfx940_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx940_src_f73668>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`u32<amdgpu_synid_gfx940_type_deviation>`, :ref:`src2<amdgpu_synid_gfx940_src_f73668>`
+ v_lshl_or_b32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`u32<amdgpu_synid_gfx940_type_deviation>`, :ref:`src2<amdgpu_synid_gfx940_src_d578c4>`
+ v_lshlrev_b16_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`::ref:`u16<amdgpu_synid_gfx940_type_deviation>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>`
+ v_lshlrev_b32_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`u32<amdgpu_synid_gfx940_type_deviation>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`
+ v_lshlrev_b64 :ref:`vdst<amdgpu_synid_gfx940_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`u32<amdgpu_synid_gfx940_type_deviation>`, :ref:`src1<amdgpu_synid_gfx940_src_f73668>`
+ v_lshrrev_b16_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`::ref:`u16<amdgpu_synid_gfx940_type_deviation>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>`
+ v_lshrrev_b32_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`u32<amdgpu_synid_gfx940_type_deviation>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`
+ v_lshrrev_b64 :ref:`vdst<amdgpu_synid_gfx940_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`u32<amdgpu_synid_gfx940_type_deviation>`, :ref:`src1<amdgpu_synid_gfx940_src_f73668>`
+ v_mac_f16_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_mad_f16 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src2<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mad_i16 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>`, :ref:`src2<amdgpu_synid_gfx940_src_d95796>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mad_i32_i16 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>`, :ref:`src2<amdgpu_synid_gfx940_src_d578c4>`::ref:`i32<amdgpu_synid_gfx940_type_deviation>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mad_i32_i24 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src2<amdgpu_synid_gfx940_src_d578c4>`::ref:`i32<amdgpu_synid_gfx940_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mad_i64_i32 :ref:`vdst<amdgpu_synid_gfx940_vdst_bdb32f>`, :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src2<amdgpu_synid_gfx940_src_f73668>`::ref:`i64<amdgpu_synid_gfx940_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mad_legacy_f16 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src2<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_mad_legacy_i16 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>`, :ref:`src2<amdgpu_synid_gfx940_src_d95796>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mad_legacy_u16 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>`, :ref:`src2<amdgpu_synid_gfx940_src_d95796>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mad_u16 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>`, :ref:`src2<amdgpu_synid_gfx940_src_d95796>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mad_u32_u16 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>`, :ref:`src2<amdgpu_synid_gfx940_src_d578c4>`::ref:`u32<amdgpu_synid_gfx940_type_deviation>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mad_u32_u24 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src2<amdgpu_synid_gfx940_src_d578c4>`::ref:`u32<amdgpu_synid_gfx940_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mad_u64_u32 :ref:`vdst<amdgpu_synid_gfx940_vdst_bdb32f>`, :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src2<amdgpu_synid_gfx940_src_f73668>`::ref:`u64<amdgpu_synid_gfx940_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_max3_f16 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src2<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_max3_f32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src2<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_max3_i16 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>`, :ref:`src2<amdgpu_synid_gfx940_src_d95796>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+ v_max3_i32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src2<amdgpu_synid_gfx940_src_d578c4>`
+ v_max3_u16 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>`, :ref:`src2<amdgpu_synid_gfx940_src_d95796>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+ v_max3_u32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src2<amdgpu_synid_gfx940_src_d578c4>`
+ v_max_f16_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_max_f32_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_max_f64 :ref:`vdst<amdgpu_synid_gfx940_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx940_src_f73668>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_f73668>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_max_i16_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>`
+ v_max_i32_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`
+ v_max_u16_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>`
+ v_max_u32_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`
+ v_mbcnt_hi_u32_b32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`
+ v_mbcnt_lo_u32_b32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`
+ v_med3_f16 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src2<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_med3_f32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src2<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_med3_i16 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>`, :ref:`src2<amdgpu_synid_gfx940_src_d95796>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+ v_med3_i32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src2<amdgpu_synid_gfx940_src_d578c4>`
+ v_med3_u16 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>`, :ref:`src2<amdgpu_synid_gfx940_src_d95796>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+ v_med3_u32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src2<amdgpu_synid_gfx940_src_d578c4>`
+ v_min3_f16 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src2<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_min3_f32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src2<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_min3_i16 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>`, :ref:`src2<amdgpu_synid_gfx940_src_d95796>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+ v_min3_i32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src2<amdgpu_synid_gfx940_src_d578c4>`
+ v_min3_u16 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>`, :ref:`src2<amdgpu_synid_gfx940_src_d95796>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+ v_min3_u32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src2<amdgpu_synid_gfx940_src_d578c4>`
+ v_min_f16_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_min_f32_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_min_f64 :ref:`vdst<amdgpu_synid_gfx940_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx940_src_f73668>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_f73668>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_min_i16_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>`
+ v_min_i32_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`
+ v_min_u16_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>`
+ v_min_u32_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`
+ v_mov_b32_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>`
+ v_mov_b64_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_bdb32f>`, :ref:`src<amdgpu_synid_gfx940_src_f73668>`
+ v_mqsad_pk_u16_u8 :ref:`vdst<amdgpu_synid_gfx940_vdst_bdb32f>`::ref:`u16x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`src0<amdgpu_synid_gfx940_src_f73668>`::ref:`u8x8<amdgpu_synid_gfx940_type_deviation>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`u8x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`src2<amdgpu_synid_gfx940_src_f73668>`::ref:`u16x4<amdgpu_synid_gfx940_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mqsad_u32_u8 :ref:`vdst<amdgpu_synid_gfx940_vdst_69a144>`::ref:`u32x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`src0<amdgpu_synid_gfx940_src_f73668>`::ref:`u8x8<amdgpu_synid_gfx940_type_deviation>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`u8x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc2<amdgpu_synid_gfx940_vsrc_e016a1>`::ref:`u32x4<amdgpu_synid_gfx940_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_msad_u8 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`::ref:`u32<amdgpu_synid_gfx940_type_deviation>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`u8x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`u8x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`src2<amdgpu_synid_gfx940_src_d578c4>`::ref:`u32<amdgpu_synid_gfx940_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mul_f16_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_mul_f32_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_mul_f64 :ref:`vdst<amdgpu_synid_gfx940_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx940_src_f73668>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_f73668>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_mul_hi_i32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`
+ v_mul_hi_i32_i24_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`
+ v_mul_hi_u32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`
+ v_mul_hi_u32_u24_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`
+ v_mul_i32_i24_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mul_legacy_f32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_mul_lo_u16_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>`
+ v_mul_lo_u32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`
+ v_mul_u32_u24_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_nop_e64
+ v_not_b32_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>`
+ v_or3_b32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src2<amdgpu_synid_gfx940_src_d578c4>`
+ v_or_b32_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`
+ v_pack_b32_f16 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+ v_perm_b32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src2<amdgpu_synid_gfx940_src_d578c4>`
+ v_qsad_pk_u16_u8 :ref:`vdst<amdgpu_synid_gfx940_vdst_bdb32f>`::ref:`u16x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`src0<amdgpu_synid_gfx940_src_f73668>`::ref:`u8x8<amdgpu_synid_gfx940_type_deviation>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`u8x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`src2<amdgpu_synid_gfx940_src_f73668>`::ref:`u16x4<amdgpu_synid_gfx940_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_rcp_f16_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_rcp_f32_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_rcp_f64_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_bdb32f>`, :ref:`src<amdgpu_synid_gfx940_src_f73668>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_rcp_iflag_f32_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_readlane_b32 :ref:`sdst<amdgpu_synid_gfx940_sdst_59204c>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_6802ce>`, :ref:`ssrc1<amdgpu_synid_gfx940_ssrc_57838b>`
+ v_rndne_f16_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_rndne_f32_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_rndne_f64_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_bdb32f>`, :ref:`src<amdgpu_synid_gfx940_src_f73668>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_rsq_f16_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_rsq_f32_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_rsq_f64_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_bdb32f>`, :ref:`src<amdgpu_synid_gfx940_src_f73668>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_sad_hi_u8 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`::ref:`u32<amdgpu_synid_gfx940_type_deviation>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`u8x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`u8x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`src2<amdgpu_synid_gfx940_src_d578c4>`::ref:`u32<amdgpu_synid_gfx940_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_sad_u16 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`::ref:`u32<amdgpu_synid_gfx940_type_deviation>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`u16x2<amdgpu_synid_gfx940_type_deviation>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`u16x2<amdgpu_synid_gfx940_type_deviation>`, :ref:`src2<amdgpu_synid_gfx940_src_d578c4>`::ref:`u32<amdgpu_synid_gfx940_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_sad_u32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src2<amdgpu_synid_gfx940_src_d578c4>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_sad_u8 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`::ref:`u32<amdgpu_synid_gfx940_type_deviation>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`u8x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`u8x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`src2<amdgpu_synid_gfx940_src_d578c4>`::ref:`u32<amdgpu_synid_gfx940_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_sat_pk_u8_i16_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`::ref:`u8x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>`
+ v_screen_partition_4se_b32_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>`
+ v_sin_f16_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_sin_f32_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_sqrt_f16_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_sqrt_f32_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_sqrt_f64_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_bdb32f>`, :ref:`src<amdgpu_synid_gfx940_src_f73668>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_sub_co_u32_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_sub_f16_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_sub_f32_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_sub_i16 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_sub_i32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_sub_u16_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_sub_u32_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_subb_co_u32_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`, :ref:`ssrc2<amdgpu_synid_gfx940_ssrc_e9f591>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_subbrev_co_u32_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`, :ref:`ssrc2<amdgpu_synid_gfx940_ssrc_e9f591>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_subrev_co_u32_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_subrev_f16_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_subrev_f32_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_subrev_u16_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_subrev_u32_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_trig_preop_f64 :ref:`vdst<amdgpu_synid_gfx940_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx940_src_f73668>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`u32<amdgpu_synid_gfx940_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_trunc_f16_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_trunc_f32_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_trunc_f64_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_bdb32f>`, :ref:`src<amdgpu_synid_gfx940_src_f73668>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_writelane_b32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`ssrc0<amdgpu_synid_gfx940_ssrc_4db4a9>`, :ref:`ssrc1<amdgpu_synid_gfx940_ssrc_57838b>`
+ v_xad_u32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src2<amdgpu_synid_gfx940_src_d578c4>`
+ v_xnor_b32_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`
+ v_xor_b32_e64 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`
+
+VOP3P
+-----
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ v_accvgpr_read_b32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx940_vsrc_1027ca>`
+ v_accvgpr_write_b32 :ref:`vdst<amdgpu_synid_gfx940_vdst_78dd0a>`, :ref:`src<amdgpu_synid_gfx940_src_d578c4>`
+ v_dot2_f32_f16 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`f16x2<amdgpu_synid_gfx940_type_deviation>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`f16x2<amdgpu_synid_gfx940_type_deviation>`, :ref:`src2<amdgpu_synid_gfx940_src_d578c4>`::ref:`f32<amdgpu_synid_gfx940_type_deviation>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_dot2_i32_i16 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`::ref:`i16x2<amdgpu_synid_gfx940_type_deviation>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>`::ref:`i16x2<amdgpu_synid_gfx940_type_deviation>`, :ref:`src2<amdgpu_synid_gfx940_src_d578c4>`::ref:`i32<amdgpu_synid_gfx940_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_dot2_u32_u16 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`::ref:`u16x2<amdgpu_synid_gfx940_type_deviation>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>`::ref:`u16x2<amdgpu_synid_gfx940_type_deviation>`, :ref:`src2<amdgpu_synid_gfx940_src_d578c4>`::ref:`u32<amdgpu_synid_gfx940_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_dot4_i32_i8 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`i8x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`i8x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`src2<amdgpu_synid_gfx940_src_d578c4>`::ref:`i32<amdgpu_synid_gfx940_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_dot4_u32_u8 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`u8x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`u8x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`src2<amdgpu_synid_gfx940_src_d578c4>`::ref:`u32<amdgpu_synid_gfx940_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_dot8_i32_i4 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`i4x8<amdgpu_synid_gfx940_type_deviation>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`i4x8<amdgpu_synid_gfx940_type_deviation>`, :ref:`src2<amdgpu_synid_gfx940_src_d578c4>`::ref:`i32<amdgpu_synid_gfx940_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_dot8_u32_u4 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`u4x8<amdgpu_synid_gfx940_type_deviation>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`u4x8<amdgpu_synid_gfx940_type_deviation>`, :ref:`src2<amdgpu_synid_gfx940_src_d578c4>`::ref:`u32<amdgpu_synid_gfx940_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_fma_mix_f32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`::ref:`fx<amdgpu_synid_gfx940_fx_operand>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`::ref:`fx<amdgpu_synid_gfx940_fx_operand>`, :ref:`src2<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`::ref:`fx<amdgpu_synid_gfx940_fx_operand>` :ref:`m_op_sel<amdgpu_synid_mad_mix_op_sel>` :ref:`m_op_sel_hi<amdgpu_synid_mad_mix_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_fma_mixhi_f16 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`::ref:`fx<amdgpu_synid_gfx940_fx_operand>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`::ref:`fx<amdgpu_synid_gfx940_fx_operand>`, :ref:`src2<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`::ref:`fx<amdgpu_synid_gfx940_fx_operand>` :ref:`m_op_sel<amdgpu_synid_mad_mix_op_sel>` :ref:`m_op_sel_hi<amdgpu_synid_mad_mix_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_fma_mixlo_f16 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`::ref:`fx<amdgpu_synid_gfx940_fx_operand>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`::ref:`fx<amdgpu_synid_gfx940_fx_operand>`, :ref:`src2<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`::ref:`fx<amdgpu_synid_gfx940_fx_operand>` :ref:`m_op_sel<amdgpu_synid_mad_mix_op_sel>` :ref:`m_op_sel_hi<amdgpu_synid_mad_mix_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mfma_f32_16x16x16_bf16 :ref:`vdst<amdgpu_synid_gfx940_vdst_180bef>`::ref:`f32x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_9ad749>`::ref:`bf16x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_9ad749>`::ref:`bf16x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`src2<amdgpu_synid_gfx940_src_af08be>`::ref:`f32x4<amdgpu_synid_gfx940_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
+ v_mfma_f32_16x16x16_f16 :ref:`vdst<amdgpu_synid_gfx940_vdst_180bef>`::ref:`f32x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_9ad749>`::ref:`f16x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_9ad749>`::ref:`f16x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`src2<amdgpu_synid_gfx940_src_af08be>`::ref:`f32x4<amdgpu_synid_gfx940_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
+ v_mfma_f32_16x16x16bf16 :ref:`vdst<amdgpu_synid_gfx940_vdst_180bef>`::ref:`f32x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_9ad749>`::ref:`bf16x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_9ad749>`::ref:`bf16x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`src2<amdgpu_synid_gfx940_src_af08be>`::ref:`f32x4<amdgpu_synid_gfx940_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
+ v_mfma_f32_16x16x16bf16_1k :ref:`vdst<amdgpu_synid_gfx940_vdst_180bef>`::ref:`f32x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_9ad749>`::ref:`bf16x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_9ad749>`::ref:`bf16x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`src2<amdgpu_synid_gfx940_src_af08be>`::ref:`f32x4<amdgpu_synid_gfx940_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
+ v_mfma_f32_16x16x16f16 :ref:`vdst<amdgpu_synid_gfx940_vdst_180bef>`::ref:`f32x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_9ad749>`::ref:`f16x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_9ad749>`::ref:`f16x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`src2<amdgpu_synid_gfx940_src_af08be>`::ref:`f32x4<amdgpu_synid_gfx940_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
+ v_mfma_f32_16x16x1_4b_f32 :ref:`vdst<amdgpu_synid_gfx940_vdst_d6f4bd>`::ref:`f32x16<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_be4895>`::ref:`f32<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_be4895>`::ref:`f32<amdgpu_synid_gfx940_type_deviation>`, :ref:`src2<amdgpu_synid_gfx940_src_a578ba>`::ref:`f32x16<amdgpu_synid_gfx940_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
+ v_mfma_f32_16x16x1f32 :ref:`vdst<amdgpu_synid_gfx940_vdst_d6f4bd>`::ref:`f32x16<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_be4895>`::ref:`f32<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_be4895>`::ref:`f32<amdgpu_synid_gfx940_type_deviation>`, :ref:`src2<amdgpu_synid_gfx940_src_a578ba>`::ref:`f32x16<amdgpu_synid_gfx940_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
+ v_mfma_f32_16x16x4_4b_bf16 :ref:`vdst<amdgpu_synid_gfx940_vdst_d6f4bd>`::ref:`f32x16<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_9ad749>`::ref:`bf16x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_9ad749>`::ref:`bf16x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`src2<amdgpu_synid_gfx940_src_a578ba>`::ref:`f32x16<amdgpu_synid_gfx940_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
+ v_mfma_f32_16x16x4_4b_f16 :ref:`vdst<amdgpu_synid_gfx940_vdst_d6f4bd>`::ref:`f32x16<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_9ad749>`::ref:`f16x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_9ad749>`::ref:`f16x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`src2<amdgpu_synid_gfx940_src_a578ba>`::ref:`f32x16<amdgpu_synid_gfx940_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
+ v_mfma_f32_16x16x4_f32 :ref:`vdst<amdgpu_synid_gfx940_vdst_180bef>`::ref:`f32x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_be4895>`::ref:`f32<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_be4895>`::ref:`f32<amdgpu_synid_gfx940_type_deviation>`, :ref:`src2<amdgpu_synid_gfx940_src_af08be>`::ref:`f32x4<amdgpu_synid_gfx940_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
+ v_mfma_f32_16x16x4bf16 :ref:`vdst<amdgpu_synid_gfx940_vdst_d6f4bd>`::ref:`f32x16<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_9ad749>`::ref:`bf16x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_9ad749>`::ref:`bf16x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`src2<amdgpu_synid_gfx940_src_a578ba>`::ref:`f32x16<amdgpu_synid_gfx940_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
+ v_mfma_f32_16x16x4bf16_1k :ref:`vdst<amdgpu_synid_gfx940_vdst_d6f4bd>`::ref:`f32x16<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_9ad749>`::ref:`bf16x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_9ad749>`::ref:`bf16x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`src2<amdgpu_synid_gfx940_src_a578ba>`::ref:`f32x16<amdgpu_synid_gfx940_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
+ v_mfma_f32_16x16x4f16 :ref:`vdst<amdgpu_synid_gfx940_vdst_d6f4bd>`::ref:`f32x16<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_9ad749>`::ref:`f16x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_9ad749>`::ref:`f16x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`src2<amdgpu_synid_gfx940_src_a578ba>`::ref:`f32x16<amdgpu_synid_gfx940_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
+ v_mfma_f32_16x16x4f32 :ref:`vdst<amdgpu_synid_gfx940_vdst_180bef>`::ref:`f32x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_be4895>`::ref:`f32<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_be4895>`::ref:`f32<amdgpu_synid_gfx940_type_deviation>`, :ref:`src2<amdgpu_synid_gfx940_src_af08be>`::ref:`f32x4<amdgpu_synid_gfx940_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
+ v_mfma_f32_16x16x8_xf32 :ref:`vdst<amdgpu_synid_gfx940_vdst_180bef>`::ref:`f32x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_9ad749>`::ref:`f32x2<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_9ad749>`::ref:`f32x2<amdgpu_synid_gfx940_type_deviation>`, :ref:`src2<amdgpu_synid_gfx940_src_af08be>`::ref:`f32x4<amdgpu_synid_gfx940_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
+ v_mfma_f32_16x16x8xf32 :ref:`vdst<amdgpu_synid_gfx940_vdst_180bef>`::ref:`f32x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_9ad749>`::ref:`f32x2<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_9ad749>`::ref:`f32x2<amdgpu_synid_gfx940_type_deviation>`, :ref:`src2<amdgpu_synid_gfx940_src_af08be>`::ref:`f32x4<amdgpu_synid_gfx940_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
+ v_mfma_f32_32x32x1_2b_f32 :ref:`vdst<amdgpu_synid_gfx940_vdst_8c77d4>`::ref:`f32x32<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_be4895>`::ref:`f32<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_be4895>`::ref:`f32<amdgpu_synid_gfx940_type_deviation>`, :ref:`src2<amdgpu_synid_gfx940_src_6cfc4e>`::ref:`f32x32<amdgpu_synid_gfx940_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
+ v_mfma_f32_32x32x1f32 :ref:`vdst<amdgpu_synid_gfx940_vdst_8c77d4>`::ref:`f32x32<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_be4895>`::ref:`f32<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_be4895>`::ref:`f32<amdgpu_synid_gfx940_type_deviation>`, :ref:`src2<amdgpu_synid_gfx940_src_6cfc4e>`::ref:`f32x32<amdgpu_synid_gfx940_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
+ v_mfma_f32_32x32x2_f32 :ref:`vdst<amdgpu_synid_gfx940_vdst_d6f4bd>`::ref:`f32x16<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_be4895>`::ref:`f32<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_be4895>`::ref:`f32<amdgpu_synid_gfx940_type_deviation>`, :ref:`src2<amdgpu_synid_gfx940_src_a578ba>`::ref:`f32x16<amdgpu_synid_gfx940_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
+ v_mfma_f32_32x32x2f32 :ref:`vdst<amdgpu_synid_gfx940_vdst_d6f4bd>`::ref:`f32x16<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_be4895>`::ref:`f32<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_be4895>`::ref:`f32<amdgpu_synid_gfx940_type_deviation>`, :ref:`src2<amdgpu_synid_gfx940_src_a578ba>`::ref:`f32x16<amdgpu_synid_gfx940_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
+ v_mfma_f32_32x32x4_2b_bf16 :ref:`vdst<amdgpu_synid_gfx940_vdst_8c77d4>`::ref:`f32x32<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_9ad749>`::ref:`bf16x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_9ad749>`::ref:`bf16x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`src2<amdgpu_synid_gfx940_src_6cfc4e>`::ref:`f32x32<amdgpu_synid_gfx940_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
+ v_mfma_f32_32x32x4_2b_f16 :ref:`vdst<amdgpu_synid_gfx940_vdst_8c77d4>`::ref:`f32x32<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_9ad749>`::ref:`f16x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_9ad749>`::ref:`f16x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`src2<amdgpu_synid_gfx940_src_6cfc4e>`::ref:`f32x32<amdgpu_synid_gfx940_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
+ v_mfma_f32_32x32x4_xf32 :ref:`vdst<amdgpu_synid_gfx940_vdst_d6f4bd>`::ref:`f32x16<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_9ad749>`::ref:`f32x2<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_9ad749>`::ref:`f32x2<amdgpu_synid_gfx940_type_deviation>`, :ref:`src2<amdgpu_synid_gfx940_src_a578ba>`::ref:`f32x16<amdgpu_synid_gfx940_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
+ v_mfma_f32_32x32x4bf16 :ref:`vdst<amdgpu_synid_gfx940_vdst_8c77d4>`::ref:`f32x32<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_9ad749>`::ref:`bf16x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_9ad749>`::ref:`bf16x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`src2<amdgpu_synid_gfx940_src_6cfc4e>`::ref:`f32x32<amdgpu_synid_gfx940_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
+ v_mfma_f32_32x32x4bf16_1k :ref:`vdst<amdgpu_synid_gfx940_vdst_8c77d4>`::ref:`f32x32<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_9ad749>`::ref:`bf16x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_9ad749>`::ref:`bf16x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`src2<amdgpu_synid_gfx940_src_6cfc4e>`::ref:`f32x32<amdgpu_synid_gfx940_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
+ v_mfma_f32_32x32x4f16 :ref:`vdst<amdgpu_synid_gfx940_vdst_8c77d4>`::ref:`f32x32<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_9ad749>`::ref:`f16x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_9ad749>`::ref:`f16x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`src2<amdgpu_synid_gfx940_src_6cfc4e>`::ref:`f32x32<amdgpu_synid_gfx940_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
+ v_mfma_f32_32x32x4xf32 :ref:`vdst<amdgpu_synid_gfx940_vdst_d6f4bd>`::ref:`f32x16<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_9ad749>`::ref:`f32x2<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_9ad749>`::ref:`f32x2<amdgpu_synid_gfx940_type_deviation>`, :ref:`src2<amdgpu_synid_gfx940_src_a578ba>`::ref:`f32x16<amdgpu_synid_gfx940_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
+ v_mfma_f32_32x32x8_bf16 :ref:`vdst<amdgpu_synid_gfx940_vdst_d6f4bd>`::ref:`f32x16<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_9ad749>`::ref:`bf16x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_9ad749>`::ref:`bf16x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`src2<amdgpu_synid_gfx940_src_a578ba>`::ref:`f32x16<amdgpu_synid_gfx940_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
+ v_mfma_f32_32x32x8_f16 :ref:`vdst<amdgpu_synid_gfx940_vdst_d6f4bd>`::ref:`f32x16<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_9ad749>`::ref:`f16x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_9ad749>`::ref:`f16x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`src2<amdgpu_synid_gfx940_src_a578ba>`::ref:`f32x16<amdgpu_synid_gfx940_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
+ v_mfma_f32_32x32x8bf16 :ref:`vdst<amdgpu_synid_gfx940_vdst_d6f4bd>`::ref:`f32x16<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_9ad749>`::ref:`bf16x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_9ad749>`::ref:`bf16x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`src2<amdgpu_synid_gfx940_src_a578ba>`::ref:`f32x16<amdgpu_synid_gfx940_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
+ v_mfma_f32_32x32x8bf16_1k :ref:`vdst<amdgpu_synid_gfx940_vdst_d6f4bd>`::ref:`f32x16<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_9ad749>`::ref:`bf16x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_9ad749>`::ref:`bf16x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`src2<amdgpu_synid_gfx940_src_a578ba>`::ref:`f32x16<amdgpu_synid_gfx940_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
+ v_mfma_f32_32x32x8f16 :ref:`vdst<amdgpu_synid_gfx940_vdst_d6f4bd>`::ref:`f32x16<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_9ad749>`::ref:`f16x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_9ad749>`::ref:`f16x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`src2<amdgpu_synid_gfx940_src_a578ba>`::ref:`f32x16<amdgpu_synid_gfx940_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
+ v_mfma_f32_4x4x1_16b_f32 :ref:`vdst<amdgpu_synid_gfx940_vdst_180bef>`::ref:`f32x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_be4895>`::ref:`f32<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_be4895>`::ref:`f32<amdgpu_synid_gfx940_type_deviation>`, :ref:`src2<amdgpu_synid_gfx940_src_af08be>`::ref:`f32x4<amdgpu_synid_gfx940_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
+ v_mfma_f32_4x4x1f32 :ref:`vdst<amdgpu_synid_gfx940_vdst_180bef>`::ref:`f32x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_be4895>`::ref:`f32<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_be4895>`::ref:`f32<amdgpu_synid_gfx940_type_deviation>`, :ref:`src2<amdgpu_synid_gfx940_src_af08be>`::ref:`f32x4<amdgpu_synid_gfx940_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
+ v_mfma_f32_4x4x4_16b_bf16 :ref:`vdst<amdgpu_synid_gfx940_vdst_180bef>`::ref:`f32x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_9ad749>`::ref:`bf16x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_9ad749>`::ref:`bf16x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`src2<amdgpu_synid_gfx940_src_af08be>`::ref:`f32x4<amdgpu_synid_gfx940_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
+ v_mfma_f32_4x4x4_16b_f16 :ref:`vdst<amdgpu_synid_gfx940_vdst_180bef>`::ref:`f32x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_9ad749>`::ref:`f16x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_9ad749>`::ref:`f16x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`src2<amdgpu_synid_gfx940_src_af08be>`::ref:`f32x4<amdgpu_synid_gfx940_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
+ v_mfma_f32_4x4x4bf16 :ref:`vdst<amdgpu_synid_gfx940_vdst_180bef>`::ref:`f32x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_9ad749>`::ref:`bf16x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_9ad749>`::ref:`bf16x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`src2<amdgpu_synid_gfx940_src_af08be>`::ref:`f32x4<amdgpu_synid_gfx940_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
+ v_mfma_f32_4x4x4bf16_1k :ref:`vdst<amdgpu_synid_gfx940_vdst_180bef>`::ref:`f32x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_9ad749>`::ref:`bf16x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_9ad749>`::ref:`bf16x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`src2<amdgpu_synid_gfx940_src_af08be>`::ref:`f32x4<amdgpu_synid_gfx940_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
+ v_mfma_f32_4x4x4f16 :ref:`vdst<amdgpu_synid_gfx940_vdst_180bef>`::ref:`f32x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_9ad749>`::ref:`f16x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_9ad749>`::ref:`f16x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`src2<amdgpu_synid_gfx940_src_af08be>`::ref:`f32x4<amdgpu_synid_gfx940_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
+ v_mfma_f64_16x16x4_f64 :ref:`vdst<amdgpu_synid_gfx940_vdst_c8d317>`::ref:`f64x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_9ad749>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_9ad749>`, :ref:`src2<amdgpu_synid_gfx940_src_e5cc81>`::ref:`f64x4<amdgpu_synid_gfx940_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`neg<amdgpu_synid_mfma_neg>`
+ v_mfma_f64_16x16x4f64 :ref:`vdst<amdgpu_synid_gfx940_vdst_c8d317>`::ref:`f64x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_9ad749>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_9ad749>`, :ref:`src2<amdgpu_synid_gfx940_src_e5cc81>`::ref:`f64x4<amdgpu_synid_gfx940_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`neg<amdgpu_synid_mfma_neg>`
+ v_mfma_f64_4x4x4_4b_f64 :ref:`vdst<amdgpu_synid_gfx940_vdst_0f48d1>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_9ad749>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_9ad749>`, :ref:`src2<amdgpu_synid_gfx940_src_64ea89>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`neg<amdgpu_synid_mfma_neg>`
+ v_mfma_f64_4x4x4f64 :ref:`vdst<amdgpu_synid_gfx940_vdst_0f48d1>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_9ad749>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_9ad749>`, :ref:`src2<amdgpu_synid_gfx940_src_64ea89>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`neg<amdgpu_synid_mfma_neg>`
+ v_mfma_i32_16x16x32_i8 :ref:`vdst<amdgpu_synid_gfx940_vdst_180bef>`::ref:`i32x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_9ad749>`::ref:`i8x8<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_9ad749>`::ref:`i8x8<amdgpu_synid_gfx940_type_deviation>`, :ref:`src2<amdgpu_synid_gfx940_src_af08be>`::ref:`i32x4<amdgpu_synid_gfx940_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
+ v_mfma_i32_16x16x32i8 :ref:`vdst<amdgpu_synid_gfx940_vdst_180bef>`::ref:`i32x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_9ad749>`::ref:`i8x8<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_9ad749>`::ref:`i8x8<amdgpu_synid_gfx940_type_deviation>`, :ref:`src2<amdgpu_synid_gfx940_src_af08be>`::ref:`i32x4<amdgpu_synid_gfx940_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
+ v_mfma_i32_16x16x4_4b_i8 :ref:`vdst<amdgpu_synid_gfx940_vdst_d6f4bd>`::ref:`i32x16<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_be4895>`::ref:`i8x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_be4895>`::ref:`i8x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`src2<amdgpu_synid_gfx940_src_a578ba>`::ref:`i32x16<amdgpu_synid_gfx940_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
+ v_mfma_i32_16x16x4i8 :ref:`vdst<amdgpu_synid_gfx940_vdst_d6f4bd>`::ref:`i32x16<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_be4895>`::ref:`i8x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_be4895>`::ref:`i8x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`src2<amdgpu_synid_gfx940_src_a578ba>`::ref:`i32x16<amdgpu_synid_gfx940_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
+ v_mfma_i32_32x32x16_i8 :ref:`vdst<amdgpu_synid_gfx940_vdst_d6f4bd>`::ref:`i32x16<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_9ad749>`::ref:`i8x8<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_9ad749>`::ref:`i8x8<amdgpu_synid_gfx940_type_deviation>`, :ref:`src2<amdgpu_synid_gfx940_src_a578ba>`::ref:`i32x16<amdgpu_synid_gfx940_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
+ v_mfma_i32_32x32x16i8 :ref:`vdst<amdgpu_synid_gfx940_vdst_d6f4bd>`::ref:`i32x16<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_9ad749>`::ref:`i8x8<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_9ad749>`::ref:`i8x8<amdgpu_synid_gfx940_type_deviation>`, :ref:`src2<amdgpu_synid_gfx940_src_a578ba>`::ref:`i32x16<amdgpu_synid_gfx940_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
+ v_mfma_i32_32x32x4_2b_i8 :ref:`vdst<amdgpu_synid_gfx940_vdst_8c77d4>`::ref:`i32x32<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_be4895>`::ref:`i8x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_be4895>`::ref:`i8x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`src2<amdgpu_synid_gfx940_src_6cfc4e>`::ref:`i32x32<amdgpu_synid_gfx940_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
+ v_mfma_i32_32x32x4i8 :ref:`vdst<amdgpu_synid_gfx940_vdst_8c77d4>`::ref:`i32x32<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_be4895>`::ref:`i8x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_be4895>`::ref:`i8x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`src2<amdgpu_synid_gfx940_src_6cfc4e>`::ref:`i32x32<amdgpu_synid_gfx940_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
+ v_mfma_i32_4x4x4_16b_i8 :ref:`vdst<amdgpu_synid_gfx940_vdst_180bef>`::ref:`i32x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_be4895>`::ref:`i8x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_be4895>`::ref:`i8x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`src2<amdgpu_synid_gfx940_src_af08be>`::ref:`i32x4<amdgpu_synid_gfx940_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
+ v_mfma_i32_4x4x4i8 :ref:`vdst<amdgpu_synid_gfx940_vdst_180bef>`::ref:`i32x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_be4895>`::ref:`i8x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_be4895>`::ref:`i8x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`src2<amdgpu_synid_gfx940_src_af08be>`::ref:`i32x4<amdgpu_synid_gfx940_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
+ v_pk_add_f16 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_pk_add_f32 :ref:`vdst<amdgpu_synid_gfx940_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx940_src_f73668>`, :ref:`src1<amdgpu_synid_gfx940_src_f73668>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+ v_pk_add_i16 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_pk_add_u16 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_pk_ashrrev_i16 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`::ref:`u16x2<amdgpu_synid_gfx940_type_deviation>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+ v_pk_fma_f16 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src2<amdgpu_synid_gfx940_src_d578c4>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_pk_fma_f32 :ref:`vdst<amdgpu_synid_gfx940_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx940_src_f73668>`, :ref:`src1<amdgpu_synid_gfx940_src_f73668>`, :ref:`src2<amdgpu_synid_gfx940_src_f73668>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+ v_pk_lshlrev_b16 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`::ref:`u16x2<amdgpu_synid_gfx940_type_deviation>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+ v_pk_lshrrev_b16 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`::ref:`u16x2<amdgpu_synid_gfx940_type_deviation>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+ v_pk_mad_i16 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>`, :ref:`src2<amdgpu_synid_gfx940_src_d95796>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_pk_mad_u16 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>`, :ref:`src2<amdgpu_synid_gfx940_src_d95796>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_pk_max_f16 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_pk_max_i16 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+ v_pk_max_u16 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+ v_pk_min_f16 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_pk_min_i16 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+ v_pk_min_u16 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+ v_pk_mov_b32 :ref:`vdst<amdgpu_synid_gfx940_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx940_src_f73668>`, :ref:`src1<amdgpu_synid_gfx940_src_f73668>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+ v_pk_mul_f16 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_pk_mul_f32 :ref:`vdst<amdgpu_synid_gfx940_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx940_src_f73668>`, :ref:`src1<amdgpu_synid_gfx940_src_f73668>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+ v_pk_mul_lo_u16 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+ v_pk_sub_i16 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_pk_sub_u16 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_smfmac_f32_16x16x32_bf16 :ref:`vdst<amdgpu_synid_gfx940_vdst_180bef>`::ref:`f32x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_9ad749>`::ref:`bf16x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_848ff7>`::ref:`bf16x8<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc2<amdgpu_synid_gfx940_vsrc_6802ce>`::ref:`b32<amdgpu_synid_gfx940_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>`
+ v_smfmac_f32_16x16x32_f16 :ref:`vdst<amdgpu_synid_gfx940_vdst_180bef>`::ref:`f32x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_9ad749>`::ref:`f16x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_848ff7>`::ref:`f16x8<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc2<amdgpu_synid_gfx940_vsrc_6802ce>`::ref:`b32<amdgpu_synid_gfx940_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>`
+ v_smfmac_f32_16x16x32bf16 :ref:`vdst<amdgpu_synid_gfx940_vdst_180bef>`::ref:`f32x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_9ad749>`::ref:`bf16x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_848ff7>`::ref:`bf16x8<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc2<amdgpu_synid_gfx940_vsrc_6802ce>`::ref:`b32<amdgpu_synid_gfx940_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>`
+ v_smfmac_f32_16x16x32f16 :ref:`vdst<amdgpu_synid_gfx940_vdst_180bef>`::ref:`f32x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_9ad749>`::ref:`f16x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_848ff7>`::ref:`f16x8<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc2<amdgpu_synid_gfx940_vsrc_6802ce>`::ref:`b32<amdgpu_synid_gfx940_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>`
+ v_smfmac_f32_32x32x16_bf16 :ref:`vdst<amdgpu_synid_gfx940_vdst_d6f4bd>`::ref:`f32x16<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_9ad749>`::ref:`bf16x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_848ff7>`::ref:`bf16x8<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc2<amdgpu_synid_gfx940_vsrc_6802ce>`::ref:`b32<amdgpu_synid_gfx940_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>`
+ v_smfmac_f32_32x32x16_f16 :ref:`vdst<amdgpu_synid_gfx940_vdst_d6f4bd>`::ref:`f32x16<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_9ad749>`::ref:`f16x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_848ff7>`::ref:`f16x8<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc2<amdgpu_synid_gfx940_vsrc_6802ce>`::ref:`b32<amdgpu_synid_gfx940_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>`
+ v_smfmac_f32_32x32x16bf16 :ref:`vdst<amdgpu_synid_gfx940_vdst_d6f4bd>`::ref:`f32x16<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_9ad749>`::ref:`bf16x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_848ff7>`::ref:`bf16x8<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc2<amdgpu_synid_gfx940_vsrc_6802ce>`::ref:`b32<amdgpu_synid_gfx940_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>`
+ v_smfmac_f32_32x32x16f16 :ref:`vdst<amdgpu_synid_gfx940_vdst_d6f4bd>`::ref:`f32x16<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_9ad749>`::ref:`f16x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_848ff7>`::ref:`f16x8<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc2<amdgpu_synid_gfx940_vsrc_6802ce>`::ref:`b32<amdgpu_synid_gfx940_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>`
+ v_smfmac_i32_16x16x64_i8 :ref:`vdst<amdgpu_synid_gfx940_vdst_180bef>`::ref:`i32x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_9ad749>`::ref:`i8x8<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_848ff7>`::ref:`i32x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc2<amdgpu_synid_gfx940_vsrc_6802ce>`::ref:`b32<amdgpu_synid_gfx940_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>`
+ v_smfmac_i32_16x16x64i8 :ref:`vdst<amdgpu_synid_gfx940_vdst_180bef>`::ref:`i32x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_9ad749>`::ref:`i8x8<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_848ff7>`::ref:`i32x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc2<amdgpu_synid_gfx940_vsrc_6802ce>`::ref:`b32<amdgpu_synid_gfx940_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>`
+ v_smfmac_i32_32x32x32_i8 :ref:`vdst<amdgpu_synid_gfx940_vdst_d6f4bd>`::ref:`i32x16<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_9ad749>`::ref:`i8x8<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_848ff7>`::ref:`i32x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc2<amdgpu_synid_gfx940_vsrc_6802ce>`::ref:`b32<amdgpu_synid_gfx940_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>`
+ v_smfmac_i32_32x32x32i8 :ref:`vdst<amdgpu_synid_gfx940_vdst_d6f4bd>`::ref:`i32x16<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx940_vsrc_9ad749>`::ref:`i8x8<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_848ff7>`::ref:`i32x4<amdgpu_synid_gfx940_type_deviation>`, :ref:`vsrc2<amdgpu_synid_gfx940_vsrc_6802ce>`::ref:`b32<amdgpu_synid_gfx940_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>`
+
+VOPC
+----
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST** **SRC0** **SRC1** **MODIFIERS**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ v_cmp_class_f16 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`::ref:`b32<amdgpu_synid_gfx940_type_deviation>`
+ v_cmp_class_f16_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>`::ref:`b32<amdgpu_synid_gfx940_type_deviation>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_class_f32 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`::ref:`b32<amdgpu_synid_gfx940_type_deviation>`
+ v_cmp_class_f32_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>`::ref:`b32<amdgpu_synid_gfx940_type_deviation>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_class_f64 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_56ed80>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`::ref:`b32<amdgpu_synid_gfx940_type_deviation>`
+ v_cmp_eq_f16 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmp_eq_f16_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_eq_f32 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmp_eq_f32_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_eq_f64 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_56ed80>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_fd235e>`
+ v_cmp_eq_i16 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_4de5c6>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmp_eq_i16_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_eq_i32 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmp_eq_i32_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_eq_i64 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_56ed80>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_fd235e>`
+ v_cmp_eq_u16 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_4de5c6>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmp_eq_u16_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_eq_u32 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmp_eq_u32_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_eq_u64 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_56ed80>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_fd235e>`
+ v_cmp_f_f16 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmp_f_f16_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_f_f32 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmp_f_f32_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_f_f64 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_56ed80>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_fd235e>`
+ v_cmp_f_i16 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_4de5c6>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmp_f_i16_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_f_i32 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmp_f_i32_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_f_i64 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_56ed80>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_fd235e>`
+ v_cmp_f_u16 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_4de5c6>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmp_f_u16_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_f_u32 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmp_f_u32_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_f_u64 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_56ed80>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_fd235e>`
+ v_cmp_ge_f16 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmp_ge_f16_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_ge_f32 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmp_ge_f32_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_ge_f64 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_56ed80>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_fd235e>`
+ v_cmp_ge_i16 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_4de5c6>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmp_ge_i16_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_ge_i32 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmp_ge_i32_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_ge_i64 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_56ed80>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_fd235e>`
+ v_cmp_ge_u16 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_4de5c6>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmp_ge_u16_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_ge_u32 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmp_ge_u32_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_ge_u64 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_56ed80>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_fd235e>`
+ v_cmp_gt_f16 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmp_gt_f16_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_gt_f32 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmp_gt_f32_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_gt_f64 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_56ed80>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_fd235e>`
+ v_cmp_gt_i16 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_4de5c6>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmp_gt_i16_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_gt_i32 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmp_gt_i32_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_gt_i64 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_56ed80>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_fd235e>`
+ v_cmp_gt_u16 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_4de5c6>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmp_gt_u16_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_gt_u32 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmp_gt_u32_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_gt_u64 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_56ed80>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_fd235e>`
+ v_cmp_le_f16 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmp_le_f16_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_le_f32 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmp_le_f32_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_le_f64 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_56ed80>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_fd235e>`
+ v_cmp_le_i16 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_4de5c6>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmp_le_i16_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_le_i32 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmp_le_i32_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_le_i64 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_56ed80>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_fd235e>`
+ v_cmp_le_u16 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_4de5c6>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmp_le_u16_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_le_u32 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmp_le_u32_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_le_u64 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_56ed80>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_fd235e>`
+ v_cmp_lg_f16 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmp_lg_f16_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_lg_f32 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmp_lg_f32_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_lg_f64 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_56ed80>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_fd235e>`
+ v_cmp_lt_f16 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmp_lt_f16_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_lt_f32 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmp_lt_f32_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_lt_f64 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_56ed80>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_fd235e>`
+ v_cmp_lt_i16 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_4de5c6>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmp_lt_i16_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_lt_i32 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmp_lt_i32_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_lt_i64 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_56ed80>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_fd235e>`
+ v_cmp_lt_u16 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_4de5c6>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmp_lt_u16_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_lt_u32 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmp_lt_u32_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_lt_u64 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_56ed80>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_fd235e>`
+ v_cmp_ne_i16 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_4de5c6>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmp_ne_i16_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_ne_i32 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmp_ne_i32_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_ne_i64 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_56ed80>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_fd235e>`
+ v_cmp_ne_u16 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_4de5c6>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmp_ne_u16_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_ne_u32 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmp_ne_u32_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_ne_u64 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_56ed80>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_fd235e>`
+ v_cmp_neq_f16 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmp_neq_f16_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_neq_f32 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmp_neq_f32_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_neq_f64 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_56ed80>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_fd235e>`
+ v_cmp_nge_f16 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmp_nge_f16_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_nge_f32 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmp_nge_f32_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_nge_f64 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_56ed80>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_fd235e>`
+ v_cmp_ngt_f16 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmp_ngt_f16_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_ngt_f32 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmp_ngt_f32_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_ngt_f64 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_56ed80>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_fd235e>`
+ v_cmp_nle_f16 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmp_nle_f16_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_nle_f32 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmp_nle_f32_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_nle_f64 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_56ed80>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_fd235e>`
+ v_cmp_nlg_f16 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmp_nlg_f16_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_nlg_f32 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmp_nlg_f32_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_nlg_f64 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_56ed80>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_fd235e>`
+ v_cmp_nlt_f16 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmp_nlt_f16_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_nlt_f32 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmp_nlt_f32_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_nlt_f64 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_56ed80>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_fd235e>`
+ v_cmp_o_f16 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmp_o_f16_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_o_f32 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmp_o_f32_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_o_f64 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_56ed80>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_fd235e>`
+ v_cmp_t_i16 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_4de5c6>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmp_t_i16_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_t_i32 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmp_t_i32_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_t_i64 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_56ed80>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_fd235e>`
+ v_cmp_t_u16 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_4de5c6>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmp_t_u16_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_t_u32 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmp_t_u32_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_t_u64 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_56ed80>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_fd235e>`
+ v_cmp_tru_f16 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmp_tru_f16_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_tru_f32 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmp_tru_f32_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_tru_f64 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_56ed80>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_fd235e>`
+ v_cmp_u_f16 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmp_u_f16_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_u_f32 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmp_u_f32_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_718cc4>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_u_f64 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_56ed80>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_fd235e>`
+ v_cmpx_class_f16 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`::ref:`b32<amdgpu_synid_gfx940_type_deviation>`
+ v_cmpx_class_f16_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>`::ref:`b32<amdgpu_synid_gfx940_type_deviation>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_class_f32 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`::ref:`b32<amdgpu_synid_gfx940_type_deviation>`
+ v_cmpx_class_f32_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>`::ref:`b32<amdgpu_synid_gfx940_type_deviation>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_class_f64 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_56ed80>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`::ref:`b32<amdgpu_synid_gfx940_type_deviation>`
+ v_cmpx_eq_f16 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmpx_eq_f16_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_eq_f32 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmpx_eq_f32_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_eq_f64 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_56ed80>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_fd235e>`
+ v_cmpx_eq_i16 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_4de5c6>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmpx_eq_i16_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_eq_i32 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmpx_eq_i32_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_eq_i64 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_56ed80>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_fd235e>`
+ v_cmpx_eq_u16 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_4de5c6>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmpx_eq_u16_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_eq_u32 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmpx_eq_u32_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_eq_u64 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_56ed80>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_fd235e>`
+ v_cmpx_f_f16 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmpx_f_f16_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_f_f32 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmpx_f_f32_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_f_f64 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_56ed80>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_fd235e>`
+ v_cmpx_f_i16 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_4de5c6>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmpx_f_i16_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_f_i32 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmpx_f_i32_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_f_i64 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_56ed80>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_fd235e>`
+ v_cmpx_f_u16 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_4de5c6>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmpx_f_u16_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_f_u32 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmpx_f_u32_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_f_u64 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_56ed80>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_fd235e>`
+ v_cmpx_ge_f16 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmpx_ge_f16_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_ge_f32 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmpx_ge_f32_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_ge_f64 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_56ed80>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_fd235e>`
+ v_cmpx_ge_i16 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_4de5c6>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmpx_ge_i16_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_ge_i32 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmpx_ge_i32_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_ge_i64 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_56ed80>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_fd235e>`
+ v_cmpx_ge_u16 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_4de5c6>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmpx_ge_u16_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_ge_u32 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmpx_ge_u32_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_ge_u64 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_56ed80>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_fd235e>`
+ v_cmpx_gt_f16 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmpx_gt_f16_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_gt_f32 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmpx_gt_f32_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_gt_f64 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_56ed80>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_fd235e>`
+ v_cmpx_gt_i16 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_4de5c6>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmpx_gt_i16_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_gt_i32 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmpx_gt_i32_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_gt_i64 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_56ed80>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_fd235e>`
+ v_cmpx_gt_u16 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_4de5c6>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmpx_gt_u16_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_gt_u32 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmpx_gt_u32_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_gt_u64 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_56ed80>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_fd235e>`
+ v_cmpx_le_f16 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmpx_le_f16_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_le_f32 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmpx_le_f32_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_le_f64 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_56ed80>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_fd235e>`
+ v_cmpx_le_i16 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_4de5c6>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmpx_le_i16_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_le_i32 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmpx_le_i32_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_le_i64 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_56ed80>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_fd235e>`
+ v_cmpx_le_u16 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_4de5c6>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmpx_le_u16_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_le_u32 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmpx_le_u32_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_le_u64 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_56ed80>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_fd235e>`
+ v_cmpx_lg_f16 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmpx_lg_f16_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_lg_f32 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmpx_lg_f32_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_lg_f64 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_56ed80>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_fd235e>`
+ v_cmpx_lt_f16 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmpx_lt_f16_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_lt_f32 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmpx_lt_f32_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_lt_f64 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_56ed80>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_fd235e>`
+ v_cmpx_lt_i16 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_4de5c6>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmpx_lt_i16_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_lt_i32 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmpx_lt_i32_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_lt_i64 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_56ed80>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_fd235e>`
+ v_cmpx_lt_u16 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_4de5c6>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmpx_lt_u16_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_lt_u32 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmpx_lt_u32_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_lt_u64 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_56ed80>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_fd235e>`
+ v_cmpx_ne_i16 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_4de5c6>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmpx_ne_i16_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_ne_i32 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmpx_ne_i32_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_ne_i64 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_56ed80>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_fd235e>`
+ v_cmpx_ne_u16 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_4de5c6>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmpx_ne_u16_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_ne_u32 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmpx_ne_u32_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_ne_u64 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_56ed80>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_fd235e>`
+ v_cmpx_neq_f16 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmpx_neq_f16_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_neq_f32 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmpx_neq_f32_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_neq_f64 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_56ed80>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_fd235e>`
+ v_cmpx_nge_f16 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmpx_nge_f16_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_nge_f32 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmpx_nge_f32_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_nge_f64 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_56ed80>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_fd235e>`
+ v_cmpx_ngt_f16 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmpx_ngt_f16_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_ngt_f32 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmpx_ngt_f32_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_ngt_f64 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_56ed80>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_fd235e>`
+ v_cmpx_nle_f16 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmpx_nle_f16_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_nle_f32 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmpx_nle_f32_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_nle_f64 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_56ed80>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_fd235e>`
+ v_cmpx_nlg_f16 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmpx_nlg_f16_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_nlg_f32 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmpx_nlg_f32_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_nlg_f64 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_56ed80>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_fd235e>`
+ v_cmpx_nlt_f16 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmpx_nlt_f16_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_nlt_f32 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmpx_nlt_f32_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_nlt_f64 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_56ed80>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_fd235e>`
+ v_cmpx_o_f16 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmpx_o_f16_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_o_f32 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmpx_o_f32_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_o_f64 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_56ed80>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_fd235e>`
+ v_cmpx_t_i16 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_4de5c6>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmpx_t_i16_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_t_i32 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmpx_t_i32_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_t_i64 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_56ed80>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_fd235e>`
+ v_cmpx_t_u16 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_4de5c6>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmpx_t_u16_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d95796>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx940_src_d95796>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_t_u32 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmpx_t_u32_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_t_u64 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_56ed80>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_fd235e>`
+ v_cmpx_tru_f16 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmpx_tru_f16_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_tru_f32 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmpx_tru_f32_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_tru_f64 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_56ed80>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_fd235e>`
+ v_cmpx_u_f16 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmpx_u_f16_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_u_f32 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_e1561c>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_6802ce>`
+ v_cmpx_u_f32_sdwa :ref:`sdst<amdgpu_synid_gfx940_sdst_a319e6>`, :ref:`src0<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx940_src_d578c4>`::ref:`m<amdgpu_synid_gfx940_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_u_f64 :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940_src_56ed80>`, :ref:`vsrc1<amdgpu_synid_gfx940_vsrc_fd235e>`
+
+.. |---| unicode:: U+02014 .. em dash
+
+.. toctree::
+ :hidden:
+
+ gfx940_dst_4f3f9a
+ gfx940_dst_95761f
+ gfx940_fx_operand
+ gfx940_hwreg
+ gfx940_imask
+ gfx940_imm16_73139a
+ gfx940_imm16_a04fb3
+ gfx940_label
+ gfx940_m_254bcb
+ gfx940_m_f5d306
+ gfx940_msg
+ gfx940_opt_0d447d
+ gfx940_opt_7c211e
+ gfx940_probe
+ gfx940_saddr_22dbc1
+ gfx940_saddr_a37373
+ gfx940_sbase_010ce0
+ gfx940_sbase_044055
+ gfx940_sbase_0cd545
+ gfx940_sdata_595c25
+ gfx940_sdata_7cbd60
+ gfx940_sdata_aefe00
+ gfx940_sdata_c6aec1
+ gfx940_sdata_e9f591
+ gfx940_sdata_eb6f2a
+ gfx940_sdst_06b266
+ gfx940_sdst_0804b1
+ gfx940_sdst_362c37
+ gfx940_sdst_3bc700
+ gfx940_sdst_59204c
+ gfx940_sdst_718cc4
+ gfx940_sdst_94342d
+ gfx940_sdst_a319e6
+ gfx940_simm32_6f0844
+ gfx940_simm32_a3e80c
+ gfx940_simm32_be0c1c
+ gfx940_soffset_4318ca
+ gfx940_soffset_7b8c50
+ gfx940_soffset_f33c5c
+ gfx940_src_4de5c6
+ gfx940_src_56ed80
+ gfx940_src_64ea89
+ gfx940_src_6cfc4e
+ gfx940_src_a578ba
+ gfx940_src_af08be
+ gfx940_src_d578c4
+ gfx940_src_d95796
+ gfx940_src_e1561c
+ gfx940_src_e5cc81
+ gfx940_src_f73668
+ gfx940_srsrc
+ gfx940_ssrc_4db4a9
+ gfx940_ssrc_57838b
+ gfx940_ssrc_595c25
+ gfx940_ssrc_65f041
+ gfx940_ssrc_aee59c
+ gfx940_ssrc_c31902
+ gfx940_ssrc_c5d631
+ gfx940_ssrc_c8a322
+ gfx940_ssrc_e9f591
+ gfx940_type_deviation
+ gfx940_vaddr_0212e3
+ gfx940_vaddr_6ab80d
+ gfx940_vaddr_9f7133
+ gfx940_vaddr_b73dc0
+ gfx940_vaddr_f20ee4
+ gfx940_vcc
+ gfx940_vdata0_9ad749
+ gfx940_vdata0_be4895
+ gfx940_vdata1_9ad749
+ gfx940_vdata1_be4895
+ gfx940_vdata_24882b
+ gfx940_vdata_5eef12
+ gfx940_vdata_848ff7
+ gfx940_vdata_9ad749
+ gfx940_vdata_be4895
+ gfx940_vdata_c8a58b
+ gfx940_vdata_cfb402
+ gfx940_vdst_08b5ba
+ gfx940_vdst_0c37de
+ gfx940_vdst_0f48d1
+ gfx940_vdst_180bef
+ gfx940_vdst_260aca
+ gfx940_vdst_5258b4
+ gfx940_vdst_56baf6
+ gfx940_vdst_63b743
+ gfx940_vdst_69a144
+ gfx940_vdst_78dd0a
+ gfx940_vdst_89680f
+ gfx940_vdst_8c77d4
+ gfx940_vdst_a32035
+ gfx940_vdst_bce42a
+ gfx940_vdst_bdb32f
+ gfx940_vdst_c3d63a
+ gfx940_vdst_c8d317
+ gfx940_vdst_d0c0cb
+ gfx940_vdst_d6f4bd
+ gfx940_vdst_d8236e
+ gfx940_vdst_e2898f
+ gfx940_vdst_fa7dbd
+ gfx940_vsrc_1027ca
+ gfx940_vsrc_6802ce
+ gfx940_vsrc_848ff7
+ gfx940_vsrc_9ad749
+ gfx940_vsrc_be4895
+ gfx940_vsrc_e016a1
+ gfx940_vsrc_fd235e
+ gfx940_waitcnt
diff --git a/llvm/docs/AMDGPU/gfx940_dst_4f3f9a.rst b/llvm/docs/AMDGPU/gfx940_dst_4f3f9a.rst
new file mode 100644
index 0000000000000..58782d53a70b9
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx940_dst_4f3f9a.rst
@@ -0,0 +1,13 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx940_dst_4f3f9a:
+
+dst
+===
+
+This is an input operand. It may optionally serve as a destination if :ref:`sc0<amdgpu_synid_sc0>` is specified.
diff --git a/llvm/docs/AMDGPU/gfx940_dst_95761f.rst b/llvm/docs/AMDGPU/gfx940_dst_95761f.rst
new file mode 100644
index 0000000000000..fcffcea92df0d
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx940_dst_95761f.rst
@@ -0,0 +1,13 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx940_dst_95761f:
+
+dst
+===
+
+This is an input operand. It may optionally serve as a destination if :ref:`glc<amdgpu_synid_glc>` is specified.
diff --git a/llvm/docs/AMDGPU/gfx940_fx_operand.rst b/llvm/docs/AMDGPU/gfx940_fx_operand.rst
new file mode 100644
index 0000000000000..e935c669cb6f6
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx940_fx_operand.rst
@@ -0,0 +1,16 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx940_fx_operand:
+
+FX Operand
+==========
+
+This is an *f32* or *f16* operand depending on instruction modifiers:
+
+* Operand size is controlled by :ref:`m_op_sel_hi<amdgpu_synid_mad_mix_op_sel_hi>`.
+* Location of 16-bit operand is controlled by :ref:`m_op_sel<amdgpu_synid_mad_mix_op_sel>`.
diff --git a/llvm/docs/AMDGPU/gfx940_hwreg.rst b/llvm/docs/AMDGPU/gfx940_hwreg.rst
new file mode 100644
index 0000000000000..2ad2bd8932da6
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx940_hwreg.rst
@@ -0,0 +1,82 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx940_hwreg:
+
+hwreg
+=====
+
+Bits of a hardware register being accessed.
+
+The bits of this operand have the following meaning:
+
+ ======= ===================== ============
+ Bits Description Value Range
+ ======= ===================== ============
+ 5:0 Register *id*. 0..63
+ 10:6 First bit *offset*. 0..31
+ 15:11 *Size* in bits. 1..32
+ ======= ===================== ============
+
+This operand may be specified as one of the following:
+
+* An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range 0..0xFFFF.
+* An *hwreg* value described below.
+
+ ==================================== ============================================================================
+ Hwreg Value Syntax Description
+ ==================================== ============================================================================
+ hwreg({0..63}) All bits of a register indicated by its *id*.
+ hwreg(<*name*>) All bits of a register indicated by its *name*.
+ hwreg({0..63}, {0..31}, {1..32}) Register bits indicated by register *id*, first bit *offset* and *size*.
+ hwreg(<*name*>, {0..31}, {1..32}) Register bits indicated by register *name*, first bit *offset* and *size*.
+ ==================================== ============================================================================
+
+Numeric values may be specified as positive :ref:`integer numbers<amdgpu_synid_integer_number>`
+or :ref:`absolute expressions<amdgpu_synid_absolute_expression>`.
+
+Defined register *names* include:
+
+ ============================== ==========================================
+ Name Description
+ ============================== ==========================================
+ HW_REG_MODE Shader writeable mode bits.
+ HW_REG_STATUS Shader read-only status.
+ HW_REG_TRAPSTS Trap status.
+ HW_REG_HW_ID Id of wave, simd, compute unit, etc.
+ HW_REG_GPR_ALLOC Per-wave SGPR and VGPR allocation.
+ HW_REG_LDS_ALLOC Per-wave LDS allocation.
+ HW_REG_IB_STS Counters of outstanding instructions.
+ HW_REG_SH_MEM_BASES Memory aperture.
+ HW_REG_TBA_LO tba_lo register.
+ HW_REG_TBA_HI tba_hi register.
+ HW_REG_TMA_LO tma_lo register.
+ HW_REG_TMA_HI tma_hi register.
+ HW_REG_XCC_ID ID of this XCC (compute accelerator chip).
+ HW_REG_SQ_PERF_SNAPSHOT_DATA Performance snapshot data (first part).
+ HW_REG_SQ_PERF_SNAPSHOT_DATA1 Performance snapshot data (second part).
+ HW_REG_SQ_PERF_SNAPSHOT_PC_LO PC.lo of wave when snapshot was taken.
+ HW_REG_SQ_PERF_SNAPSHOT_PC_HI PC.hi of wave when snapshot was taken.
+ ============================== ==========================================
+
+Examples:
+
+.. parsed-literal::
+
+ reg = 1
+ offset = 2
+ size = 4
+ hwreg_enc = reg | (offset << 6) | ((size - 1) << 11)
+
+ s_getreg_b32 s2, 0x1881
+ s_getreg_b32 s2, hwreg_enc // the same as above
+ s_getreg_b32 s2, hwreg(1, 2, 4) // the same as above
+ s_getreg_b32 s2, hwreg(reg, offset, size) // the same as above
+
+ s_getreg_b32 s2, hwreg(15)
+ s_getreg_b32 s2, hwreg(51, 1, 31)
+ s_getreg_b32 s2, hwreg(HW_REG_LDS_ALLOC, 0, 1)
diff --git a/llvm/docs/AMDGPU/gfx940_imask.rst b/llvm/docs/AMDGPU/gfx940_imask.rst
new file mode 100644
index 0000000000000..d904db56e1c10
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx940_imask.rst
@@ -0,0 +1,65 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx940_imask:
+
+imask
+=====
+
+This operand is a mask which controls indexing mode for operands of subsequent instructions.
+Bits 0, 1 and 2 control indexing of *src0*, *src1* and *src2*, while bit 3 controls indexing of *dst*.
+Value 1 enables indexing and value 0 disables it.
+
+ ===== ========================================
+ Bit Meaning
+ ===== ========================================
+ 0 Enables or disables *src0* indexing.
+ 1 Enables or disables *src1* indexing.
+ 2 Enables or disables *src2* indexing.
+ 3 Enables or disables *dst* indexing.
+ ===== ========================================
+
+This operand may be specified as one of the following:
+
+* An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range 0..15.
+* A *gpr_idx* value described below.
+
+ ==================================== ===========================================
+ Gpr_idx Value Syntax Description
+ ==================================== ===========================================
+ gpr_idx(*<operands>*) Enable indexing for specified *operands*
+ and disable it for the rest.
+ *Operands* is a comma-separated list of
+ values which may include:
+
+ * "SRC0" - enable *src0* indexing.
+
+ * "SRC1" - enable *src1* indexing.
+
+ * "SRC2" - enable *src2* indexing.
+
+ * "DST" - enable *dst* indexing.
+
+ Each of these values may be specified only
+ once.
+
+ *Operands* list may be empty; this syntax
+ disables indexing for all operands.
+ ==================================== ===========================================
+
+Examples:
+
+.. parsed-literal::
+
+ s_set_gpr_idx_mode 0
+ s_set_gpr_idx_mode gpr_idx() // the same as above
+
+ s_set_gpr_idx_mode 15
+ s_set_gpr_idx_mode gpr_idx(DST,SRC0,SRC1,SRC2) // the same as above
+ s_set_gpr_idx_mode gpr_idx(SRC0,SRC1,SRC2,DST) // the same as above
+
+ s_set_gpr_idx_mode gpr_idx(DST,SRC1)
diff --git a/llvm/docs/AMDGPU/gfx940_imm16_73139a.rst b/llvm/docs/AMDGPU/gfx940_imm16_73139a.rst
new file mode 100644
index 0000000000000..c4c0f28eefeb6
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx940_imm16_73139a.rst
@@ -0,0 +1,13 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx940_imm16_73139a:
+
+imm16
+=====
+
+An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range -32768..65535.
diff --git a/llvm/docs/AMDGPU/gfx940_imm16_a04fb3.rst b/llvm/docs/AMDGPU/gfx940_imm16_a04fb3.rst
new file mode 100644
index 0000000000000..c6787df41aca7
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx940_imm16_a04fb3.rst
@@ -0,0 +1,13 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx940_imm16_a04fb3:
+
+imm16
+=====
+
+An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range 0..65535.
diff --git a/llvm/docs/AMDGPU/gfx940_label.rst b/llvm/docs/AMDGPU/gfx940_label.rst
new file mode 100644
index 0000000000000..be1018b984ec8
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx940_label.rst
@@ -0,0 +1,36 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx940_label:
+
+label
+=====
+
+A branch target which is a 16-bit signed integer treated as a PC-relative dword offset.
+
+This operand may be specified as one of the following:
+
+* An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range -32768..65535.
+* A :ref:`symbol<amdgpu_synid_symbol>` (for example, a label) representing a relocatable address in the same compilation unit where it is referred from. The value is handled as a 16-bit PC-relative dword offset to be resolved by a linker.
+
+Examples:
+
+.. parsed-literal::
+
+ offset = 30
+ label_1:
+ label_2 = . + 4
+
+ s_branch 32
+ s_branch offset + 2
+ s_branch label_1
+ s_branch label_2
+ s_branch label_3
+ s_branch label_4
+
+ label_3 = label_2 + 4
+ label_4:
diff --git a/llvm/docs/AMDGPU/gfx940_m_254bcb.rst b/llvm/docs/AMDGPU/gfx940_m_254bcb.rst
new file mode 100644
index 0000000000000..f8a56f55339e3
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx940_m_254bcb.rst
@@ -0,0 +1,13 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx940_m_254bcb:
+
+m
+=
+
+This operand may be used with integer operand modifier :ref:`sext<amdgpu_synid_sext>`.
diff --git a/llvm/docs/AMDGPU/gfx940_m_f5d306.rst b/llvm/docs/AMDGPU/gfx940_m_f5d306.rst
new file mode 100644
index 0000000000000..324faf5fff66f
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx940_m_f5d306.rst
@@ -0,0 +1,13 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx940_m_f5d306:
+
+m
+=
+
+This operand may be used with floating point operand modifiers :ref:`abs<amdgpu_synid_abs>` and :ref:`neg<amdgpu_synid_neg>`.
diff --git a/llvm/docs/AMDGPU/gfx940_msg.rst b/llvm/docs/AMDGPU/gfx940_msg.rst
new file mode 100644
index 0000000000000..b357a689b8f1b
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx940_msg.rst
@@ -0,0 +1,100 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx940_msg:
+
+msg
+===
+
+A 16-bit message code. The bits of this operand have the following meaning:
+
+ ============ =============================== ===============
+ Bits Description Value Range
+ ============ =============================== ===============
+ 3:0 Message *type*. 0..15
+ 6:4 Optional *operation*. 0..7
+ 7:7 Unused. \-
+ 9:8 Optional *stream*. 0..3
+ 15:10 Unused. \-
+ ============ =============================== ===============
+
+This operand may be specified as one of the following:
+
+* An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range 0..0xFFFF.
+* A *sendmsg* value described below.
+
+ ==================================== ====================================================
+ Sendmsg Value Syntax Description
+ ==================================== ====================================================
+ sendmsg(<*type*>) A message identified by its *type*.
+ sendmsg(<*type*>,<*op*>) A message identified by its *type* and *operation*.
+ sendmsg(<*type*>,<*op*>,<*stream*>) A message identified by its *type* and *operation*
+ with a stream *id*.
+ ==================================== ====================================================
+
+*Type* may be specified using message *name* or message *id*.
+
+*Op* may be specified using operation *name* or operation *id*.
+
+Stream *id* is an integer in the range 0..3.
+
+Numeric values may be specified as positive :ref:`integer numbers<amdgpu_synid_integer_number>`
+or :ref:`absolute expressions<amdgpu_synid_absolute_expression>`.
+
+Each message type supports specific operations:
+
+ ====================== ========== ============================== ============ ==========
+ Message name Message Id Supported Operations Operation Id Stream Id
+ ====================== ========== ============================== ============ ==========
+ MSG_INTERRUPT 1 \- \- \-
+ MSG_GS 2 GS_OP_CUT 1 Optional
+ \ GS_OP_EMIT 2 Optional
+ \ GS_OP_EMIT_CUT 3 Optional
+ MSG_GS_DONE 3 GS_OP_NOP 0 \-
+ \ GS_OP_CUT 1 Optional
+ \ GS_OP_EMIT 2 Optional
+ \ GS_OP_EMIT_CUT 3 Optional
+ MSG_SAVEWAVE 4 \- \- \-
+ MSG_STALL_WAVE_GEN 5 \- \- \-
+ MSG_HALT_WAVES 6 \- \- \-
+ MSG_ORDERED_PS_DONE 7 \- \- \-
+ MSG_EARLY_PRIM_DEALLOC 8 \- \- \-
+ MSG_GS_ALLOC_REQ 9 \- \- \-
+ MSG_GET_DOORBELL 10 \- \- \-
+ MSG_SYSMSG 15 SYSMSG_OP_ECC_ERR_INTERRUPT 1 \-
+ \ SYSMSG_OP_REG_RD 2 \-
+ \ SYSMSG_OP_TTRACE_PC 4 \-
+ ====================== ========== ============================== ============ ==========
+
+*Sendmsg* arguments are validated depending on how *type* value is specified:
+
+* If message *type* is specified by name, arguments values must satisfy limitations detailed in the table above.
+* If message *type* is specified as a number, each argument must not exceed corresponding value range (see the first table).
+
+Examples:
+
+.. parsed-literal::
+
+ // numeric message code
+ msg = 0x10
+ s_sendmsg 0x12
+ s_sendmsg msg + 2
+
+ // sendmsg with strict arguments validation
+ s_sendmsg sendmsg(MSG_INTERRUPT)
+ s_sendmsg sendmsg(MSG_GS, GS_OP_EMIT)
+ s_sendmsg sendmsg(MSG_GS, 2)
+ s_sendmsg sendmsg(MSG_GS_DONE, GS_OP_EMIT_CUT, 1)
+ s_sendmsg sendmsg(MSG_SYSMSG, SYSMSG_OP_TTRACE_PC)
+ s_sendmsg sendmsg(MSG_GET_DOORBELL)
+
+ // sendmsg with validation of value range only
+ msg = 2
+ op = 3
+ stream = 1
+ s_sendmsg sendmsg(msg, op, stream)
+ s_sendmsg sendmsg(2, GS_OP_CUT)
diff --git a/llvm/docs/AMDGPU/gfx940_opt_0d447d.rst b/llvm/docs/AMDGPU/gfx940_opt_0d447d.rst
new file mode 100644
index 0000000000000..eef6323915fda
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx940_opt_0d447d.rst
@@ -0,0 +1,13 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx940_opt_0d447d:
+
+opt
+===
+
+This is an optional operand. It must be used if and only if :ref:`lds<amdgpu_synid_lds>` is omitted.
diff --git a/llvm/docs/AMDGPU/gfx940_opt_7c211e.rst b/llvm/docs/AMDGPU/gfx940_opt_7c211e.rst
new file mode 100644
index 0000000000000..5865e678a0fd8
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx940_opt_7c211e.rst
@@ -0,0 +1,13 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx940_opt_7c211e:
+
+opt
+===
+
+This is an optional operand. It must be used if and only if :ref:`sc0<amdgpu_synid_sc0>` is specified.
diff --git a/llvm/docs/AMDGPU/gfx940_probe.rst b/llvm/docs/AMDGPU/gfx940_probe.rst
new file mode 100644
index 0000000000000..b5c2061e3cbcd
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx940_probe.rst
@@ -0,0 +1,24 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx940_probe:
+
+probe
+=====
+
+A bit mask which indicates request permissions.
+
+This operand must be specified as an :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`.
+The value is truncated to 7 bits, but only 3 low bits are significant.
+
+ ============ ==============================
+ Bit Number Description
+ ============ ==============================
+ 0 Request *read* permission.
+ 1 Request *write* permission.
+ 2 Request *execute* permission.
+ ============ ==============================
diff --git a/llvm/docs/AMDGPU/gfx940_saddr_22dbc1.rst b/llvm/docs/AMDGPU/gfx940_saddr_22dbc1.rst
new file mode 100644
index 0000000000000..b97ad24dd791b
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx940_saddr_22dbc1.rst
@@ -0,0 +1,19 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx940_saddr_22dbc1:
+
+saddr
+=====
+
+An optional 32-bit flat scratch offset. Must be specified as :ref:`off<amdgpu_synid_off>` if not used.
+
+* Offset = [:ref:`vaddr<amdgpu_synid_gfx940_vaddr_6ab80d>`] + [:ref:`saddr<amdgpu_synid_gfx940_saddr_22dbc1>`] + :ref:`offset13s<amdgpu_synid_flat_offset13s>`.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`off<amdgpu_synid_off>`
diff --git a/llvm/docs/AMDGPU/gfx940_saddr_a37373.rst b/llvm/docs/AMDGPU/gfx940_saddr_a37373.rst
new file mode 100644
index 0000000000000..75f28d3d4be4a
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx940_saddr_a37373.rst
@@ -0,0 +1,19 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx940_saddr_a37373:
+
+saddr
+=====
+
+An optional 64-bit flat global address. Must be specified as :ref:`off<amdgpu_synid_off>` if not used.
+
+See :ref:`vaddr<amdgpu_synid_gfx940_vaddr_0212e3>` for description of available addressing modes.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`off<amdgpu_synid_off>`
diff --git a/llvm/docs/AMDGPU/gfx940_sbase_010ce0.rst b/llvm/docs/AMDGPU/gfx940_sbase_010ce0.rst
new file mode 100644
index 0000000000000..38ba55b6713ee
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx940_sbase_010ce0.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx940_sbase_010ce0:
+
+sbase
+=====
+
+A 128-bit buffer resource constant for scalar memory operations which provides a base address, a size and a stride.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx940_sbase_044055.rst b/llvm/docs/AMDGPU/gfx940_sbase_044055.rst
new file mode 100644
index 0000000000000..7994cf169a508
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx940_sbase_044055.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx940_sbase_044055:
+
+sbase
+=====
+
+A 64-bit base address for scalar memory operations.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx940_sbase_0cd545.rst b/llvm/docs/AMDGPU/gfx940_sbase_0cd545.rst
new file mode 100644
index 0000000000000..42bfda6ea967f
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx940_sbase_0cd545.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx940_sbase_0cd545:
+
+sbase
+=====
+
+This operand is ignored by H/W and :ref:`flat_scratch<amdgpu_synid_flat_scratch>` is supplied instead.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx940_sdata_595c25.rst b/llvm/docs/AMDGPU/gfx940_sdata_595c25.rst
new file mode 100644
index 0000000000000..be7b69b053f82
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx940_sdata_595c25.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx940_sdata_595c25:
+
+sdata
+=====
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx940_sdata_7cbd60.rst b/llvm/docs/AMDGPU/gfx940_sdata_7cbd60.rst
new file mode 100644
index 0000000000000..835bf626acf9f
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx940_sdata_7cbd60.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx940_sdata_7cbd60:
+
+sdata
+=====
+
+Instruction input.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx940_sdata_aefe00.rst b/llvm/docs/AMDGPU/gfx940_sdata_aefe00.rst
new file mode 100644
index 0000000000000..ee9e6a86526e6
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx940_sdata_aefe00.rst
@@ -0,0 +1,21 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx940_sdata_aefe00:
+
+sdata
+=====
+
+Input data for an atomic instruction.
+
+Optionally may serve as an output data:
+
+* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx940_sdata_c6aec1.rst b/llvm/docs/AMDGPU/gfx940_sdata_c6aec1.rst
new file mode 100644
index 0000000000000..faf9818bec65e
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx940_sdata_c6aec1.rst
@@ -0,0 +1,21 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx940_sdata_c6aec1:
+
+sdata
+=====
+
+Input data for an atomic instruction.
+
+Optionally may serve as an output data:
+
+* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx940_sdata_e9f591.rst b/llvm/docs/AMDGPU/gfx940_sdata_e9f591.rst
new file mode 100644
index 0000000000000..b66886a63b6c3
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx940_sdata_e9f591.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx940_sdata_e9f591:
+
+sdata
+=====
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx940_sdata_eb6f2a.rst b/llvm/docs/AMDGPU/gfx940_sdata_eb6f2a.rst
new file mode 100644
index 0000000000000..a7b06c28c3036
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx940_sdata_eb6f2a.rst
@@ -0,0 +1,21 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx940_sdata_eb6f2a:
+
+sdata
+=====
+
+Input data for an atomic instruction.
+
+Optionally may serve as an output data:
+
+* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx940_sdst_06b266.rst b/llvm/docs/AMDGPU/gfx940_sdst_06b266.rst
new file mode 100644
index 0000000000000..6b05e20a09c23
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx940_sdst_06b266.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx940_sdst_06b266:
+
+sdst
+====
+
+Instruction output.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`
diff --git a/llvm/docs/AMDGPU/gfx940_sdst_0804b1.rst b/llvm/docs/AMDGPU/gfx940_sdst_0804b1.rst
new file mode 100644
index 0000000000000..e08e0d2a9c14f
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx940_sdst_0804b1.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx940_sdst_0804b1:
+
+sdst
+====
+
+Instruction output.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx940_sdst_362c37.rst b/llvm/docs/AMDGPU/gfx940_sdst_362c37.rst
new file mode 100644
index 0000000000000..64befcbd19f0d
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx940_sdst_362c37.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx940_sdst_362c37:
+
+sdst
+====
+
+Instruction output.
+
+*Size:* 8 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx940_sdst_3bc700.rst b/llvm/docs/AMDGPU/gfx940_sdst_3bc700.rst
new file mode 100644
index 0000000000000..cc7006d84f7e3
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx940_sdst_3bc700.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx940_sdst_3bc700:
+
+sdst
+====
+
+Instruction output.
+
+*Size:* 16 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx940_sdst_59204c.rst b/llvm/docs/AMDGPU/gfx940_sdst_59204c.rst
new file mode 100644
index 0000000000000..afbc0e3da71b7
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx940_sdst_59204c.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx940_sdst_59204c:
+
+sdst
+====
+
+Instruction output.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx940_sdst_718cc4.rst b/llvm/docs/AMDGPU/gfx940_sdst_718cc4.rst
new file mode 100644
index 0000000000000..4f4104edf7b65
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx940_sdst_718cc4.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx940_sdst_718cc4:
+
+sdst
+====
+
+Instruction output.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx940_sdst_94342d.rst b/llvm/docs/AMDGPU/gfx940_sdst_94342d.rst
new file mode 100644
index 0000000000000..5bf066ba1bd48
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx940_sdst_94342d.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx940_sdst_94342d:
+
+sdst
+====
+
+Instruction output.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx940_sdst_a319e6.rst b/llvm/docs/AMDGPU/gfx940_sdst_a319e6.rst
new file mode 100644
index 0000000000000..f502a1e9ee4b4
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx940_sdst_a319e6.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx940_sdst_a319e6:
+
+sdst
+====
+
+Instruction output.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`exec<amdgpu_synid_exec>`
diff --git a/llvm/docs/AMDGPU/gfx940_simm32_6f0844.rst b/llvm/docs/AMDGPU/gfx940_simm32_6f0844.rst
new file mode 100644
index 0000000000000..4b049cc85ab52
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx940_simm32_6f0844.rst
@@ -0,0 +1,14 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx940_simm32_6f0844:
+
+simm32
+======
+
+A :ref:`floating-point_number<amdgpu_synid_floating-point_number>`, an :ref:`integer_number<amdgpu_synid_integer_number>`, or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`.
+The value is converted to *f32* as described :ref:`here<amdgpu_synid_conv>`.
diff --git a/llvm/docs/AMDGPU/gfx940_simm32_a3e80c.rst b/llvm/docs/AMDGPU/gfx940_simm32_a3e80c.rst
new file mode 100644
index 0000000000000..e60446373b886
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx940_simm32_a3e80c.rst
@@ -0,0 +1,13 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx940_simm32_a3e80c:
+
+simm32
+======
+
+An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value is truncated to 32 bits.
diff --git a/llvm/docs/AMDGPU/gfx940_simm32_be0c1c.rst b/llvm/docs/AMDGPU/gfx940_simm32_be0c1c.rst
new file mode 100644
index 0000000000000..ea75a8f0055cf
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx940_simm32_be0c1c.rst
@@ -0,0 +1,14 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx940_simm32_be0c1c:
+
+simm32
+======
+
+A :ref:`floating-point_number<amdgpu_synid_floating-point_number>`, an :ref:`integer_number<amdgpu_synid_integer_number>`, or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`.
+The value is converted to *f16* as described :ref:`here<amdgpu_synid_conv>`.
diff --git a/llvm/docs/AMDGPU/gfx940_soffset_4318ca.rst b/llvm/docs/AMDGPU/gfx940_soffset_4318ca.rst
new file mode 100644
index 0000000000000..cb7d014f1bef5
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx940_soffset_4318ca.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx940_soffset_4318ca:
+
+soffset
+=======
+
+An unsigned byte offset.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`
diff --git a/llvm/docs/AMDGPU/gfx940_soffset_7b8c50.rst b/llvm/docs/AMDGPU/gfx940_soffset_7b8c50.rst
new file mode 100644
index 0000000000000..b76580d861b47
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx940_soffset_7b8c50.rst
@@ -0,0 +1,20 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx940_soffset_7b8c50:
+
+soffset
+=======
+
+An offset added to the base address to get memory address.
+
+* If offset is specified as a register, it supplies an unsigned byte offset.
+* If offset is specified as a 21-bit immediate, it supplies a signed byte offset.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`simm21<amdgpu_synid_simm21>`
diff --git a/llvm/docs/AMDGPU/gfx940_soffset_f33c5c.rst b/llvm/docs/AMDGPU/gfx940_soffset_f33c5c.rst
new file mode 100644
index 0000000000000..9a115009db6af
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx940_soffset_f33c5c.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx940_soffset_f33c5c:
+
+soffset
+=======
+
+An unsigned 20-bit offset added to the base address to get memory address.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`uimm20<amdgpu_synid_uimm20>`
diff --git a/llvm/docs/AMDGPU/gfx940_src_4de5c6.rst b/llvm/docs/AMDGPU/gfx940_src_4de5c6.rst
new file mode 100644
index 0000000000000..cb0bbb9577a3b
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx940_src_4de5c6.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx940_src_4de5c6:
+
+src
+===
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`iconst<amdgpu_synid_iconst>`, :ref:`ival<amdgpu_synid_ival>`, :ref:`literal<amdgpu_synid_literal>`
diff --git a/llvm/docs/AMDGPU/gfx940_src_56ed80.rst b/llvm/docs/AMDGPU/gfx940_src_56ed80.rst
new file mode 100644
index 0000000000000..292bedd3d418c
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx940_src_56ed80.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx940_src_56ed80:
+
+src
+===
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`
diff --git a/llvm/docs/AMDGPU/gfx940_src_64ea89.rst b/llvm/docs/AMDGPU/gfx940_src_64ea89.rst
new file mode 100644
index 0000000000000..cd4325949bfec
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx940_src_64ea89.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx940_src_64ea89:
+
+src
+===
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`, :ref:`iconst<amdgpu_synid_iconst>`, :ref:`fconst<amdgpu_synid_fconst>`
diff --git a/llvm/docs/AMDGPU/gfx940_src_6cfc4e.rst b/llvm/docs/AMDGPU/gfx940_src_6cfc4e.rst
new file mode 100644
index 0000000000000..518e17e65cefd
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx940_src_6cfc4e.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx940_src_6cfc4e:
+
+src
+===
+
+Instruction input.
+
+*Size:* 32 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`, :ref:`iconst<amdgpu_synid_iconst>`, :ref:`fconst<amdgpu_synid_fconst>`
diff --git a/llvm/docs/AMDGPU/gfx940_src_a578ba.rst b/llvm/docs/AMDGPU/gfx940_src_a578ba.rst
new file mode 100644
index 0000000000000..7a3e530db9e91
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx940_src_a578ba.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx940_src_a578ba:
+
+src
+===
+
+Instruction input.
+
+*Size:* 16 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`, :ref:`iconst<amdgpu_synid_iconst>`, :ref:`fconst<amdgpu_synid_fconst>`
diff --git a/llvm/docs/AMDGPU/gfx940_src_af08be.rst b/llvm/docs/AMDGPU/gfx940_src_af08be.rst
new file mode 100644
index 0000000000000..f80d885eee97c
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx940_src_af08be.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx940_src_af08be:
+
+src
+===
+
+Instruction input.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`, :ref:`iconst<amdgpu_synid_iconst>`, :ref:`fconst<amdgpu_synid_fconst>`
diff --git a/llvm/docs/AMDGPU/gfx940_src_d578c4.rst b/llvm/docs/AMDGPU/gfx940_src_d578c4.rst
new file mode 100644
index 0000000000000..1309bea4b8a43
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx940_src_d578c4.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx940_src_d578c4:
+
+src
+===
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`
diff --git a/llvm/docs/AMDGPU/gfx940_src_d95796.rst b/llvm/docs/AMDGPU/gfx940_src_d95796.rst
new file mode 100644
index 0000000000000..bac9554e63e82
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx940_src_d95796.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx940_src_d95796:
+
+src
+===
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`iconst<amdgpu_synid_iconst>`, :ref:`ival<amdgpu_synid_ival>`
diff --git a/llvm/docs/AMDGPU/gfx940_src_e1561c.rst b/llvm/docs/AMDGPU/gfx940_src_e1561c.rst
new file mode 100644
index 0000000000000..ae7b4682a56fc
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx940_src_e1561c.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx940_src_e1561c:
+
+src
+===
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`
diff --git a/llvm/docs/AMDGPU/gfx940_src_e5cc81.rst b/llvm/docs/AMDGPU/gfx940_src_e5cc81.rst
new file mode 100644
index 0000000000000..af1619656c9d3
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx940_src_e5cc81.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx940_src_e5cc81:
+
+src
+===
+
+Instruction input.
+
+*Size:* 8 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`, :ref:`iconst<amdgpu_synid_iconst>`, :ref:`fconst<amdgpu_synid_fconst>`
diff --git a/llvm/docs/AMDGPU/gfx940_src_f73668.rst b/llvm/docs/AMDGPU/gfx940_src_f73668.rst
new file mode 100644
index 0000000000000..31ab428fb8c45
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx940_src_f73668.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx940_src_f73668:
+
+src
+===
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`
diff --git a/llvm/docs/AMDGPU/gfx940_srsrc.rst b/llvm/docs/AMDGPU/gfx940_srsrc.rst
new file mode 100644
index 0000000000000..708f5272c2e77
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx940_srsrc.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx940_srsrc:
+
+srsrc
+=====
+
+Buffer resource constant which defines the address and characteristics of the buffer in memory.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx940_ssrc_4db4a9.rst b/llvm/docs/AMDGPU/gfx940_ssrc_4db4a9.rst
new file mode 100644
index 0000000000000..05ec538cd8ab0
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx940_ssrc_4db4a9.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx940_ssrc_4db4a9:
+
+ssrc
+====
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`
diff --git a/llvm/docs/AMDGPU/gfx940_ssrc_57838b.rst b/llvm/docs/AMDGPU/gfx940_ssrc_57838b.rst
new file mode 100644
index 0000000000000..fb1787d89be80
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx940_ssrc_57838b.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx940_ssrc_57838b:
+
+ssrc
+====
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`iconst<amdgpu_synid_iconst>`
diff --git a/llvm/docs/AMDGPU/gfx940_ssrc_595c25.rst b/llvm/docs/AMDGPU/gfx940_ssrc_595c25.rst
new file mode 100644
index 0000000000000..cefddc64d61ae
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx940_ssrc_595c25.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx940_ssrc_595c25:
+
+ssrc
+====
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx940_ssrc_65f041.rst b/llvm/docs/AMDGPU/gfx940_ssrc_65f041.rst
new file mode 100644
index 0000000000000..dea559d160124
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx940_ssrc_65f041.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx940_ssrc_65f041:
+
+ssrc
+====
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`exec<amdgpu_synid_exec>`
diff --git a/llvm/docs/AMDGPU/gfx940_ssrc_aee59c.rst b/llvm/docs/AMDGPU/gfx940_ssrc_aee59c.rst
new file mode 100644
index 0000000000000..22f7130c6e165
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx940_ssrc_aee59c.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx940_ssrc_aee59c:
+
+ssrc
+====
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`
diff --git a/llvm/docs/AMDGPU/gfx940_ssrc_c31902.rst b/llvm/docs/AMDGPU/gfx940_ssrc_c31902.rst
new file mode 100644
index 0000000000000..c33aec812372b
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx940_ssrc_c31902.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx940_ssrc_c31902:
+
+ssrc
+====
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`
diff --git a/llvm/docs/AMDGPU/gfx940_ssrc_c5d631.rst b/llvm/docs/AMDGPU/gfx940_ssrc_c5d631.rst
new file mode 100644
index 0000000000000..c7c436fa8500a
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx940_ssrc_c5d631.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx940_ssrc_c5d631:
+
+ssrc
+====
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`
diff --git a/llvm/docs/AMDGPU/gfx940_ssrc_c8a322.rst b/llvm/docs/AMDGPU/gfx940_ssrc_c8a322.rst
new file mode 100644
index 0000000000000..020a07a86b832
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx940_ssrc_c8a322.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx940_ssrc_c8a322:
+
+ssrc
+====
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`
diff --git a/llvm/docs/AMDGPU/gfx940_ssrc_e9f591.rst b/llvm/docs/AMDGPU/gfx940_ssrc_e9f591.rst
new file mode 100644
index 0000000000000..14138355393ae
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx940_ssrc_e9f591.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx940_ssrc_e9f591:
+
+ssrc
+====
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx940_type_deviation.rst b/llvm/docs/AMDGPU/gfx940_type_deviation.rst
new file mode 100644
index 0000000000000..95cac5f7d2dd2
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx940_type_deviation.rst
@@ -0,0 +1,13 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx940_type_deviation:
+
+Type Deviation
+==============
+
+*Type* of this operand
diff ers from *type* :ref:`implied by the opcode<amdgpu_syn_instruction_mnemo>`. This tag specifies actual operand *type*.
diff --git a/llvm/docs/AMDGPU/gfx940_vaddr_0212e3.rst b/llvm/docs/AMDGPU/gfx940_vaddr_0212e3.rst
new file mode 100644
index 0000000000000..828d62552ec3d
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx940_vaddr_0212e3.rst
@@ -0,0 +1,20 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx940_vaddr_0212e3:
+
+vaddr
+=====
+
+A 64-bit flat global address or a 32-bit offset depending on addressing mode:
+
+* Address = :ref:`vaddr<amdgpu_synid_gfx940_vaddr_0212e3>` + :ref:`offset13s<amdgpu_synid_flat_offset13s>`. :ref:`vaddr<amdgpu_synid_gfx940_vaddr_0212e3>` is a 64-bit address. This mode is indicated by :ref:`saddr<amdgpu_synid_gfx940_saddr_a37373>` set to :ref:`off<amdgpu_synid_off>`.
+* Address = :ref:`saddr<amdgpu_synid_gfx940_saddr_a37373>` + :ref:`vaddr<amdgpu_synid_gfx940_vaddr_0212e3>` + :ref:`offset13s<amdgpu_synid_flat_offset13s>`. :ref:`vaddr<amdgpu_synid_gfx940_vaddr_0212e3>` is a 32-bit offset. This mode is used when :ref:`saddr<amdgpu_synid_gfx940_saddr_a37373>` is not :ref:`off<amdgpu_synid_off>`.
+
+*Size:* 1 or 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx940_vaddr_6ab80d.rst b/llvm/docs/AMDGPU/gfx940_vaddr_6ab80d.rst
new file mode 100644
index 0000000000000..a4e400766164a
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx940_vaddr_6ab80d.rst
@@ -0,0 +1,19 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx940_vaddr_6ab80d:
+
+vaddr
+=====
+
+An optional 32-bit flat scratch offset. Must be specified as :ref:`off<amdgpu_synid_off>` if not used.
+
+* Offset = [:ref:`vaddr<amdgpu_synid_gfx940_vaddr_6ab80d>`] + [:ref:`saddr<amdgpu_synid_gfx940_saddr_22dbc1>`] + :ref:`offset13s<amdgpu_synid_flat_offset13s>`.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`off<amdgpu_synid_off>`
diff --git a/llvm/docs/AMDGPU/gfx940_vaddr_9f7133.rst b/llvm/docs/AMDGPU/gfx940_vaddr_9f7133.rst
new file mode 100644
index 0000000000000..b021672df12cf
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx940_vaddr_9f7133.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx940_vaddr_9f7133:
+
+vaddr
+=====
+
+A 64-bit flat address.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx940_vaddr_b73dc0.rst b/llvm/docs/AMDGPU/gfx940_vaddr_b73dc0.rst
new file mode 100644
index 0000000000000..2d307e721a36f
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx940_vaddr_b73dc0.rst
@@ -0,0 +1,22 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx940_vaddr_b73dc0:
+
+vaddr
+=====
+
+This is an optional operand which may specify offset and/or index.
+
+*Size:* 0, 1 or 2 dwords. Size is controlled by modifiers :ref:`offen<amdgpu_synid_offen>` and :ref:`idxen<amdgpu_synid_idxen>`:
+
+* If only :ref:`idxen<amdgpu_synid_idxen>` is specified, this operand supplies an index. Size is 1 dword.
+* If only :ref:`offen<amdgpu_synid_offen>` is specified, this operand supplies an offset. Size is 1 dword.
+* If both modifiers are specified, index is in the first register and offset is in the second. Size is 2 dwords.
+* If none of these modifiers are specified, this operand must be set to :ref:`off<amdgpu_synid_off>`.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`off<amdgpu_synid_off>`
diff --git a/llvm/docs/AMDGPU/gfx940_vaddr_f20ee4.rst b/llvm/docs/AMDGPU/gfx940_vaddr_f20ee4.rst
new file mode 100644
index 0000000000000..94901560132c3
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx940_vaddr_f20ee4.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx940_vaddr_f20ee4:
+
+vaddr
+=====
+
+An offset from the start of GDS/LDS memory.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx940_vcc.rst b/llvm/docs/AMDGPU/gfx940_vcc.rst
new file mode 100644
index 0000000000000..b82480731d30b
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx940_vcc.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx940_vcc:
+
+vcc
+===
+
+Vector condition code.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`vcc<amdgpu_synid_vcc>`
diff --git a/llvm/docs/AMDGPU/gfx940_vdata0_9ad749.rst b/llvm/docs/AMDGPU/gfx940_vdata0_9ad749.rst
new file mode 100644
index 0000000000000..64cb5c6a64e87
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx940_vdata0_9ad749.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx940_vdata0_9ad749:
+
+vdata0
+======
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx940_vdata0_be4895.rst b/llvm/docs/AMDGPU/gfx940_vdata0_be4895.rst
new file mode 100644
index 0000000000000..763545c830c1e
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx940_vdata0_be4895.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx940_vdata0_be4895:
+
+vdata0
+======
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx940_vdata1_9ad749.rst b/llvm/docs/AMDGPU/gfx940_vdata1_9ad749.rst
new file mode 100644
index 0000000000000..1d5cfe2b100b0
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx940_vdata1_9ad749.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx940_vdata1_9ad749:
+
+vdata1
+======
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx940_vdata1_be4895.rst b/llvm/docs/AMDGPU/gfx940_vdata1_be4895.rst
new file mode 100644
index 0000000000000..68f12481c6158
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx940_vdata1_be4895.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx940_vdata1_be4895:
+
+vdata1
+======
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx940_vdata_24882b.rst b/llvm/docs/AMDGPU/gfx940_vdata_24882b.rst
new file mode 100644
index 0000000000000..f549d27e3fd3d
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx940_vdata_24882b.rst
@@ -0,0 +1,21 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx940_vdata_24882b:
+
+vdata
+=====
+
+Input data for an atomic instruction.
+
+Optionally may serve as an output data:
+
+* If :ref:`sc0<amdgpu_synid_sc0>` is specified, gets the memory value before the operation.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx940_vdata_5eef12.rst b/llvm/docs/AMDGPU/gfx940_vdata_5eef12.rst
new file mode 100644
index 0000000000000..279f4a2b52702
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx940_vdata_5eef12.rst
@@ -0,0 +1,21 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx940_vdata_5eef12:
+
+vdata
+=====
+
+Input data for an atomic instruction.
+
+Optionally may serve as an output data:
+
+* If :ref:`sc0<amdgpu_synid_sc0>` is specified, gets the memory value before the operation.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx940_vdata_848ff7.rst b/llvm/docs/AMDGPU/gfx940_vdata_848ff7.rst
new file mode 100644
index 0000000000000..31e8402d7ef9a
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx940_vdata_848ff7.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx940_vdata_848ff7:
+
+vdata
+=====
+
+Instruction input.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx940_vdata_9ad749.rst b/llvm/docs/AMDGPU/gfx940_vdata_9ad749.rst
new file mode 100644
index 0000000000000..145c24fc276f5
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx940_vdata_9ad749.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx940_vdata_9ad749:
+
+vdata
+=====
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx940_vdata_be4895.rst b/llvm/docs/AMDGPU/gfx940_vdata_be4895.rst
new file mode 100644
index 0000000000000..e907da7439cbe
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx940_vdata_be4895.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx940_vdata_be4895:
+
+vdata
+=====
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx940_vdata_c8a58b.rst b/llvm/docs/AMDGPU/gfx940_vdata_c8a58b.rst
new file mode 100644
index 0000000000000..46a39d7243880
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx940_vdata_c8a58b.rst
@@ -0,0 +1,21 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx940_vdata_c8a58b:
+
+vdata
+=====
+
+Input data for an atomic instruction.
+
+Optionally may serve as an output data:
+
+* If :ref:`sc0<amdgpu_synid_sc0>` is specified, gets the memory value before the operation.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx940_vdata_cfb402.rst b/llvm/docs/AMDGPU/gfx940_vdata_cfb402.rst
new file mode 100644
index 0000000000000..ed5a54cf72112
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx940_vdata_cfb402.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx940_vdata_cfb402:
+
+vdata
+=====
+
+Instruction input.
+
+*Size:* 3 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx940_vdst_08b5ba.rst b/llvm/docs/AMDGPU/gfx940_vdst_08b5ba.rst
new file mode 100644
index 0000000000000..ae0f3618795d6
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx940_vdst_08b5ba.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx940_vdst_08b5ba:
+
+vdst
+====
+
+Instruction output: data read from a memory buffer.
+
+*Size:* 4 dwords by default. :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx940_vdst_0c37de.rst b/llvm/docs/AMDGPU/gfx940_vdst_0c37de.rst
new file mode 100644
index 0000000000000..d1bdf9b86ff73
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx940_vdst_0c37de.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx940_vdst_0c37de:
+
+vdst
+====
+
+Instruction output: data read from a memory buffer.
+
+*Size:* 2 dwords by default. :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx940_vdst_0f48d1.rst b/llvm/docs/AMDGPU/gfx940_vdst_0f48d1.rst
new file mode 100644
index 0000000000000..221ef8bb3e4dd
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx940_vdst_0f48d1.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx940_vdst_0f48d1:
+
+vdst
+====
+
+Instruction output.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx940_vdst_180bef.rst b/llvm/docs/AMDGPU/gfx940_vdst_180bef.rst
new file mode 100644
index 0000000000000..f022ba745c200
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx940_vdst_180bef.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx940_vdst_180bef:
+
+vdst
+====
+
+Instruction output.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx940_vdst_260aca.rst b/llvm/docs/AMDGPU/gfx940_vdst_260aca.rst
new file mode 100644
index 0000000000000..147e562dc2f49
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx940_vdst_260aca.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx940_vdst_260aca:
+
+vdst
+====
+
+Instruction output.
+
+*Size:* 3 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx940_vdst_5258b4.rst b/llvm/docs/AMDGPU/gfx940_vdst_5258b4.rst
new file mode 100644
index 0000000000000..bd6c7b2520a91
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx940_vdst_5258b4.rst
@@ -0,0 +1,19 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx940_vdst_5258b4:
+
+vdst
+====
+
+Instruction output: data read from a memory buffer.
+
+This is an optional operand. It must be used if and only if :ref:`lds<amdgpu_synid_lds>` is omitted.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx940_vdst_56baf6.rst b/llvm/docs/AMDGPU/gfx940_vdst_56baf6.rst
new file mode 100644
index 0000000000000..a5e524aa2c565
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx940_vdst_56baf6.rst
@@ -0,0 +1,19 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx940_vdst_56baf6:
+
+vdst
+====
+
+Data returned by a 32-bit atomic flat instruction.
+
+This is an optional operand. It must be used if and only if :ref:`sc0<amdgpu_synid_sc0>` is specified.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx940_vdst_63b743.rst b/llvm/docs/AMDGPU/gfx940_vdst_63b743.rst
new file mode 100644
index 0000000000000..a53055b611334
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx940_vdst_63b743.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx940_vdst_63b743:
+
+vdst
+====
+
+Instruction output: data read from a memory buffer.
+
+*Size:* 3 dwords by default. :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx940_vdst_69a144.rst b/llvm/docs/AMDGPU/gfx940_vdst_69a144.rst
new file mode 100644
index 0000000000000..3f05fed7cd828
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx940_vdst_69a144.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx940_vdst_69a144:
+
+vdst
+====
+
+Instruction output.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx940_vdst_78dd0a.rst b/llvm/docs/AMDGPU/gfx940_vdst_78dd0a.rst
new file mode 100644
index 0000000000000..0614436a99760
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx940_vdst_78dd0a.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx940_vdst_78dd0a:
+
+vdst
+====
+
+Instruction output.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx940_vdst_89680f.rst b/llvm/docs/AMDGPU/gfx940_vdst_89680f.rst
new file mode 100644
index 0000000000000..f06d4f9016538
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx940_vdst_89680f.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx940_vdst_89680f:
+
+vdst
+====
+
+Instruction output.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx940_vdst_8c77d4.rst b/llvm/docs/AMDGPU/gfx940_vdst_8c77d4.rst
new file mode 100644
index 0000000000000..e9e560d4e3e73
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx940_vdst_8c77d4.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx940_vdst_8c77d4:
+
+vdst
+====
+
+Instruction output.
+
+*Size:* 32 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx940_vdst_a32035.rst b/llvm/docs/AMDGPU/gfx940_vdst_a32035.rst
new file mode 100644
index 0000000000000..fe107d21f000a
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx940_vdst_a32035.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx940_vdst_a32035:
+
+vdst
+====
+
+Instruction output: data read from a memory buffer.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx940_vdst_bce42a.rst b/llvm/docs/AMDGPU/gfx940_vdst_bce42a.rst
new file mode 100644
index 0000000000000..0df073d458bd9
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx940_vdst_bce42a.rst
@@ -0,0 +1,19 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx940_vdst_bce42a:
+
+vdst
+====
+
+Data returned by a 64-bit atomic flat instruction.
+
+This is an optional operand. It must be used if and only if :ref:`sc0<amdgpu_synid_sc0>` is specified.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx940_vdst_bdb32f.rst b/llvm/docs/AMDGPU/gfx940_vdst_bdb32f.rst
new file mode 100644
index 0000000000000..041977c02a4c7
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx940_vdst_bdb32f.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx940_vdst_bdb32f:
+
+vdst
+====
+
+Instruction output.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx940_vdst_c3d63a.rst b/llvm/docs/AMDGPU/gfx940_vdst_c3d63a.rst
new file mode 100644
index 0000000000000..7828fb14d50e6
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx940_vdst_c3d63a.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx940_vdst_c3d63a:
+
+vdst
+====
+
+Instruction output: data read from a memory buffer.
+
+*Size:* 1 dword by default. :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx940_vdst_c8d317.rst b/llvm/docs/AMDGPU/gfx940_vdst_c8d317.rst
new file mode 100644
index 0000000000000..b3cce6e25b02c
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx940_vdst_c8d317.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx940_vdst_c8d317:
+
+vdst
+====
+
+Instruction output.
+
+*Size:* 8 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx940_vdst_d0c0cb.rst b/llvm/docs/AMDGPU/gfx940_vdst_d0c0cb.rst
new file mode 100644
index 0000000000000..bccff9d884495
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx940_vdst_d0c0cb.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx940_vdst_d0c0cb:
+
+vdst
+====
+
+Instruction output: data read from a memory buffer.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx940_vdst_d6f4bd.rst b/llvm/docs/AMDGPU/gfx940_vdst_d6f4bd.rst
new file mode 100644
index 0000000000000..6d73d09de6b64
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx940_vdst_d6f4bd.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx940_vdst_d6f4bd:
+
+vdst
+====
+
+Instruction output.
+
+*Size:* 16 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx940_vdst_d8236e.rst b/llvm/docs/AMDGPU/gfx940_vdst_d8236e.rst
new file mode 100644
index 0000000000000..d600629fbfa7b
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx940_vdst_d8236e.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx940_vdst_d8236e:
+
+vdst
+====
+
+Instruction output: data read from a memory buffer.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx940_vdst_e2898f.rst b/llvm/docs/AMDGPU/gfx940_vdst_e2898f.rst
new file mode 100644
index 0000000000000..5c8e254d75651
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx940_vdst_e2898f.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx940_vdst_e2898f:
+
+vdst
+====
+
+Instruction output: data read from a memory buffer.
+
+*Size:* 3 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx940_vdst_fa7dbd.rst b/llvm/docs/AMDGPU/gfx940_vdst_fa7dbd.rst
new file mode 100644
index 0000000000000..96dc1e7503409
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx940_vdst_fa7dbd.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx940_vdst_fa7dbd:
+
+vdst
+====
+
+Instruction output.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx940_vsrc_1027ca.rst b/llvm/docs/AMDGPU/gfx940_vsrc_1027ca.rst
new file mode 100644
index 0000000000000..1f5f5e23c648d
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx940_vsrc_1027ca.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx940_vsrc_1027ca:
+
+vsrc
+====
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx940_vsrc_6802ce.rst b/llvm/docs/AMDGPU/gfx940_vsrc_6802ce.rst
new file mode 100644
index 0000000000000..c719c2503b9ec
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx940_vsrc_6802ce.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx940_vsrc_6802ce:
+
+vsrc
+====
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx940_vsrc_848ff7.rst b/llvm/docs/AMDGPU/gfx940_vsrc_848ff7.rst
new file mode 100644
index 0000000000000..8c390c62fbb48
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx940_vsrc_848ff7.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx940_vsrc_848ff7:
+
+vsrc
+====
+
+Instruction input.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx940_vsrc_9ad749.rst b/llvm/docs/AMDGPU/gfx940_vsrc_9ad749.rst
new file mode 100644
index 0000000000000..81f54012e6b79
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx940_vsrc_9ad749.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx940_vsrc_9ad749:
+
+vsrc
+====
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx940_vsrc_be4895.rst b/llvm/docs/AMDGPU/gfx940_vsrc_be4895.rst
new file mode 100644
index 0000000000000..6cdf3686d030c
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx940_vsrc_be4895.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx940_vsrc_be4895:
+
+vsrc
+====
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx940_vsrc_e016a1.rst b/llvm/docs/AMDGPU/gfx940_vsrc_e016a1.rst
new file mode 100644
index 0000000000000..a10534b0cb1c8
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx940_vsrc_e016a1.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx940_vsrc_e016a1:
+
+vsrc
+====
+
+Instruction input.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx940_vsrc_fd235e.rst b/llvm/docs/AMDGPU/gfx940_vsrc_fd235e.rst
new file mode 100644
index 0000000000000..92988838d6b82
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx940_vsrc_fd235e.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx940_vsrc_fd235e:
+
+vsrc
+====
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx940_waitcnt.rst b/llvm/docs/AMDGPU/gfx940_waitcnt.rst
new file mode 100644
index 0000000000000..de3bcc5627ae9
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx940_waitcnt.rst
@@ -0,0 +1,64 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx940_waitcnt:
+
+waitcnt
+=======
+
+Counts of outstanding instructions to wait for.
+
+The bits of this operand have the following meaning:
+
+ ========== ========= ================================================ ============
+ High Bits Low Bits Description Value Range
+ ========== ========= ================================================ ============
+ 15:14 3:0 VM_CNT: vector memory operations count. 0..63
+ \- 6:4 EXP_CNT: export count. 0..7
+ \- 11:8 LGKM_CNT: LDS, GDS, Constant and Message count. 0..15
+ ========== ========= ================================================ ============
+
+This operand may be specified as one of the following:
+
+* An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range 0..0xFFFF.
+* A combination of *vmcnt*, *expcnt*, *lgkmcnt* and other values described below.
+
+ ====================== ======================================================================
+ Syntax Description
+ ====================== ======================================================================
+ vmcnt(<*N*>) A VM_CNT value. *N* must not exceed the largest VM_CNT value.
+ expcnt(<*N*>) An EXP_CNT value. *N* must not exceed the largest EXP_CNT value.
+ lgkmcnt(<*N*>) An LGKM_CNT value. *N* must not exceed the largest LGKM_CNT value.
+ vmcnt_sat(<*N*>) A VM_CNT value computed as min(*N*, the largest VM_CNT value).
+ expcnt_sat(<*N*>) An EXP_CNT value computed as min(*N*, the largest EXP_CNT value).
+ lgkmcnt_sat(<*N*>) An LGKM_CNT value computed as min(*N*, the largest LGKM_CNT value).
+ ====================== ======================================================================
+
+These values may be specified in any order. Spaces, ampersands and commas may be used as optional separators.
+
+*N* is either an
+:ref:`integer number<amdgpu_synid_integer_number>` or an
+:ref:`absolute expression<amdgpu_synid_absolute_expression>`.
+
+Examples:
+
+.. parsed-literal::
+
+ vm_cnt = 1
+ exp_cnt = 2
+ lgkm_cnt = 3
+ cnt = vm_cnt | (exp_cnt << 4) | (lgkm_cnt << 8)
+
+ s_waitcnt cnt
+ s_waitcnt 1 | (2 << 4) | (3 << 8) // the same as above
+ s_waitcnt vmcnt(1) expcnt(2) lgkmcnt(3) // the same as above
+ s_waitcnt vmcnt(vm_cnt) expcnt(exp_cnt) lgkmcnt(lgkm_cnt) // the same as above
+
+ s_waitcnt vmcnt(1)
+ s_waitcnt expcnt(2) lgkmcnt(3)
+ s_waitcnt vmcnt(1), expcnt(2), lgkmcnt(3)
+ s_waitcnt vmcnt(1) & lgkmcnt_sat(100) & expcnt(2)
diff --git a/llvm/docs/AMDGPUModifierSyntax.rst b/llvm/docs/AMDGPUModifierSyntax.rst
index a39f13051c9a1..97e259517299a 100644
--- a/llvm/docs/AMDGPUModifierSyntax.rst
+++ b/llvm/docs/AMDGPUModifierSyntax.rst
@@ -364,6 +364,21 @@ nv
See a description :ref:`here<amdgpu_synid_nv>`.
+sc0
+~~~
+
+See a description :ref:`here<amdgpu_synid_sc0>`.
+
+sc1
+~~~
+
+See a description :ref:`here<amdgpu_synid_sc1>`.
+
+nt
+~~
+
+See a description :ref:`here<amdgpu_synid_nt>`.
+
MIMG Modifiers
--------------
@@ -658,6 +673,48 @@ See AMD documentation for details.
tfe Set tfe bit to 1.
======================================== ================================================
+.. _amdgpu_synid_sc0:
+
+sc0
+~~~
+
+For atomics, sc0 indicates that the atomic operation returns a value.
+For other opcodes is is used together with :ref:`sc1<amdgpu_synid_sc1>` to specify cache
+policy. See AMD documentation for details.
+
+ ======================================== ================================================
+ Syntax Description
+ ======================================== ================================================
+ sc0 Set sc0 bit to 1.
+ ======================================== ================================================
+
+.. _amdgpu_synid_sc1:
+
+sc1
+~~~
+
+This modifier is used together with :ref:`sc0<amdgpu_synid_sc0>` to specify cache
+policy.
+
+ ======================================== ================================================
+ Syntax Description
+ ======================================== ================================================
+ sc1 Set sc1 bit to 1.
+ ======================================== ================================================
+
+.. _amdgpu_synid_nt:
+
+nt
+~~
+
+Indicates an operation with non-temporal data.
+
+ ======================================== ================================================
+ Syntax Description
+ ======================================== ================================================
+ nt Set nt bit to 1.
+ ======================================== ================================================
+
MUBUF/MTBUF Modifiers
---------------------
@@ -1955,3 +2012,34 @@ Note: numeric value may be specified as either
an :ref:`integer number<amdgpu_synid_integer_number>` or
an :ref:`absolute expression<amdgpu_synid_absolute_expression>`.
+.. _amdgpu_synid_mfma_neg:
+
+neg
+~~~
+
+Indicates operands that must be negated before the operation.
+The number of values specified by this modifier must match the number of source
+operands. First value controls src0, second value controls src1 and so on.
+
+The value 0 indicates that the corresponding operand value is used unmodified,
+the value 1 indicates that the operand value must be negated before the operation.
+
+By default, operand values are used unmodified.
+
+This modifier is valid for floating point operands only.
+
+ =============================== ==================================================================
+ Syntax Description
+ =============================== ==================================================================
+ neg:[{0..1},{0..1},{0..1}] Select operands which must be negated before the operation.
+ =============================== ==================================================================
+
+Note: numeric values may be specified as either
+:ref:`integer numbers<amdgpu_synid_integer_number>` or
+:ref:`absolute expressions<amdgpu_synid_absolute_expression>`.
+
+Examples:
+
+.. parsed-literal::
+
+ neg:[0,1,1]
diff --git a/llvm/docs/AMDGPUUsage.rst b/llvm/docs/AMDGPUUsage.rst
index 2427df15e1f85..81dad6a487cce 100644
--- a/llvm/docs/AMDGPUUsage.rst
+++ b/llvm/docs/AMDGPUUsage.rst
@@ -16,6 +16,7 @@ User Guide for AMDGPU Backend
AMDGPU/AMDGPUAsmGFX906
AMDGPU/AMDGPUAsmGFX908
AMDGPU/AMDGPUAsmGFX90a
+ AMDGPU/AMDGPUAsmGFX940
AMDGPU/AMDGPUAsmGFX10
AMDGPU/AMDGPUAsmGFX1011
AMDGPU/AMDGPUAsmGFX1013
@@ -14242,8 +14243,14 @@ in this description.
:doc:`gfx909<AMDGPU/AMDGPUAsmGFX900>`
+ :doc:`gfx90c<AMDGPU/AMDGPUAsmGFX900>`
+
CDNA 1 :doc:`GFX9<AMDGPU/AMDGPUAsmGFX9>` :doc:`gfx908<AMDGPU/AMDGPUAsmGFX908>`
+
CDNA 2 :doc:`GFX9<AMDGPU/AMDGPUAsmGFX9>` :doc:`gfx90a<AMDGPU/AMDGPUAsmGFX90a>`
+
+ CDNA 3 :doc:`GFX9<AMDGPU/AMDGPUAsmGFX9>` :doc:`gfx940<AMDGPU/AMDGPUAsmGFX940>`
+
RDNA 1 :doc:`GFX10 RDNA1<AMDGPU/AMDGPUAsmGFX10>` :doc:`gfx1010<AMDGPU/AMDGPUAsmGFX10>`
:doc:`gfx1011<AMDGPU/AMDGPUAsmGFX1011>`
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