[PATCH] D125271: [riscv] Enable strict assertions in InsertVSETVLI data flow

LiqinWeng via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Tue May 31 02:08:30 PDT 2022


Miss_Grape added a comment.

In D125271#3545007 <https://reviews.llvm.org/D125271#3545007>, @pcwang-thead wrote:

> In D125271#3544963 <https://reviews.llvm.org/D125271#3544963>, @Miss_Grape wrote:
>
>> Form your IR,
>>
>>   call void @llvm.masked.scatter.v4f32.v4p0(<4 x float> zeroinitializer, <4 x ptr> %1, i32 0, <4 x i1> undef)
>>
>> I think this is not loop vectorization as scale-vector,set -mllvm -scalable-vectorization=off , may also core dump? Could you try it?
>
> Yes, it will cause core dump even with `-mllvm -scalable-vectorization=off`, but will not if we remove `-mllvm -riscv-v-vector-bits-max=128 -mllvm -riscv-v-vector-bits-min=128`.
> So, it seems that there are two problems here I guess:
>
> 1. Some loops can't be vectorized by scalable vectorization and fixed-width vectorization is took as a fallback.
> 2. There are some bugs in codes generated by fixed-width vectorization.

I Update the LLVM, 
command: clang --target=riscv64-unknown-elf --sysroot=$HOME/task/rvv/riscv64-unknown-elf --gcc-toolchain=$HOME/task/rvv -march=rv64gcv -O2 -mllvm -riscv-v-vector-bits-max=128 -mllvm -riscv-v-vector-bits-min=128 -mllvm -scalable-vectorization=on tsc.c dummy.c -lm -o test.o , But not core dump? Could you see what happend?


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