[PATCH] D126641: [RISCV] Pass OptLevel to `RISCVDAGToDAGISel` correctly

[Yueh-Ting (eop) Chen via Phabricator via llvm-commits]

eopXD updated this revision to Diff 432991.
eopXD added a comment.

Rebase and show bug fix.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D126641/new/

https://reviews.llvm.org/D126641

Files:
  llvm/lib/Target/RISCV/RISCV.h
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
  llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
  llvm/test/CodeGen/RISCV/isel-optnone.ll


Index: llvm/test/CodeGen/RISCV/isel-optnone.ll
===================================================================
--- llvm/test/CodeGen/RISCV/isel-optnone.ll
+++ llvm/test/CodeGen/RISCV/isel-optnone.ll
@@ -2,11 +2,9 @@
 ; RUN: llc < %s -O0 -mtriple=riscv64 -debug-only=isel 2>&1 | FileCheck %s
 
 define i32* @fooOptnone(i32* %p, i32* %q, i32** %z) #0 {
-; CHECK: Changing optimization level for Function fooOptnone
-; CHECL: Before: -O2 ; After: -O0
+; CHECK-NOT: Changing optimization level for Function fooOptnone
+; CHECK-NOT: Restoring optimization level for Function fooOptnone
 
-; CHECK: Restoring optimization level for Function fooOptnone
-; CHECK: Before: -O0 ; After: -O2
 entry:
   %r = load i32, i32* %p
   %s = load i32, i32* %q
Index: llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+++ llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
@@ -182,7 +182,7 @@
 }
 
 bool RISCVPassConfig::addInstSelector() {
-  addPass(createRISCVISelDag(getRISCVTargetMachine()));
+  addPass(createRISCVISelDag(getRISCVTargetMachine(), getOptLevel()));
 
   return false;
 }
Index: llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
===================================================================
--- llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
+++ llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
@@ -24,8 +24,9 @@
   const RISCVSubtarget *Subtarget = nullptr;
 
 public:
-  explicit RISCVDAGToDAGISel(RISCVTargetMachine &TargetMachine)
-      : SelectionDAGISel(TargetMachine) {}
+  explicit RISCVDAGToDAGISel(RISCVTargetMachine &TargetMachine,
+                             CodeGenOpt::Level OptLevel)
+      : SelectionDAGISel(TargetMachine, OptLevel) {}
 
   StringRef getPassName() const override {
     return "RISCV DAG->DAG Pattern Instruction Selection";
Index: llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -2436,6 +2436,7 @@
 
 // This pass converts a legalized DAG into a RISCV-specific DAG, ready
 // for instruction scheduling.
-FunctionPass *llvm::createRISCVISelDag(RISCVTargetMachine &TM) {
-  return new RISCVDAGToDAGISel(TM);
+FunctionPass *llvm::createRISCVISelDag(RISCVTargetMachine &TM,
+                                       CodeGenOpt::Level OptLevel) {
+  return new RISCVDAGToDAGISel(TM, OptLevel);
 }
Index: llvm/lib/Target/RISCV/RISCV.h
===================================================================
--- llvm/lib/Target/RISCV/RISCV.h
+++ llvm/lib/Target/RISCV/RISCV.h
@@ -35,7 +35,8 @@
 bool lowerRISCVMachineOperandToMCOperand(const MachineOperand &MO,
                                          MCOperand &MCOp, const AsmPrinter &AP);
 
-FunctionPass *createRISCVISelDag(RISCVTargetMachine &TM);
+FunctionPass *createRISCVISelDag(RISCVTargetMachine &TM,
+                                 CodeGenOpt::Level OptLevel);
 
 FunctionPass *createRISCVMakeCompressibleOptPass();
 void initializeRISCVMakeCompressibleOptPass(PassRegistry &);


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