[llvm] b7d2b16 - [VPlan] Add test for printing VPlan for outer loop vectorization.

[Florian Hahn via llvm-commits]

Author: Florian Hahn
Date: 2022-05-30T18:19:52+01:00
New Revision: b7d2b160c3ba85c42427d5db96e0af01a0a9d1b5

URL: https://github.com/llvm/llvm-project/commit/b7d2b160c3ba85c42427d5db96e0af01a0a9d1b5
DIFF: https://github.com/llvm/llvm-project/commit/b7d2b160c3ba85c42427d5db96e0af01a0a9d1b5.diff

LOG: [VPlan] Add test for printing VPlan for outer loop vectorization.

Test coverage for D123005.

Added: 
    llvm/test/Transforms/LoopVectorize/vplan-printing-outer-loop.ll

Modified: 
    

Removed: 
    


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diff  --git a/llvm/test/Transforms/LoopVectorize/vplan-printing-outer-loop.ll b/llvm/test/Transforms/LoopVectorize/vplan-printing-outer-loop.ll
new file mode 100644
index 000000000000..038b15700cf1
--- /dev/null
+++ b/llvm/test/Transforms/LoopVectorize/vplan-printing-outer-loop.ll
@@ -0,0 +1,72 @@
+; REQUIRES: asserts
+
+; RUN: opt -loop-vectorize -enable-vplan-native-path -debug -disable-output %s 2>&1 | FileCheck %s
+
+ at arr2 = external global [8 x i64], align 16
+ at arr = external global [8 x [8 x i64]], align 16
+
+define void @foo(i64 %n) {
+; CHECK:      VPlan 'HCFGBuilder: Plain CFG
+; CHECK-NEXT: {
+; CHECK-NEXT: <x1> TopRegion: {
+; CHECK-NEXT:   entry:
+; CHECK-NEXT:   Successor(s): vector.body
+; CHECK-EMPTY:
+; CHECK-NEXT:   vector.body:
+; CHECK-NEXT:     WIDEN-PHI ir<%outer.iv> = phi ir<0>, ir<%outer.iv.next>
+; CHECK-NEXT:     EMIT ir<%gep.1> = getelementptr ir<@arr2> ir<0> ir<%outer.iv>
+; CHECK-NEXT:     EMIT store ir<%outer.iv> ir<%gep.1>
+; CHECK-NEXT:     EMIT ir<%add> = add ir<%outer.iv> ir<%n>
+; CHECK-NEXT:   Successor(s): inner
+; CHECK-EMPTY:
+; CHECK-NEXT:   inner:
+; CHECK-NEXT:     WIDEN-PHI ir<%inner.iv> = phi ir<0>, ir<%inner.iv.next>
+; CHECK-NEXT:     EMIT ir<%gep.2> = getelementptr ir<@arr> ir<0> ir<%inner.iv> ir<%outer.iv>
+; CHECK-NEXT:     EMIT store ir<%add> ir<%gep.2>
+; CHECK-NEXT:     EMIT ir<%inner.iv.next> = add ir<%inner.iv> ir<1>
+; CHECK-NEXT:     EMIT ir<%inner.ec> = icmp ir<%inner.iv.next> ir<8>
+; CHECK-NEXT:   Successor(s): outer.latch, inner
+; CHECK-NEXT:   CondBit: ir<%inner.ec> (inner)
+; CHECK-EMPTY:
+; CHECK-NEXT:   outer.latch:
+; CHECK-NEXT:     EMIT ir<%outer.iv.next> = add ir<%outer.iv> ir<1>
+; CHECK-NEXT:     EMIT ir<%outer.ec> = icmp ir<%outer.iv.next> ir<8>
+; CHECK-NEXT:   Successor(s): exit, vector.body
+; CHECK-NEXT:   CondBit: ir<%outer.ec> (outer.latch)
+; CHECK-EMPTY:
+; CHECK-NEXT:   exit:
+; CHECK-NEXT:     EMIT ret
+; CHECK-NEXT:   No successors
+; CHECK-NEXT: }
+; CHECK-NEXT: No successors
+; CHECK-NEXT: }
+entry:
+  br label %outer.header
+
+outer.header:
+  %outer.iv = phi i64 [ 0, %entry ], [ %outer.iv.next, %outer.latch ]
+  %gep.1 = getelementptr inbounds [8 x i64], [8 x i64]* @arr2, i64 0, i64 %outer.iv
+  store i64 %outer.iv, i64* %gep.1, align 4
+  %add = add nsw i64 %outer.iv, %n
+  br label %inner
+
+inner:
+  %inner.iv = phi i64 [ 0, %outer.header ], [ %inner.iv.next, %inner ]
+  %gep.2 = getelementptr inbounds [8 x [8 x i64]], [8 x [8 x i64]]* @arr, i64 0, i64 %inner.iv, i64 %outer.iv
+  store i64 %add, i64* %gep.2, align 4
+  %inner.iv.next = add nuw nsw i64 %inner.iv, 1
+  %inner.ec = icmp eq i64 %inner.iv.next, 8
+  br i1 %inner.ec, label %outer.latch, label %inner
+
+outer.latch:
+  %outer.iv.next = add nuw nsw i64 %outer.iv, 1
+  %outer.ec = icmp eq i64 %outer.iv.next, 8
+  br i1 %outer.ec, label %exit, label %outer.header, !llvm.loop !1
+
+exit:
+  ret void
+}
+
+!1 = distinct !{!1, !2, !3}
+!2 = !{!"llvm.loop.vectorize.width", i32 4}
+!3 = !{!"llvm.loop.vectorize.enable", i1 true}