[PATCH] D126652: [RISCV] Change GPRPF64's hwmode and spill alignment

[luxufan via Phabricator via llvm-commits]

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GPRPF64 is only available when zdinx enabled on RV32.
GPRPF64 is composed of two GPR register, therefore the
spill alignment value should be consistent with GPR,
which is 32 bits in RV32.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D126652

Files:
  llvm/lib/Target/RISCV/RISCVRegisterInfo.td


Index: llvm/lib/Target/RISCV/RISCVRegisterInfo.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVRegisterInfo.td
+++ llvm/lib/Target/RISCV/RISCVRegisterInfo.td
@@ -560,8 +560,8 @@
   }
 }
 
-let RegInfos = RegInfoByHwMode<[RV64], [RegInfo<64, 64, 64>]> in
-def GPRPF64 : RegisterClass<"RISCV", [f64], 64, (add
+let RegInfos = RegInfoByHwMode<[RV32], [RegInfo<64, 64, 32>]> in
+def GPRPF64 : RegisterClass<"RISCV", [f64], 32, (add
     X10_PD, X12_PD, X14_PD, X16_PD,
     X6_PD,
     X28_PD, X30_PD,


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