[PATCH] D126632: [AArch64] Look through copy in MachineCombiner FMUL patterns.
Dave Green via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon May 30 00:20:43 PDT 2022
dmgreen created this revision.
dmgreen added reviewers: SjoerdMeijer, asavonic, fhahn, jaykang10.
Herald added subscribers: hiraditya, kristof.beyls.
Herald added a project: All.
dmgreen requested review of this revision.
Herald added a project: LLVM.
This is a small addition to D99662 <https://reviews.llvm.org/D99662>, which added machine combiner patterns for `FMUL(DUP(..))`. Due to the way these are generated from ISel, they may also be `FMUL(COPY(DUP(..)))`, which this patch now ignores.
https://reviews.llvm.org/D126632
Files:
llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
llvm/test/CodeGen/AArch64/machine-combiner-copy.ll
llvm/test/CodeGen/AArch64/machine-combiner-fmul-dup.mir
Index: llvm/test/CodeGen/AArch64/machine-combiner-fmul-dup.mir
===================================================================
--- llvm/test/CodeGen/AArch64/machine-combiner-fmul-dup.mir
+++ llvm/test/CodeGen/AArch64/machine-combiner-fmul-dup.mir
@@ -588,12 +588,12 @@
; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY3]], %subreg.dsub
; CHECK-NEXT: [[COPY4:%[0-9]+]]:fpr64 = COPY [[COPY1]]
; CHECK-NEXT: [[COPY5:%[0-9]+]]:fpr64 = COPY [[COPY2]]
- ; CHECK-NEXT: [[DUPv2i32lane:%[0-9]+]]:fpr64 = DUPv2i32lane killed [[INSERT_SUBREG]], 0
+ ; CHECK-NEXT: [[DUPv2i32lane:%[0-9]+]]:fpr64 = DUPv2i32lane [[INSERT_SUBREG]], 0
; CHECK-NEXT: [[COPY6:%[0-9]+]]:fpr64 = COPY [[DUPv2i32lane]]
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
- ; CHECK-NEXT: [[FMULv2f32_:%[0-9]+]]:fpr64 = FMULv2f32 [[COPY5]], [[COPY6]]
- ; CHECK-NEXT: [[FADDv2f32_:%[0-9]+]]:fpr64 = FADDv2f32 killed [[FMULv2f32_]], [[COPY4]]
+ ; CHECK-NEXT: [[FMULv2i32_indexed:%[0-9]+]]:fpr64 = FMULv2i32_indexed [[COPY5]], [[INSERT_SUBREG]], 0
+ ; CHECK-NEXT: [[FADDv2f32_:%[0-9]+]]:fpr64 = FADDv2f32 killed [[FMULv2i32_indexed]], [[COPY4]]
; CHECK-NEXT: STRDui killed [[FADDv2f32_]], [[COPY]], 0 :: (store (s64), align 16)
; CHECK-NEXT: B %bb.1
bb.0:
Index: llvm/test/CodeGen/AArch64/machine-combiner-copy.ll
===================================================================
--- llvm/test/CodeGen/AArch64/machine-combiner-copy.ll
+++ llvm/test/CodeGen/AArch64/machine-combiner-copy.ll
@@ -18,16 +18,15 @@
; CHECK-NEXT: add x10, x1, #16
; CHECK-NEXT: add x11, x0, #16
; CHECK-NEXT: mov x12, x9
-; CHECK-NEXT: dup v1.8h, v0.h[0]
; CHECK-NEXT: .LBB0_4: // %vector.body
; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: ldp q2, q3, [x11, #-16]
+; CHECK-NEXT: ldp q1, q2, [x11, #-16]
; CHECK-NEXT: subs x12, x12, #16
; CHECK-NEXT: add x11, x11, #32
-; CHECK-NEXT: ldp q4, q5, [x10, #-16]
-; CHECK-NEXT: fmla v4.8h, v2.8h, v1.8h
-; CHECK-NEXT: fmla v5.8h, v3.8h, v0.h[0]
-; CHECK-NEXT: stp q4, q5, [x10, #-16]
+; CHECK-NEXT: ldp q3, q4, [x10, #-16]
+; CHECK-NEXT: fmla v3.8h, v1.8h, v0.h[0]
+; CHECK-NEXT: fmla v4.8h, v2.8h, v0.h[0]
+; CHECK-NEXT: stp q3, q4, [x10, #-16]
; CHECK-NEXT: add x10, x10, #32
; CHECK-NEXT: b.ne .LBB0_4
; CHECK-NEXT: // %bb.5: // %middle.block
Index: llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+++ llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -5170,6 +5170,9 @@
MachineInstr *MI = nullptr;
if (MO.isReg() && Register::isVirtualRegister(MO.getReg()))
MI = MRI.getUniqueVRegDef(MO.getReg());
+ if (MI && MI->getOpcode() == TargetOpcode::COPY &&
+ MI->getOperand(1).getReg().isVirtual())
+ MI = MRI.getUniqueVRegDef(MI->getOperand(1).getReg());
if (MI && MI->getOpcode() == Opcode) {
Patterns.push_back(Pattern);
return true;
@@ -5441,6 +5444,9 @@
MachineInstr *Dup =
MF.getRegInfo().getUniqueVRegDef(Root.getOperand(IdxDupOp).getReg());
+ if (Dup->getOpcode() == TargetOpcode::COPY)
+ Dup = MRI.getUniqueVRegDef(Dup->getOperand(1).getReg());
+
Register DupSrcReg = Dup->getOperand(1).getReg();
MRI.clearKillFlags(DupSrcReg);
MRI.constrainRegClass(DupSrcReg, RC);
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