[PATCH] D126624: [DAGCombine][NFC] Add braces to 'else' to match braced 'if'
Pretty-box via Phabricator via llvm-commits
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Sun May 29 20:07:50 PDT 2022
Pretty-box created this revision.
Pretty-box added reviewers: frasercrmck, benshi001.
Pretty-box added projects: All, LLVM.
Herald added subscribers: ecnelises, hiraditya.
Pretty-box requested review of this revision.
Herald added a subscriber: llvm-commits.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D126624
Files:
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -2094,8 +2094,9 @@
return false;
VT = ST->getMemoryVT();
AS = ST->getAddressSpace();
- } else
+ } else {
return false;
+ }
TargetLowering::AddrMode AM;
if (N->getOpcode() == ISD::ADD) {
@@ -2116,8 +2117,9 @@
else
// [reg +/- reg]
AM.Scale = 1;
- } else
+ } else {
return false;
+ }
return TLI.isLegalAddressingMode(DAG.getDataLayout(), AM,
VT.getTypeForEVT(*DAG.getContext()), AS);
@@ -6712,8 +6714,9 @@
if (!(isBSwapHWordElement(N01, Parts) && isBSwapHWordPair(N00, Parts)) &&
!(isBSwapHWordElement(N00, Parts) && isBSwapHWordPair(N01, Parts)))
return SDValue();
- } else
+ } else {
return SDValue();
+ }
// Make sure the parts are all coming from the same node.
if (Parts[0] != Parts[1] || Parts[0] != Parts[2] || Parts[0] != Parts[3])
@@ -7519,8 +7522,9 @@
SDValue RotX = DAG.getNode(ISD::ROTL, DL, VT, X, LHSShiftAmt);
SDValue SrlY = DAG.getNode(ISD::SRL, DL, VT, Y, RHSShiftAmt);
Res = DAG.getNode(ISD::OR, DL, VT, RotX, SrlY);
- } else
+ } else {
return SDValue();
+ }
return ApplyMasks(Res);
}
@@ -12649,8 +12653,9 @@
ActiveBits = Mask.countTrailingOnes();
} else if (Mask.isShiftedMask(ShAmt, ActiveBits)) {
HasShiftedOffset = true;
- } else
+ } else {
return SDValue();
+ }
ExtType = ISD::ZEXTLOAD;
ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits);
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