[PATCH] D125747: [RISCV] Enable scalable vectorization by default for RVV

[LiqinWeng via Phabricator via llvm-commits]

Miss_Grape added a comment.

In D125747#3542925 <https://reviews.llvm.org/D125747#3542925>, @reames wrote:

> In D125747#3542559 <https://reviews.llvm.org/D125747#3542559>, @craig.topper wrote:
>
>> In D125747#3541849 <https://reviews.llvm.org/D125747#3541849>, @Miss_Grape wrote:
>>
>>> In D125747#3518172 <https://reviews.llvm.org/D125747#3518172>, @craig.topper wrote:
>>>
>>>> Do you have any performance data?
>>>
>>> I use the TSCV test suit,  then run on the spike, 
>>> F23214515: image.png <https://reviews.llvm.org/F23214515>
>>>
>>> when option: -scalable-vectorization=on, the performance more better. But I'm not sure if the performance data from the spike run can be used as a standard to measure performance
>>
>> Better than specifying -riscv-v-vector-bits-min to match the machine width?
>
> @craig.topper I think this is somewhat the wrong question here.  While I agree that fixed length should be our eventual default for known vector lengths, we currently don't enable any vectorization.  If we can show either form of vectorization is generally profitable over the no-vectorization configuration, we should enable.  We can then evaluate the other configuration against that new baseline.
>
> @Miss_Grape I struggle to make out what that screenshot is conveying.  Could you summarize please?  Also, a text attachment is greatly preferred over images.



1. F23248688: TSVC.tar.gz <https://reviews.llvm.org/F23248688>，  TSVC Test suit cases，
2. Options：default -scalable-vectorization is off

1）clang --target=riscv64-unknown-elf --sysroot=$HOME/task/rvv/riscv64-unknown-elf --gcc-toolchain=$HOME/task/rvv --march=rv64gcv -O3 -mllvm -riscv-v-vector-bits-max=128 -mllvm -riscv-v-vector-bits-min=128 **-mllvm -scalable-vectorization=on** tsc.c dummy.c  -lm -o xxx
2）clang --target=riscv64-unknown-elf --sysroot=$HOME/task/rvv/riscv64-unknown-elf --gcc-toolchain=$HOME/task/rvv -march=rv64gcv -O3 -mllvm -riscv-v-vector-bits-max=128 -mllvm -riscv-v-vector-bits-min=128 tsc.c dummy.c  -lm -o xxx

3. down load riscv's pk and run the spike:

/home/wengliqin/task/rvv/bin/spike pk xxx, then you can get the  results shown in the following figure
F23248775: image.png <https://reviews.llvm.org/F23248775>


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