[PATCH] D126591: [InstCombine] Optimise shift+and+boolean conversion pattern to simple comparison

[chenglin.bi via Phabricator via llvm-commits]

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  iff (C1 is pow2) & (C2 is pow2) & (C1 <= C2):
  ((C1 << X) & C2) == 0 -> X != (Log2(C2) - Log2(C1)); https://alive2.llvm.org/ce/z/SVtcJM
  ((C1 << X) & C2) != 0 -> X == (Log2(C2) - Log2(C1)); https://alive2.llvm.org/ce/z/eLzTjS
  
  iff (C1 is pow2) & (C2 is pow2) & (C1 <= C2):
  ((C1 << X) & (C2 - 1)) == 0 -> X >= (Log2(C2) - Log2(C1)); https://alive2.llvm.org/ce/z/QHACBa
  ((C1 << X) & (C2 - 1)) != 0 -> X < (Log2(C2) - Log2(C1)); https://alive2.llvm.org/ce/z/xLdLWK
  
  iff (C1 is pow2) & (C2 is pow2):
  ((C1 >>u X) & C2) == 0 -> X != (Log2(C1) - Log2(C2)); https://alive2.llvm.org/ce/z/9p362A
  ((C1 >>u X) & C2) != 0 -> X == (Log2(C1) - Log2(C2)); https://alive2.llvm.org/ce/z/FsiU-A
  
  Fix issue https://github.com/llvm/llvm-project/issues/55739


https://reviews.llvm.org/D126591

Files:
  llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
  llvm/test/Transforms/InstCombine/icmp-and-shift.ll
  llvm/test/Transforms/InstCombine/lshr-and-signbit-icmpeq-zero.ll

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