[PATCH] D126563: [RISCV] Allow PRE of vsetvli involving non-1 LMUL

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll:4181
 ; CHECK-NEXT:    # =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    vsetvli zero, a3, e32, m8, ta, mu
 ; CHECK-NEXT:    vle32.v v8, (a0)
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I guess this didn't optimized because the amount was in a register?


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D126563/new/

https://reviews.llvm.org/D126563