[llvm] d4905a7 - [RISCV] Add a vsetvli PRE test involving non-1 LMUL

[Philip Reames via llvm-commits]

Author: Philip Reames
Date: 2022-05-27T13:16:05-07:00
New Revision: d4905a7b20b19383f84dd5249c9dae5325cb7305

URL: https://github.com/llvm/llvm-project/commit/d4905a7b20b19383f84dd5249c9dae5325cb7305
DIFF: https://github.com/llvm/llvm-project/commit/d4905a7b20b19383f84dd5249c9dae5325cb7305.diff

LOG: [RISCV] Add a vsetvli PRE test involving non-1 LMUL

Added: 
    

Modified: 
    llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll

Removed: 
    


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diff  --git a/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll
index b554b11a6ab88..ce8eabdfb4181 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll
@@ -832,6 +832,36 @@ fallthrough:
   ret <vscale x 4 x i32> %res
 }
 
+define <vscale x 2 x i32> @pre_lmul(<vscale x 2 x i32> %x, <vscale x 2 x i32> %y, i1 %cond) nounwind {
+; CHECK-LABEL: pre_lmul:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    andi a1, a0, 1
+; CHECK-NEXT:    vsetvli a0, zero, e64, m1, ta, mu
+; CHECK-NEXT:    vsetvli a2, zero, e32, m1, ta, mu
+; CHECK-NEXT:    vadd.vv v8, v8, v9
+; CHECK-NEXT:    beqz a1, .LBB18_2
+; CHECK-NEXT:  # %bb.1: # %if
+; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
+; CHECK-NEXT:  .LBB18_2: # %if.end
+; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, mu
+; CHECK-NEXT:    vadd.vv v8, v8, v9
+; CHECK-NEXT:    ret
+entry:
+  %vl = tail call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 0)
+  %a = call <vscale x 2 x i32> @llvm.riscv.vadd.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> %x, <vscale x 2 x i32> %y, i64 %vl)
+  br i1 %cond, label %if, label %if.end
+
+if:
+  ; Deliberately change vtype - this could be an unknown call, but the broader
+  ; code quality is distractingly bad
+  tail call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 1)
+  br label %if.end
+
+if.end:
+  %b = call <vscale x 2 x i32> @llvm.riscv.vadd.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> %a, <vscale x 2 x i32> %y, i64 %vl)
+  ret <vscale x 2 x i32> %b
+}
+
 declare i64 @llvm.riscv.vsetvlimax.i64(i64, i64)
 declare <vscale x 1 x double> @llvm.riscv.vle.nxv1f64.i64(<vscale x 1 x double>, <vscale x 1 x double>* nocapture, i64)
 declare <vscale x 1 x double> @llvm.riscv.vfadd.nxv1f64.nxv1f64.i64(<vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, i64)