[PATCH] D126562: [RISCV][WIP] Load/store relaxation

[Greg McGary via Phabricator via llvm-commits]

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Relax loads, stores, and address arithmetic for absolute, pc-relative, gp-relative
and tp-relative addressing.

[ Caveat: this diff still has some gaps in implementation and testing. ]

Depends on D125497 <https://reviews.llvm.org/D125497>


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D126562

Files:
  lld/ELF/Arch/RISCV.cpp
  lld/ELF/InputSection.cpp
  lld/ELF/InputSection.h
  lld/ELF/Relocations.h
  lld/test/ELF/riscv-gp.s
  lld/test/ELF/riscv-relax-hi20-lo12.s
  lld/test/ELF/riscv-relax-pcrel.s

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