[PATCH] D126558: [RISCV] Return false from isOffsetFoldingLegal instead of reversing the fold in lowering.
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri May 27 10:20:45 PDT 2022
craig.topper created this revision.
craig.topper added reviewers: reames, asb, luismarques, jrtc27.
Herald added subscribers: sunshaoce, VincentWu, luke957, StephenFan, vkmr, frasercrmck, evandro, apazos, sameer.abuasal, steven.zhang, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, shiva0217, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, hiraditya, arichardson.
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Herald added a project: LLVM.
When lowering GlobalAddressNodes, we were removing a non-zero offset and
creating a separate ADD.
It already comes out of SelectionDAGBuilder with a separate ADD. The
ADD was being removed by DAGCombiner.
This patch disables the DAG combine so we don't have to reverse it.
Test changes all look to be instruction order changes. Probably due
to different DAG node ordering.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D126558
Files:
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/lib/Target/RISCV/RISCVISelLowering.h
llvm/test/CodeGen/RISCV/double-mem.ll
llvm/test/CodeGen/RISCV/float-mem.ll
llvm/test/CodeGen/RISCV/half-mem.ll
llvm/test/CodeGen/RISCV/hoist-global-addr-base.ll
llvm/test/CodeGen/RISCV/loop-strength-reduce-add-cheaper-than-mul.ll
llvm/test/CodeGen/RISCV/loop-strength-reduce-loop-invar.ll
llvm/test/CodeGen/RISCV/mem.ll
llvm/test/CodeGen/RISCV/mem64.ll
llvm/test/CodeGen/RISCV/zext-with-load-is-free.ll
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