[PATCH] D116088: [compiler-rt] Implement ARM atomic operations for architectures without SMP support

[Pavel Kosov via Phabricator via llvm-commits]

kpdev42 updated this revision to Diff 432478.
kpdev42 edited the summary of this revision.
kpdev42 added a comment.

Well, after some investigation it turned out that:

1. ARMv5 has DMB instruction in the form of mcr p15, #0, <Rd>, c7, c10, #5
2. There is SWP instruction (deprecated on ARMv6), which does atomic exchange of 32-bit values

I've reimplemented sync ops using these primitves, PTAL
Theoretically this should work on ARMv6 and higher, though I didn't check this


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D116088/new/

https://reviews.llvm.org/D116088

Files:
  compiler-rt/cmake/Modules/CompilerRTUtils.cmake
  compiler-rt/cmake/config-ix.cmake
  compiler-rt/lib/builtins/CMakeLists.txt
  compiler-rt/lib/builtins/arm/sync-ops.h

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