[PATCH] D126516: [RISCV][NFC] Simplified code for integer promotion setcc/vp.setcc
Ben Shi via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu May 26 22:50:46 PDT 2022
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG121689a62e5b: [SelectionDAG][NFC] Simplify integer promotion in setcc/vp.setcc (authored by Pretty-box, committed by benshi001).
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D126516/new/
https://reviews.llvm.org/D126516
Files:
llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
@@ -1949,10 +1949,9 @@
PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(2))->get());
// The CC (#2) is always legal.
- if (N->getNumOperands() == 3)
+ if (N->getOpcode() == ISD::SETCC)
return SDValue(DAG.UpdateNodeOperands(N, LHS, RHS, N->getOperand(2)), 0);
- assert(N->getNumOperands() == 5 && "Unexpected number of operands!");
assert(N->getOpcode() == ISD::VP_SETCC && "Expected VP_SETCC opcode");
return SDValue(DAG.UpdateNodeOperands(N, LHS, RHS, N->getOperand(2),
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