[PATCH] D126519: [X86][AMX] Replace LDTILECFG with PLDTILECFGV on auto-config.

[LuoYuanke via Phabricator via llvm-commits]

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There is intrinsic `@llvm.x86.ldtilecfg` which is lowered to LDTILECFG.
This intrinsic is open for user to configure tile registers by
themselves. There is a chance that `@llvm.x86.ldtilecfg` would be mixed
with the new AMX intrinsics which depend on compiler to configure tile
registers. Separate pusedo instruction PLDTILECFGV would avoid
unexpected behavious when `@llvm.x86.ldtilecfg` is mixed with new AMX
intrinsics. Though user should not mix the two programming model,
compiler should avoid crash or UB when they are mixed.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D126519

Files:
  llvm/lib/Target/X86/X86FastPreTileConfig.cpp
  llvm/lib/Target/X86/X86FastTileConfig.cpp
  llvm/lib/Target/X86/X86InstrAMX.td
  llvm/lib/Target/X86/X86InstrInfo.cpp
  llvm/lib/Target/X86/X86PreTileConfig.cpp
  llvm/lib/Target/X86/X86TileConfig.cpp
  llvm/test/CodeGen/X86/AMX/amx-fastconfig-phi.mir
  llvm/test/CodeGen/X86/AMX/amx-fastconfig-phi2.mir
  llvm/test/CodeGen/X86/AMX/amx-fastconfig-phi4.mir
  llvm/test/CodeGen/X86/AMX/amx-fastconfig-spill.mir
  llvm/test/CodeGen/X86/AMX/amx-fastconfig.mir
  llvm/test/CodeGen/X86/AMX/amx-fastpreconfig.mir
  llvm/test/CodeGen/X86/AMX/amx-lower-tile-copy.ll
  llvm/test/CodeGen/X86/AMX/amx-spill-merge.ll
  llvm/test/CodeGen/X86/AMX/amx-tile-intrinsics.ll

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