[PATCH] D126400: [RISCV] Allow compatible VTYPE in AVL Reg Forward cases

[Fraser Cormack via Phabricator via llvm-commits]

frasercrmck accepted this revision.
frasercrmck added a comment.
This revision is now accepted and ready to land.

LGTM



================
Comment at: llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp:722
   // We didn't find a compatible value. If our AVL is a virtual register,
-  // it might be defined by a VSET(I)VLI. If it has the same VTYPE we need
+  // it might be defined by a VSET(I)VLI. If it has the same VLMAXE we need
   // and the last VL/VTYPE we observed is the same, we don't need a
----------------
VLMAXE -> VLMAX


================
Comment at: llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp:1242
 
-        // If AVL is defined by a vsetvli with the same vtype, we can
+        // If AVL is defined by a vsetvli with the same vlmax, we can
         // replace the AVL operand with the AVL of the defining vsetvli.
----------------
Maybe make this `vlmax` upper case for consistency while you're here?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D126400/new/

https://reviews.llvm.org/D126400