[PATCH] D126372: [RISCV]Add basic cost model for vector reduce for scalable vector

[Roger Ferrer Ibanez via Phabricator via llvm-commits]

rogfer01 added a comment.

Can we test some illegal type here (e.g. `vscale x 16 x i64`). The patch includes logic for that so it may be worth having it.



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Comment at: llvm/test/Analysis/CostModel/RISCV/scalable-reduce.ll:63
+;
+  %fadd_nxv4f32 = call float @llvm.vector.reduce.fadd.nxv4f32(float 0.0, <vscale x 4 x float> %v0)
+  %fadd_nxv4f64 = call double @llvm.vector.reduce.fadd.nxv4f64(double 0.0, <vscale x 4 x double> %v1)
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This doesn't seem very realistic (I assume these reductions must be done linearly) but I guess the cost here is measuring number of instructions required rather than latency, right?


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