[llvm] 1a51ab7 - [AMDGPU] gfx11 export instructions
Joe Nash via llvm-commits
llvm-commits at lists.llvm.org
Wed May 25 12:12:17 PDT 2022
Author: Joe Nash
Date: 2022-05-25T14:44:09-04:00
New Revision: 1a51ab766f471059abe6ae9123512d2137e2e0af
URL: https://github.com/llvm/llvm-project/commit/1a51ab766f471059abe6ae9123512d2137e2e0af
DIFF: https://github.com/llvm/llvm-project/commit/1a51ab766f471059abe6ae9123512d2137e2e0af.diff
LOG: [AMDGPU] gfx11 export instructions
Contributors:
Jay Foad <jay.foad at amd.com>
Dmitry Preobrazhensky <d-pre at mail.ru>
Patch 10/N for upstreaming of AMDGPU gfx11 architecture.
Depends on D125822
Reviewed By: dp
Differential Revision: https://reviews.llvm.org/D125824
Added:
llvm/test/MC/AMDGPU/exp-gfx11.s
llvm/test/MC/AMDGPU/exp-pregfx11.s
llvm/test/MC/Disassembler/AMDGPU/exp_gfx11.txt
Modified:
llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h
llvm/lib/Target/AMDGPU/EXPInstructions.td
llvm/lib/Target/AMDGPU/SIDefines.h
llvm/lib/Target/AMDGPU/SIInstrFormats.td
llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
llvm/lib/Target/AMDGPU/VIInstrFormats.td
llvm/test/MC/AMDGPU/exp-err.s
llvm/test/MC/AMDGPU/exp-gfx10.s
llvm/test/MC/AMDGPU/exp.s
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index e3cddd64a4a58..6f707cc4cfaff 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -6282,7 +6282,7 @@ void AMDGPUAsmParser::cvtExp(MCInst &Inst, const OperandVector &Operands) {
continue;
}
- if (Op.isToken() && Op.getToken() == "done")
+ if (Op.isToken() && (Op.getToken() == "done" || Op.getToken() == "row_en"))
continue;
// Handle optional arguments
diff --git a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
index a9540b14f1ad9..62aaa321f498a 100644
--- a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
+++ b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
@@ -604,6 +604,9 @@ DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
Res = convertMIMGInst(MI);
}
+ if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::EXP))
+ Res = convertEXPInst(MI);
+
if (Res && IsSDWA)
Res = convertSDWAInst(MI);
@@ -635,6 +638,16 @@ DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
return Res;
}
+DecodeStatus AMDGPUDisassembler::convertEXPInst(MCInst &MI) const {
+ if (STI.getFeatureBits()[AMDGPU::FeatureGFX11]) {
+ // The MCInst still has these fields even though they are no longer encoded
+ // in the GFX11 instruction.
+ insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::vm);
+ insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::compr);
+ }
+ return MCDisassembler::Success;
+}
+
DecodeStatus AMDGPUDisassembler::convertSDWAInst(MCInst &MI) const {
if (STI.getFeatureBits()[AMDGPU::FeatureGFX9] ||
STI.getFeatureBits()[AMDGPU::FeatureGFX10]) {
diff --git a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h
index 5e44fecf43c11..3d1ee29faa3a1 100644
--- a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h
+++ b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h
@@ -101,6 +101,7 @@ class AMDGPUDisassembler : public MCDisassembler {
DecodeStatus decodeCOMPUTE_PGM_RSRC2(uint32_t FourByteBuffer,
raw_string_ostream &KdStream) const;
+ DecodeStatus convertEXPInst(MCInst &MI) const;
DecodeStatus convertFMAanyK(MCInst &MI, int ImmLitIdx) const;
DecodeStatus convertSDWAInst(MCInst &MI) const;
DecodeStatus convertDPP8Inst(MCInst &MI) const;
diff --git a/llvm/lib/Target/AMDGPU/EXPInstructions.td b/llvm/lib/Target/AMDGPU/EXPInstructions.td
index 3654b8b623298..f8742a9ce2ff5 100644
--- a/llvm/lib/Target/AMDGPU/EXPInstructions.td
+++ b/llvm/lib/Target/AMDGPU/EXPInstructions.td
@@ -10,7 +10,7 @@
// EXP classes
//===----------------------------------------------------------------------===//
-class EXPCommon<bit done, string asm = ""> : InstSI<
+class EXPCommon<bit row, bit done, string asm = ""> : InstSI<
(outs),
(ins exp_tgt:$tgt,
ExpSrc0:$src0, ExpSrc1:$src1, ExpSrc2:$src2, ExpSrc3:$src3,
@@ -21,21 +21,30 @@ class EXPCommon<bit done, string asm = ""> : InstSI<
let mayLoad = done;
let mayStore = 1;
let UseNamedOperandTable = 1;
- let Uses = [EXEC];
+ let Uses = !if(row, [EXEC, M0], [EXEC]);
let SchedRW = [WriteExport];
let DisableWQM = 1;
}
-class EXP_Pseudo<bit done> : EXPCommon<done>,
- SIMCInstr <NAME, SIEncodingFamily.NONE> {
+class EXP_Pseudo<bit row, bit done>
+ : EXPCommon<row, done>, SIMCInstr<NAME, SIEncodingFamily.NONE> {
let isPseudo = 1;
let isCodeGenOnly = 1;
}
-class EXP_Real<bit done, string pseudo, int subtarget>
- : EXPCommon<done, "exp$tgt $src0, $src1, $src2, $src3"#!if(done, " done", "")
- #"$compr$vm">,
- SIMCInstr <pseudo, subtarget> {
+// Real instruction with optional asm operands "compr" and "vm".
+class EXP_Real_ComprVM<bit done, string pseudo, int subtarget>
+ : EXPCommon<0, done, "exp$tgt $src0, $src1, $src2, $src3"
+ #!if(done, " done", "")#"$compr$vm">,
+ SIMCInstr<pseudo, subtarget> {
+ let AsmMatchConverter = "cvtExp";
+}
+
+// Real instruction with optional asm operand "row_en".
+class EXP_Real_Row<bit row, bit done, string pseudo, int subtarget>
+ : EXPCommon<row, done, "exp$tgt $src0, $src1, $src2, $src3"
+ #!if(done, " done", "")#!if(row, " row_en", "")>,
+ SIMCInstr<pseudo, subtarget> {
let AsmMatchConverter = "cvtExp";
}
@@ -43,11 +52,13 @@ class EXP_Real<bit done, string pseudo, int subtarget>
// EXP Instructions
//===----------------------------------------------------------------------===//
-// Split EXP instruction into EXP and EXP_DONE so we can set
-// mayLoad for done=1.
+// DONE variants have mayLoad = 1.
+// ROW variants have an implicit use of M0.
let SubtargetPredicate = isNotGFX90APlus in {
-def EXP : EXP_Pseudo<0>;
-def EXP_DONE : EXP_Pseudo<1>;
+def EXP : EXP_Pseudo<0, 0>;
+def EXP_DONE : EXP_Pseudo<0, 1>;
+def EXP_ROW : EXP_Pseudo<1, 0>;
+def EXP_ROW_DONE : EXP_Pseudo<1, 1>;
} // let SubtargetPredicate = isNotGFX90APlus
//===----------------------------------------------------------------------===//
@@ -55,7 +66,7 @@ def EXP_DONE : EXP_Pseudo<1>;
//===----------------------------------------------------------------------===//
class EXP_Real_si<bit _done, string pseudo>
- : EXP_Real<_done, pseudo, SIEncodingFamily.SI>, EXPe {
+ : EXP_Real_ComprVM<_done, pseudo, SIEncodingFamily.SI>, EXPe_ComprVM {
let AssemblerPredicate = isGFX6GFX7;
let DecoderNamespace = "GFX6GFX7";
let done = _done;
@@ -69,7 +80,7 @@ def EXP_DONE_si : EXP_Real_si<1, "EXP_DONE">;
//===----------------------------------------------------------------------===//
class EXP_Real_vi<bit _done, string pseudo>
- : EXP_Real<_done, pseudo, SIEncodingFamily.VI>, EXPe_vi {
+ : EXP_Real_ComprVM<_done, pseudo, SIEncodingFamily.VI>, EXPe_vi {
let AssemblerPredicate = isGFX8GFX9;
let SubtargetPredicate = isNotGFX90APlus;
let DecoderNamespace = "GFX8";
@@ -80,12 +91,12 @@ def EXP_vi : EXP_Real_vi<0, "EXP">;
def EXP_DONE_vi : EXP_Real_vi<1, "EXP_DONE">;
//===----------------------------------------------------------------------===//
-// GFX10+
+// GFX10
//===----------------------------------------------------------------------===//
class EXP_Real_gfx10<bit _done, string pseudo>
- : EXP_Real<_done, pseudo, SIEncodingFamily.GFX10>, EXPe {
- let AssemblerPredicate = isGFX10Plus;
+ : EXP_Real_ComprVM<_done, pseudo, SIEncodingFamily.GFX10>, EXPe_ComprVM {
+ let AssemblerPredicate = isGFX10Only;
let DecoderNamespace = "GFX10";
let done = _done;
}
@@ -93,6 +104,23 @@ class EXP_Real_gfx10<bit _done, string pseudo>
def EXP_gfx10 : EXP_Real_gfx10<0, "EXP">;
def EXP_DONE_gfx10 : EXP_Real_gfx10<1, "EXP_DONE">;
+//===----------------------------------------------------------------------===//
+// GFX11+
+//===----------------------------------------------------------------------===//
+
+class EXP_Real_gfx11<bit _row, bit _done, string pseudo>
+ : EXP_Real_Row<_row, _done, pseudo, SIEncodingFamily.GFX11>, EXPe_Row {
+ let AssemblerPredicate = isGFX11Plus;
+ let DecoderNamespace = "GFX11";
+ let row = _row;
+ let done = _done;
+}
+
+def EXP_gfx11 : EXP_Real_gfx11<0, 0, "EXP">;
+def EXP_DONE_gfx11 : EXP_Real_gfx11<0, 1, "EXP_DONE">;
+def EXP_ROW_gfx11 : EXP_Real_gfx11<1, 0, "EXP_ROW">;
+def EXP_ROW_DONE_gfx11 : EXP_Real_gfx11<1, 1, "EXP_ROW_DONE">;
+
//===----------------------------------------------------------------------===//
// EXP Patterns
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/AMDGPU/SIDefines.h b/llvm/lib/Target/AMDGPU/SIDefines.h
index 80ac558955c51..07819f8475c28 100644
--- a/llvm/lib/Target/AMDGPU/SIDefines.h
+++ b/llvm/lib/Target/AMDGPU/SIDefines.h
@@ -852,20 +852,23 @@ enum Target : unsigned {
ET_MRT0 = 0,
ET_MRT7 = 7,
ET_MRTZ = 8,
- ET_NULL = 9,
+ ET_NULL = 9, // Pre-GFX11
ET_POS0 = 12,
ET_POS3 = 15,
- ET_POS4 = 16, // GFX10+
- ET_POS_LAST = ET_POS4, // Highest pos used on any subtarget
- ET_PRIM = 20, // GFX10+
- ET_PARAM0 = 32,
- ET_PARAM31 = 63,
+ ET_POS4 = 16, // GFX10+
+ ET_POS_LAST = ET_POS4, // Highest pos used on any subtarget
+ ET_PRIM = 20, // GFX10+
+ ET_DUAL_SRC_BLEND0 = 21, // GFX11+
+ ET_DUAL_SRC_BLEND1 = 22, // GFX11+
+ ET_PARAM0 = 32, // Pre-GFX11
+ ET_PARAM31 = 63, // Pre-GFX11
ET_NULL_MAX_IDX = 0,
ET_MRTZ_MAX_IDX = 0,
ET_PRIM_MAX_IDX = 0,
ET_MRT_MAX_IDX = 7,
ET_POS_MAX_IDX = 4,
+ ET_DUAL_SRC_BLEND_MAX_IDX = 1,
ET_PARAM_MAX_IDX = 31,
ET_INVALID = 255,
diff --git a/llvm/lib/Target/AMDGPU/SIInstrFormats.td b/llvm/lib/Target/AMDGPU/SIInstrFormats.td
index 838cd1e25523f..2fd1a0b60d1bf 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrFormats.td
+++ b/llvm/lib/Target/AMDGPU/SIInstrFormats.td
@@ -357,9 +357,7 @@ class MIMGe_gfx10 <bits<8> op> : MIMGe {
class EXPe : Enc64 {
bits<4> en;
bits<6> tgt;
- bits<1> compr;
bits<1> done;
- bits<1> vm;
bits<8> src0;
bits<8> src1;
bits<8> src2;
@@ -367,9 +365,7 @@ class EXPe : Enc64 {
let Inst{3-0} = en;
let Inst{9-4} = tgt;
- let Inst{10} = compr;
let Inst{11} = done;
- let Inst{12} = vm;
let Inst{31-26} = 0x3e;
let Inst{39-32} = src0;
let Inst{47-40} = src1;
@@ -377,6 +373,22 @@ class EXPe : Enc64 {
let Inst{63-56} = src3;
}
+// Pre-GFX11 encoding has compr and vm bits.
+class EXPe_ComprVM : EXPe {
+ bits<1> compr;
+ bits<1> vm;
+
+ let Inst{10} = compr;
+ let Inst{12} = vm;
+}
+
+// GFX11+ encoding has row bit.
+class EXPe_Row : EXPe {
+ bits<1> row;
+
+ let Inst{13} = row;
+}
+
let Uses = [EXEC] in {
class VINTRPCommon <dag outs, dag ins, string asm, list<dag> pattern> :
diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
index 9dae84d8c47a3..bc1abd7a58845 100644
--- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
@@ -1276,12 +1276,13 @@ struct ExpTgt {
};
static constexpr ExpTgt ExpTgtInfo[] = {
- {{"null"}, ET_NULL, ET_NULL_MAX_IDX},
- {{"mrtz"}, ET_MRTZ, ET_MRTZ_MAX_IDX},
- {{"prim"}, ET_PRIM, ET_PRIM_MAX_IDX},
- {{"mrt"}, ET_MRT0, ET_MRT_MAX_IDX},
- {{"pos"}, ET_POS0, ET_POS_MAX_IDX},
- {{"param"}, ET_PARAM0, ET_PARAM_MAX_IDX},
+ {{"null"}, ET_NULL, ET_NULL_MAX_IDX},
+ {{"mrtz"}, ET_MRTZ, ET_MRTZ_MAX_IDX},
+ {{"prim"}, ET_PRIM, ET_PRIM_MAX_IDX},
+ {{"mrt"}, ET_MRT0, ET_MRT_MAX_IDX},
+ {{"pos"}, ET_POS0, ET_POS_MAX_IDX},
+ {{"dual_src_blend"}, ET_DUAL_SRC_BLEND0, ET_DUAL_SRC_BLEND_MAX_IDX},
+ {{"param"}, ET_PARAM0, ET_PARAM_MAX_IDX},
};
bool getTgtName(unsigned Id, StringRef &Name, int &Index) {
@@ -1319,7 +1320,20 @@ unsigned getTgtId(const StringRef Name) {
}
bool isSupportedTgtId(unsigned Id, const MCSubtargetInfo &STI) {
- return (Id != ET_POS4 && Id != ET_PRIM) || isGFX10Plus(STI);
+ switch (Id) {
+ case ET_NULL:
+ return !isGFX11Plus(STI);
+ case ET_POS4:
+ case ET_PRIM:
+ return isGFX10Plus(STI);
+ case ET_DUAL_SRC_BLEND0:
+ case ET_DUAL_SRC_BLEND1:
+ return isGFX11Plus(STI);
+ default:
+ if (Id >= ET_PARAM0 && Id <= ET_PARAM31)
+ return !isGFX11Plus(STI);
+ return true;
+ }
}
} // namespace Exp
diff --git a/llvm/lib/Target/AMDGPU/VIInstrFormats.td b/llvm/lib/Target/AMDGPU/VIInstrFormats.td
index bd65a495fa727..7393ef6c2a2d7 100644
--- a/llvm/lib/Target/AMDGPU/VIInstrFormats.td
+++ b/llvm/lib/Target/AMDGPU/VIInstrFormats.td
@@ -10,7 +10,7 @@
//
//===----------------------------------------------------------------------===//
-class EXPe_vi : EXPe {
+class EXPe_vi : EXPe_ComprVM {
let Inst{31-26} = 0x31; //encoding
}
diff --git a/llvm/test/MC/AMDGPU/exp-err.s b/llvm/test/MC/AMDGPU/exp-err.s
index bab0434c8dec0..630f8558d6993 100644
--- a/llvm/test/MC/AMDGPU/exp-err.s
+++ b/llvm/test/MC/AMDGPU/exp-err.s
@@ -1,11 +1,12 @@
-// RUN: not llvm-mc -arch=amdgcn %s 2>&1 | FileCheck -check-prefix=GCN --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga %s 2>&1 | FileCheck -check-prefix=GCN --implicit-check-not=error: %s
+// RUN: not llvm-mc -arch=amdgcn %s 2>&1 | FileCheck -check-prefixes=GCN,GFX68 --implicit-check-not=error: %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga %s 2>&1 | FileCheck -check-prefixes=GCN,GFX68 --implicit-check-not=error: %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 %s 2>&1 | FileCheck -check-prefixes=GCN,GFX11 --implicit-check-not=error: %s
exp mrt8 v3, v2, v1, v0
// GCN: :5: error: invalid exp target
exp pos4 v3, v2, v1, v0
-// GCN: :5: error: exp target is not supported on this GPU
+// GFX68: :5: error: exp target is not supported on this GPU
exp pos5 v3, v2, v1, v0
// GCN: :5: error: invalid exp target
@@ -117,3 +118,18 @@ exp mrt0 v0, v0, 0x12345678, v0
exp mrt0 v0, v0, v0, 0x12345678
// GCN: 22: error: invalid operand for instruction
+
+exp null v4, v3, v2, v1
+// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: exp target is not supported on this GPU
+
+exp param0 v4, v3, v2, v1
+// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: exp target is not supported on this GPU
+
+exp param31 v4, v3, v2, v1
+// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: exp target is not supported on this GPU
+
+exp mrt0 v4, v3, v2, v1 vm
+// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+exp mrtz, v3, v3, off, off compr
+// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
diff --git a/llvm/test/MC/AMDGPU/exp-gfx10.s b/llvm/test/MC/AMDGPU/exp-gfx10.s
index c64278ff1547e..0d28b654d8190 100644
--- a/llvm/test/MC/AMDGPU/exp-gfx10.s
+++ b/llvm/test/MC/AMDGPU/exp-gfx10.s
@@ -1,15 +1,19 @@
// RUN: not llvm-mc -arch=amdgcn -mcpu=verde %s 2>&1 | FileCheck -check-prefix=SIVI --implicit-check-not=error: %s
// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga %s 2>&1 | FileCheck -check-prefix=SIVI --implicit-check-not=error: %s
// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -show-encoding %s | FileCheck -check-prefix=GFX10 %s
+// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -show-encoding %s | FileCheck -check-prefix=GFX11 %s
exp prim v1, off, off, off
// SIVI: :5: error: exp target is not supported on this GPU
// GFX10: exp prim v1, off, off, off ; encoding: [0x41,0x01,0x00,0xf8,0x01,0x00,0x00,0x00]
+// GFX11: exp prim v1, off, off, off ; encoding: [0x41,0x01,0x00,0xf8,0x01,0x00,0x00,0x00]
exp prim v2, v3, off, off
// SIVI: :5: error: exp target is not supported on this GPU
// GFX10: exp prim v2, v3, off, off ; encoding: [0x43,0x01,0x00,0xf8,0x02,0x03,0x00,0x00]
+// GFX11: exp prim v2, v3, off, off ; encoding: [0x43,0x01,0x00,0xf8,0x02,0x03,0x00,0x00]
exp pos4 v4, v3, v2, v1
// SIVI: error: exp target is not supported on this GPU
// GFX10: exp pos4 v4, v3, v2, v1 ; encoding: [0x0f,0x01,0x00,0xf8,0x04,0x03,0x02,0x01]
+// GFX11: exp pos4 v4, v3, v2, v1 ; encoding: [0x0f,0x01,0x00,0xf8,0x04,0x03,0x02,0x01]
diff --git a/llvm/test/MC/AMDGPU/exp-gfx11.s b/llvm/test/MC/AMDGPU/exp-gfx11.s
new file mode 100644
index 0000000000000..577e800811f6c
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/exp-gfx11.s
@@ -0,0 +1,19 @@
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 %s 2>&1 | FileCheck -check-prefix=PREGFX11 --implicit-check-not=error: %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 %s 2>&1 | FileCheck -check-prefix=PREGFX11 --implicit-check-not=error: %s
+// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -show-encoding %s | FileCheck -check-prefix=GFX11 --implicit-check-not=error: %s
+
+exp dual_src_blend0 v4, v3, v2, v1
+// PREGFX11: :[[@LINE-1]]:{{[0-9]+}}: error: exp target is not supported on this GPU
+// GFX11: exp dual_src_blend0 v4, v3, v2, v1 ; encoding: [0x5f,0x01,0x00,0xf8,0x04,0x03,0x02,0x01]
+
+exp dual_src_blend1 v2, v3, off, off
+// PREGFX11: :[[@LINE-1]]:{{[0-9]+}}: error: exp target is not supported on this GPU
+// GFX11: exp dual_src_blend1 v2, v3, off, off ; encoding: [0x63,0x01,0x00,0xf8,0x02,0x03,0x00,0x00]
+
+exp mrtz v4, v3, v2, v1 row_en
+// PREGFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+// GFX11: exp mrtz v4, v3, v2, v1 row_en ; encoding: [0x8f,0x20,0x00,0xf8,0x04,0x03,0x02,0x01]
+
+exp mrtz v4, v3, off, off done row_en
+// PREGFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+// GFX11: exp mrtz v4, v3, off, off done row_en ; encoding: [0x83,0x28,0x00,0xf8,0x04,0x03,0x00,0x00]
diff --git a/llvm/test/MC/AMDGPU/exp-pregfx11.s b/llvm/test/MC/AMDGPU/exp-pregfx11.s
new file mode 100644
index 0000000000000..8a8d0bfc42ef4
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/exp-pregfx11.s
@@ -0,0 +1,59 @@
+// RUN: llvm-mc -arch=amdgcn -show-encoding %s | FileCheck -check-prefix=SI %s
+// RUN: llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck -check-prefix=GFX89 %s
+// RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck -check-prefix=GFX89 %s
+// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -show-encoding %s | FileCheck -check-prefix=GFX10 %s
+
+exp null v4, v3, v2, v1
+// SI: exp null v4, v3, v2, v1 ; encoding: [0x9f,0x00,0x00,0xf8,0x04,0x03,0x02,0x01]
+// GFX89: exp null v4, v3, v2, v1 ; encoding: [0x9f,0x00,0x00,0xc4,0x04,0x03,0x02,0x01]
+// GFX10: exp null v4, v3, v2, v1 ; encoding: [0x9f,0x00,0x00,0xf8,0x04,0x03,0x02,0x01]
+
+exp null v4, v3, v2, v1 done
+// SI: exp null v4, v3, v2, v1 done ; encoding: [0x9f,0x08,0x00,0xf8,0x04,0x03,0x02,0x01]
+// GFX89: exp null v4, v3, v2, v1 done ; encoding: [0x9f,0x08,0x00,0xc4,0x04,0x03,0x02,0x01]
+// GFX10: exp null v4, v3, v2, v1 done ; encoding: [0x9f,0x08,0x00,0xf8,0x04,0x03,0x02,0x01]
+
+exp param0 v4, v3, v2, v1
+// SI: exp param0 v4, v3, v2, v1 ; encoding: [0x0f,0x02,0x00,0xf8,0x04,0x03,0x02,0x01]
+// GFX89: exp param0 v4, v3, v2, v1 ; encoding: [0x0f,0x02,0x00,0xc4,0x04,0x03,0x02,0x01]
+// GFX10: exp param0 v4, v3, v2, v1 ; encoding: [0x0f,0x02,0x00,0xf8,0x04,0x03,0x02,0x01]
+
+exp param0 v4, v3, v2, v1 done
+// SI: exp param0 v4, v3, v2, v1 done ; encoding: [0x0f,0x0a,0x00,0xf8,0x04,0x03,0x02,0x01]
+// GFX89: exp param0 v4, v3, v2, v1 done ; encoding: [0x0f,0x0a,0x00,0xc4,0x04,0x03,0x02,0x01]
+// GFX10: exp param0 v4, v3, v2, v1 done ; encoding: [0x0f,0x0a,0x00,0xf8,0x04,0x03,0x02,0x01]
+
+exp param31 v4, v3, v2, v1
+// SI: exp param31 v4, v3, v2, v1 ; encoding: [0xff,0x03,0x00,0xf8,0x04,0x03,0x02,0x01]
+// GFX89: exp param31 v4, v3, v2, v1 ; encoding: [0xff,0x03,0x00,0xc4,0x04,0x03,0x02,0x01]
+// GFX10: exp param31 v4, v3, v2, v1 ; encoding: [0xff,0x03,0x00,0xf8,0x04,0x03,0x02,0x01]
+
+exp param31 v4, v3, v2, v1 done
+// SI: exp param31 v4, v3, v2, v1 done ; encoding: [0xff,0x0b,0x00,0xf8,0x04,0x03,0x02,0x01]
+// GFX89: exp param31 v4, v3, v2, v1 done ; encoding: [0xff,0x0b,0x00,0xc4,0x04,0x03,0x02,0x01]
+// GFX10: exp param31 v4, v3, v2, v1 done ; encoding: [0xff,0x0b,0x00,0xf8,0x04,0x03,0x02,0x01]
+
+exp mrt0 v4, v3, v2, v1 vm
+// SI: exp mrt0 v4, v3, v2, v1 vm ; encoding: [0x0f,0x10,0x00,0xf8,0x04,0x03,0x02,0x01]
+// GFX89: exp mrt0 v4, v3, v2, v1 vm ; encoding: [0x0f,0x10,0x00,0xc4,0x04,0x03,0x02,0x01]
+// GFX10: exp mrt0 v4, v3, v2, v1 vm ; encoding: [0x0f,0x10,0x00,0xf8,0x04,0x03,0x02,0x01]
+
+exp mrt0 v4, v3, v2, v1 done vm
+// SI: exp mrt0 v4, v3, v2, v1 done vm ; encoding: [0x0f,0x18,0x00,0xf8,0x04,0x03,0x02,0x01]
+// GFX89: exp mrt0 v4, v3, v2, v1 done vm ; encoding: [0x0f,0x18,0x00,0xc4,0x04,0x03,0x02,0x01]
+// GFX10: exp mrt0 v4, v3, v2, v1 done vm ; encoding: [0x0f,0x18,0x00,0xf8,0x04,0x03,0x02,0x01]
+
+exp mrtz, v3, v3, v7, v7 compr
+// SI: exp mrtz v3, v3, v7, v7 compr ; encoding: [0x8f,0x04,0x00,0xf8,0x03,0x07,0x00,0x00]
+// GFX89: exp mrtz v3, v3, v7, v7 compr ; encoding: [0x8f,0x04,0x00,0xc4,0x03,0x07,0x00,0x00]
+// GFX10: exp mrtz v3, v3, v7, v7 compr ; encoding: [0x8f,0x04,0x00,0xf8,0x03,0x07,0x00,0x00]
+
+exp mrtz, off, off, v7, v7 compr
+// SI: exp mrtz off, off, v7, v7 compr ; encoding: [0x8c,0x04,0x00,0xf8,0x00,0x07,0x00,0x00]
+// GFX89: exp mrtz off, off, v7, v7 compr ; encoding: [0x8c,0x04,0x00,0xc4,0x00,0x07,0x00,0x00]
+// GFX10: exp mrtz off, off, v7, v7 compr ; encoding: [0x8c,0x04,0x00,0xf8,0x00,0x07,0x00,0x00]
+
+exp mrtz, v3, v3, off, off compr
+// SI: exp mrtz v3, v3, off, off compr ; encoding: [0x83,0x04,0x00,0xf8,0x03,0x00,0x00,0x00]
+// GFX89: exp mrtz v3, v3, off, off compr ; encoding: [0x83,0x04,0x00,0xc4,0x03,0x00,0x00,0x00]
+// GFX10: exp mrtz v3, v3, off, off compr ; encoding: [0x83,0x04,0x00,0xf8,0x03,0x00,0x00,0x00]
diff --git a/llvm/test/MC/AMDGPU/exp.s b/llvm/test/MC/AMDGPU/exp.s
index a1d106b3c2aaa..321075057a21a 100644
--- a/llvm/test/MC/AMDGPU/exp.s
+++ b/llvm/test/MC/AMDGPU/exp.s
@@ -2,6 +2,7 @@
// RUN: llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck -check-prefix=GFX89 %s
// RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck -check-prefix=GFX89 %s
// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -show-encoding %s | FileCheck -check-prefix=GFX10 %s
+// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -show-encoding %s | FileCheck -check-prefix=GFX10 %s
exp mrt0 off, off, off, off
// SI: exp mrt0 off, off, off, off ; encoding: [0x00,0x00,0x00,0xf8,0x00,0x00,0x00,0x00]
@@ -83,16 +84,6 @@ exp mrtz v4, v3, v2, v1 done
// GFX89: exp mrtz v4, v3, v2, v1 done ; encoding: [0x8f,0x08,0x00,0xc4,0x04,0x03,0x02,0x01]
// GFX10: exp mrtz v4, v3, v2, v1 done ; encoding: [0x8f,0x08,0x00,0xf8,0x04,0x03,0x02,0x01]
-exp null v4, v3, v2, v1
-// SI: exp null v4, v3, v2, v1 ; encoding: [0x9f,0x00,0x00,0xf8,0x04,0x03,0x02,0x01]
-// GFX89: exp null v4, v3, v2, v1 ; encoding: [0x9f,0x00,0x00,0xc4,0x04,0x03,0x02,0x01]
-// GFX10: exp null v4, v3, v2, v1 ; encoding: [0x9f,0x00,0x00,0xf8,0x04,0x03,0x02,0x01]
-
-exp null v4, v3, v2, v1 done
-// SI: exp null v4, v3, v2, v1 done ; encoding: [0x9f,0x08,0x00,0xf8,0x04,0x03,0x02,0x01]
-// GFX89: exp null v4, v3, v2, v1 done ; encoding: [0x9f,0x08,0x00,0xc4,0x04,0x03,0x02,0x01]
-// GFX10: exp null v4, v3, v2, v1 done ; encoding: [0x9f,0x08,0x00,0xf8,0x04,0x03,0x02,0x01]
-
exp pos0 v4, v3, v2, v1
// SI: exp pos0 v4, v3, v2, v1 ; encoding: [0xcf,0x00,0x00,0xf8,0x04,0x03,0x02,0x01]
// GFX89: exp pos0 v4, v3, v2, v1 ; encoding: [0xcf,0x00,0x00,0xc4,0x04,0x03,0x02,0x01]
@@ -112,48 +103,3 @@ exp pos3 v4, v3, v2, v1 done
// SI: exp pos3 v4, v3, v2, v1 done ; encoding: [0xff,0x08,0x00,0xf8,0x04,0x03,0x02,0x01]
// GFX89: exp pos3 v4, v3, v2, v1 done ; encoding: [0xff,0x08,0x00,0xc4,0x04,0x03,0x02,0x01]
// GFX10: exp pos3 v4, v3, v2, v1 done ; encoding: [0xff,0x08,0x00,0xf8,0x04,0x03,0x02,0x01]
-
-exp param0 v4, v3, v2, v1
-// SI: exp param0 v4, v3, v2, v1 ; encoding: [0x0f,0x02,0x00,0xf8,0x04,0x03,0x02,0x01]
-// GFX89: exp param0 v4, v3, v2, v1 ; encoding: [0x0f,0x02,0x00,0xc4,0x04,0x03,0x02,0x01]
-// GFX10: exp param0 v4, v3, v2, v1 ; encoding: [0x0f,0x02,0x00,0xf8,0x04,0x03,0x02,0x01]
-
-exp param0 v4, v3, v2, v1 done
-// SI: exp param0 v4, v3, v2, v1 done ; encoding: [0x0f,0x0a,0x00,0xf8,0x04,0x03,0x02,0x01]
-// GFX89: exp param0 v4, v3, v2, v1 done ; encoding: [0x0f,0x0a,0x00,0xc4,0x04,0x03,0x02,0x01]
-// GFX10: exp param0 v4, v3, v2, v1 done ; encoding: [0x0f,0x0a,0x00,0xf8,0x04,0x03,0x02,0x01]
-
-exp param31 v4, v3, v2, v1
-// SI: exp param31 v4, v3, v2, v1 ; encoding: [0xff,0x03,0x00,0xf8,0x04,0x03,0x02,0x01]
-// GFX89: exp param31 v4, v3, v2, v1 ; encoding: [0xff,0x03,0x00,0xc4,0x04,0x03,0x02,0x01]
-// GFX10: exp param31 v4, v3, v2, v1 ; encoding: [0xff,0x03,0x00,0xf8,0x04,0x03,0x02,0x01]
-
-exp param31 v4, v3, v2, v1 done
-// SI: exp param31 v4, v3, v2, v1 done ; encoding: [0xff,0x0b,0x00,0xf8,0x04,0x03,0x02,0x01]
-// GFX89: exp param31 v4, v3, v2, v1 done ; encoding: [0xff,0x0b,0x00,0xc4,0x04,0x03,0x02,0x01]
-// GFX10: exp param31 v4, v3, v2, v1 done ; encoding: [0xff,0x0b,0x00,0xf8,0x04,0x03,0x02,0x01]
-
-exp mrt0 v4, v3, v2, v1 vm
-// SI: exp mrt0 v4, v3, v2, v1 vm ; encoding: [0x0f,0x10,0x00,0xf8,0x04,0x03,0x02,0x01]
-// GFX89: exp mrt0 v4, v3, v2, v1 vm ; encoding: [0x0f,0x10,0x00,0xc4,0x04,0x03,0x02,0x01]
-// GFX10: exp mrt0 v4, v3, v2, v1 vm ; encoding: [0x0f,0x10,0x00,0xf8,0x04,0x03,0x02,0x01]
-
-exp mrt0 v4, v3, v2, v1 done vm
-// SI: exp mrt0 v4, v3, v2, v1 done vm ; encoding: [0x0f,0x18,0x00,0xf8,0x04,0x03,0x02,0x01]
-// GFX89: exp mrt0 v4, v3, v2, v1 done vm ; encoding: [0x0f,0x18,0x00,0xc4,0x04,0x03,0x02,0x01]
-// GFX10: exp mrt0 v4, v3, v2, v1 done vm ; encoding: [0x0f,0x18,0x00,0xf8,0x04,0x03,0x02,0x01]
-
-exp mrtz, v3, v3, v7, v7 compr
-// SI: exp mrtz v3, v3, v7, v7 compr ; encoding: [0x8f,0x04,0x00,0xf8,0x03,0x07,0x00,0x00]
-// GFX89: exp mrtz v3, v3, v7, v7 compr ; encoding: [0x8f,0x04,0x00,0xc4,0x03,0x07,0x00,0x00]
-// GFX10: exp mrtz v3, v3, v7, v7 compr ; encoding: [0x8f,0x04,0x00,0xf8,0x03,0x07,0x00,0x00]
-
-exp mrtz, off, off, v7, v7 compr
-// SI: exp mrtz off, off, v7, v7 compr ; encoding: [0x8c,0x04,0x00,0xf8,0x00,0x07,0x00,0x00]
-// GFX89: exp mrtz off, off, v7, v7 compr ; encoding: [0x8c,0x04,0x00,0xc4,0x00,0x07,0x00,0x00]
-// GFX10: exp mrtz off, off, v7, v7 compr ; encoding: [0x8c,0x04,0x00,0xf8,0x00,0x07,0x00,0x00]
-
-exp mrtz, v3, v3, off, off compr
-// SI: exp mrtz v3, v3, off, off compr ; encoding: [0x83,0x04,0x00,0xf8,0x03,0x00,0x00,0x00]
-// GFX89: exp mrtz v3, v3, off, off compr ; encoding: [0x83,0x04,0x00,0xc4,0x03,0x00,0x00,0x00]
-// GFX10: exp mrtz v3, v3, off, off compr ; encoding: [0x83,0x04,0x00,0xf8,0x03,0x00,0x00,0x00]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/exp_gfx11.txt b/llvm/test/MC/Disassembler/AMDGPU/exp_gfx11.txt
new file mode 100644
index 0000000000000..ffdd30597ddd8
--- /dev/null
+++ b/llvm/test/MC/Disassembler/AMDGPU/exp_gfx11.txt
@@ -0,0 +1,13 @@
+# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -disassemble -show-encoding < %s | FileCheck -strict-whitespace %s -check-prefix=GFX11
+
+# GFX11: exp dual_src_blend0 v4, v3, v2, v1 ; encoding: [0x5f,0x01,0x00,0xf8,0x04,0x03,0x02,0x01]
+0x5f,0x01,0x00,0xf8,0x04,0x03,0x02,0x01
+
+# GFX11: exp dual_src_blend1 v2, v3, off, off ; encoding: [0x63,0x01,0x00,0xf8,0x02,0x03,0x00,0x00]
+0x63,0x01,0x00,0xf8,0x02,0x03,0x00,0x00
+
+# GFX11: exp mrtz v4, v3, v2, v1 row_en ; encoding: [0x8f,0x20,0x00,0xf8,0x04,0x03,0x02,0x01]
+0x8f,0x20,0x00,0xf8,0x04,0x03,0x02,0x01
+
+# GFX11: exp mrtz v4, v3, off, off done row_en ; encoding: [0x83,0x28,0x00,0xf8,0x04,0x03,0x00,0x00]
+0x83,0x28,0x00,0xf8,0x04,0x03,0x00,0x00
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