[PATCH] D124612: [AArch64][LV] AArch64 does not prefer vectorized addressing

[Dave Green via Phabricator via llvm-commits]

dmgreen added a comment.

Thanks for getting the numbers.



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Comment at: llvm/test/Transforms/LoopVectorize/AArch64/interleaved-vs-scalar.ll:13
 ; CHECK: vector.body
-; CHECK: load <4 x i8>
+; CHECK: load i8
 ; CHECK: br i1 {{.*}}, label %middle.block, label %vector.body
----------------
dmgreen wrote:
> It is hard to see why this is now correct.. the vector body looks pretty empty?
Do you know what is going on in this case?


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https://reviews.llvm.org/D124612