[PATCH] D126356: [tests] precommit tests for D126040
Allen zhong via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed May 25 00:56:45 PDT 2022
Allen created this revision.
Allen added a reviewer: spatel.
Herald added a project: All.
Allen requested review of this revision.
Herald added a project: LLVM.
Herald added a subscriber: llvm-commits.
https://reviews.llvm.org/D126356
Files:
llvm/test/Transforms/InstCombine/mul-masked-bits.ll
Index: llvm/test/Transforms/InstCombine/mul-masked-bits.ll
===================================================================
--- llvm/test/Transforms/InstCombine/mul-masked-bits.ll
+++ llvm/test/Transforms/InstCombine/mul-masked-bits.ll
@@ -163,3 +163,60 @@
%and = and i33 %mul, 7
ret i33 %and
}
+
+; Instcombine should be able to simplify mul operator.
+
+; Scalar tests
+define i64 @scalar_mul_bit_x0_y0(i64 %x, i64 %y) {
+; CHECK-LABEL: @scalar_mul_bit_x0_y0(
+; CHECK-NEXT: [[AND1:%.*]] = and i64 [[X:%.*]], 1
+; CHECK-NEXT: [[AND2:%.*]] = and i64 [[Y:%.*]], 1
+; CHECK-NEXT: [[MUL:%.*]] = mul nuw nsw i64 [[AND1]], [[AND2]]
+; CHECK-NEXT: ret i64 [[MUL]]
+;
+ %and1 = and i64 %x, 1
+ %and2 = and i64 %y, 1
+ %mul = mul i64 %and1, %and2
+ ret i64 %mul
+}
+
+; Negative test
+define i64 @scalar_mul_bit_x0_y1(i64 %x, i64 %y) {
+; CHECK-LABEL: @scalar_mul_bit_x0_y1(
+; CHECK-NEXT: [[AND1:%.*]] = and i64 [[X:%.*]], 1
+; CHECK-NEXT: [[AND2:%.*]] = and i64 [[Y:%.*]], 2
+; CHECK-NEXT: [[MUL:%.*]] = mul nuw nsw i64 [[AND1]], [[AND2]]
+; CHECK-NEXT: ret i64 [[MUL]]
+;
+ %and1 = and i64 %x, 1
+ %and2 = and i64 %y, 2
+ %mul = mul i64 %and1, %and2
+ ret i64 %mul
+}
+
+define i64 @scalar_mul_bit_x0_yC(i64 %x, i64 %y, i64 %c) {
+; CHECK-LABEL: @scalar_mul_bit_x0_yC(
+; CHECK-NEXT: [[AND1:%.*]] = and i64 [[X:%.*]], 1
+; CHECK-NEXT: [[AND2:%.*]] = and i64 [[Y:%.*]], [[C:%.*]]
+; CHECK-NEXT: [[MUL:%.*]] = mul nuw i64 [[AND1]], [[AND2]]
+; CHECK-NEXT: ret i64 [[MUL]]
+;
+ %and1 = and i64 %x, 1
+ %and2 = and i64 %y, %c
+ %mul = mul i64 %and1, %and2
+ ret i64 %mul
+}
+
+; Vector tests
+define <2 x i64> @vector_mul_bit_x0_y0(<2 x i64> %x, <2 x i64> %y) {
+; CHECK-LABEL: @vector_mul_bit_x0_y0(
+; CHECK-NEXT: [[AND1:%.*]] = and <2 x i64> [[X:%.*]], <i64 1, i64 1>
+; CHECK-NEXT: [[AND2:%.*]] = and <2 x i64> [[Y:%.*]], <i64 1, i64 1>
+; CHECK-NEXT: [[MUL:%.*]] = mul nuw nsw <2 x i64> [[AND1]], [[AND2]]
+; CHECK-NEXT: ret <2 x i64> [[MUL]]
+;
+ %and1 = and <2 x i64> %x, <i64 1, i64 1>
+ %and2 = and <2 x i64> %y, <i64 1, i64 1>
+ %mul = mul <2 x i64> %and1, %and2
+ ret <2 x i64> %mul
+}
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